JPH0338902A - Digital sinusoidal wave function series generating circuit - Google Patents

Abstract

PURPOSE:To prevent overflow oscillation phenomenon, to reduce the chip area and to attain high speed operation by inputting an output signal to a coefficient correction input of a multiplier through a decision circuit. CONSTITUTION:The circuit is provided with an adder 1 adding an input signal IN, a 1st multiplication signal MP1 and a 2nd multiplication signal MP2, and outputting an output signal OUT of a digital sinusoidal wave function series, a 1st delay circuit 2 retarding the output signal OUT by a prescribed time, and a 2nd delay circuit 3 retarding the output signal by a prescribed time. Moreover, 2nd multipliers 4, 5 multiplying a coefficient with output signals of the 1st and 2nd delay circuits 2, 3 and a decision circuit 6 generating a coefficient in response to the output signal OUT of the adder 1 are provided. Thus, the digital sinusoidal wave function series generating circuit with a small area and operated at high speed is obtained without overflow oscillation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital sine wave function sequence generation circuit, and more particularly to a digital sine wave function sequence generation circuit applied to system control and the like.

[Conventional technology]

A typical example of a conventional digital sine wave function series generating circuit of this type is shown in FIG.

The configuration of this system is to convert the sine wave function value for one period into RO
The function value is stored in the M section 14, and the address of the ROM section 14 is sequentially designated by the address counter 10 to read out the function value.

The input signal IN is connected to one input terminal of the adder 11, the output of the adder 11 is connected to the input of the changing circuit 12,
The output of the change circuit 12 is shifted by the shift register 13 using the clock signal GK, and the output of the shift register 13 becomes the address input of the ROM 14. It is also input to the other input terminal of the adder 11, and the output of the ROM 14 is converted into a digital sine wave. This becomes the output signal OUT of the function series.

Next, the operation of this circuit will be explained.

When one period of the sine wave function series is 21 (a...integer), the address counter 10 is an a-bit parallel adder 11.
fa bit shift register 13, and by giving the numerical value n (0 to 2°-1) of the input signal IN to the address counter 10, the output frequency is determined by n of the sampling clock frequency f of the clock signal CK.・2
It can be arbitrarily set to -1.

If it is necessary to set the basic period to an arbitrary integer, the output of the a-bit parallel adder 11 is changed through a change circuit 12 and inputted to the ROM section 14.

[Problem to be solved by the invention]

The conventional digital sine wave function sequence generation circuit described above is
Since one cycle of the sine wave function value is stored in the ROM section 14, there is a drawback that the chaff area becomes large and high speed operation is not possible.

SUMMARY OF THE INVENTION An object of the present invention is to provide a digital sine wave function sequence generation circuit that requires a small area and operates at high speed.

[Means to solve the problem]

The digital sine wave function sequence generation circuit of the present invention includes an adder that adds an input signal, a first multiplication signal, and a second multiplication signal to produce an output signal of a digital sine wave function sequence; a first delay circuit that delays the output signal of the first delay circuit by a predetermined time; and a second delay circuit that delays the output signal of the first delay circuit by a predetermined time.
a first multiplier that multiplies the output signal of the first delay circuit by a first coefficient and outputs the first multiplied signal; a second multiplier that multiplies the second multiplication signal by a coefficient of 2 and outputs the second multiplication signal; and a determination circuit that generates the first and second coefficients according to the output signal of the adder. There is.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

This embodiment includes an adder l that adds an input signal IN, a first multiplication signal MP, and a second multiplication signal MPz to produce an output signal OUT of a digital sine wave function series, and an output signal O.
A first delay circuit 2 that delays the UT by a predetermined time (z"") and an output signal of this first delay circuit 2 for a predetermined time (z"").
z-') a second delay circuit 3 that delays the output signal, and a first multiplier that multiplies the output signal of the first delay circuit 2 by a first coefficient (b+) and outputs a first multiplication signal MP. 4, a second multiplier 5 that multiplies the output signal of the second delay circuit 3 by a second coefficient (-b2) and outputs a second multiplication signal MP2, and an output signal OUT of the adder l. The first and second coefficients (
-b+, -bz).

Next, regarding the operation of this embodiment, FIGS. 2 and 3 (
This will be explained with reference to a) to (d).

First, consider the operation of a second-order IIR digital filter.

The difference equation of the second-order IIR digital filter is (1)
It is expressed by the formula.

y (n) = x (n) -b 1y(n-1) -b
zy (n-2) (1) Equation (1) is converted into two to obtain H(z), resulting in Equation (2).

H(z) = 1+b+z−'+tgz−” ・・・・・・(2) Consider the case where the root of the denominator polynomial in equation (2) is a complex number 1
, H(z) is expanded into partial fractions to give equation (3).

Here α.

P is α.

each conjugate complex number of P It is.

(3) Equation transformation and, To investigate the impulse response of H(z), let H(z) be After performing the inverse 2 transformation, equation (5) is obtained.

This is a relationship of a reduced width sine wave, and the closer r is to 1, the smaller the degree of width reduction. Also, the larger φ is, the higher the frequency of vibration is.

Figure 2 shows four types of pole arrangements on two planes (z = u + jv), and Figures 3 (a) to (d) show the impulse response h (n) for each pole arrangement. It is.

The arrangement of point A in FIG. 2 is rA=Q, 7. φ4=−π, which shows the impulse response of state A in FIG. 3(a). With this characteristic, even if n increases, the impulse response quickly converges.

The pole arrangement of point B in FIG. 2 is rn=0.9. φ8−π, which shows the impulse response of state B in FIG.
, is larger than φ, so the vibration frequency is high.

The pole arrangement of the 0 point in FIG. 2 is rc=1.0. φ. =-π = 6 The impulse response of state C in FIG. 3(C) is shown.

This characteristic is a cosine wave function with an amplitude of 1.0, indicating an oscillation state. However, the amplitude of the oscillation output depends on the coefficients and initial values, and the system does not have a steady stable point that is automatically determined, so it is not stable against disturbances.

Furthermore, the period of the cosine wave can be freely set by changing the coefficients b2.

The pole arrangement of point D in FIG. 2 is rD=1.5. φゎ=−π, and the impulse response in the state shown in FIG. 3(d) is shown. This characteristic indicates an oscillation state and is not a stable state.

From the above results, by limiting the value of r, the convergent stable state A,
It is necessary to operate at a stability limit value between B and the unstable oscillation state. For this purpose, the output results are fed back, and the determination circuit 6 sets a multiplier coefficient that always reaches the stability limit, and inputs the value to the coefficient correction terminals of the multipliers 4 and 5.

By doing this, the impulse response characteristic becomes
A sine wave function series such as the states shown in FIGS. (a) to (d) can be realized without causing an overflow oscillation phenomenon in which overflows induce subsequent overflows one after another and the characteristics are significantly deteriorated.

By using the above configuration, it is possible to generate a digital sine wave function sequence with a circuit that does not include memory (ROM section), so the chip area used for memory (
(circuit area) can be reduced. Furthermore, since the delay caused by the memory circuit can be reduced, high-speed operation is possible.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

In this second embodiment, the decision circuit 6 of the first embodiment is divided into two decision circuits 7 and 8, and the value of r is determined first, and then the phase This configuration has the advantage that φ is determined, and the value of r can be easily corrected, and the value of r can be immediately set to the stability limit value.

〔Effect of the invention〕

As explained above, the present invention prevents the overflow oscillation phenomenon in which overflows cause subsequent overflows one after another and significantly deteriorates the characteristics by inputting the output signal through the determination circuit to the coefficient correction input of the multiplier. Because it can be configured with a circuit that does not include memory, it is possible to reduce the chip area (circuit area) used for memory, and it is also possible to eliminate delays caused by memory circuits, resulting in high-speed operation. The effect is that it is possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention;
3(a) to 3(d) are a plan view and an impulse response diagram for explaining the operation of the embodiment shown in FIG. 1, respectively, and FIG. 4 is a second embodiment of the present invention. FIG. 5 is a block diagram showing an example of a conventional digital sine wave function sequence generation circuit. l... Adder, 2, 3... Delay circuit,
4, 5... Multiplier, 6, 7. Death...Judgment circuit, IO...Address counter, 11...
...adder, 12...change circuit, 13...
...Shift register, 14...ROM section. D: n” 15, '!'o = Shikou Moon Zu Kazu

Claims (1)

[Claims] an adder that adds an input signal, a first multiplication signal, and a second multiplication signal to produce an output signal of a digital sine wave function series; a first delay circuit that delays the output signal for a predetermined time; a second delay circuit that delays the output signal of the first delay circuit for a predetermined time; and a first delay circuit that multiplies the output signal of the first delay circuit by a first coefficient and outputs the first multiplied signal. a multiplier, and a second delay circuit for the output signal of the second delay circuit.
and a determination circuit that generates the first and second coefficients according to the output signal of the adder. A digital sine wave function sequence generation circuit.