JP2869833B2 - Power failure time detection control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a process for erasing so-called daily data when a power outage time (including an artificial power-off time) exceeds a predetermined time in a pachinko game arcade. Further, the present invention relates to an apparatus for detecting whether or not a power outage time exceeds a predetermined time.

[0002]

2. Description of the Related Art In a ball lending machine for a pachinko game, a medal lending machine in various game machines, or a money changer, etc.
Various kinds of totals such as the number of received and lent balls and the number of medals are performed on a daily basis, and the daily total data is stored in the RAM and taken out as needed. Then, the daily total data is cleared for a new totalization of the next day. The clearing of the daily total data is programmed to be performed a predetermined time t after the movement of the machine is stopped. Normally, for example, the daily total data is cleared at about 10:00 pm, about 2 hours after the end of the operation of the machine after business hours, and about 2 hours after the end of the operation of the machine.

The detection of whether or not the power outage time for the above processing is equal to or longer than the predetermined time t is determined by the CR circuit (comprising a large-capacity capacitor) that backs up the RAM in which the daily data is registered. It was performed based on a time constant. That is, the RAM time is determined by the CR time constant.
Are set to operate only for a predetermined time t at the time of power failure, and it is determined whether or not the identification data registered in the RAM at the time of power failure remains when the power is restored.

[0004]

However, the large-capacity capacitor used in the above-mentioned conventional device has a problem in the accuracy of setting the time constant, so that the reliability of the power failure time detection is poor, and the power failure time is within a predetermined time. In such a case, there is a disadvantage that it is difficult to perform accurate processing of retaining data and clearing data when the power failure time exceeds a predetermined time. That is, for example, when the CR time constant is shorter than the predetermined time due to an error, there is a problem that the daily meter data to be held is cleared even though the power failure time is actually shorter than the predetermined time.

As a means for solving this problem, a clock IC that operates even during a power failure by a backup battery is provided, and a means for determining whether or not the power failure time is equal to or longer than a predetermined time t from the count value of the clock IC is considered. However, in this case, there is a problem that the processing of the CPU or the like for making the determination becomes complicated and the determination takes a long time.

[0006] That is, conventionally known processing procedures of this type of time detection by the clock IC are as follows: (1) Clear the time data of the clock IC at the time of power failure (ie, 0
00: 00: 00: 00: 00), time data is read when the power is restored, and it is checked whether it is greater than or equal to t. (2) The clock IC is always operated even when a power failure occurs. Then, the time data at the time of power failure is registered in the RAM which operates even at the time of power failure by the backup power supply, and then the time data of the clock IC at the time of power recovery and the time data at the time of power failure registered in the RAM are compared, and the difference is t or more. In the method (1), when it is checked whether the power outage time is, for example, two hours or more, the processing at the time of the power outage includes the data set as described above. To determine whether two hours have passed since
0, the tenth of the month is zero, the first of the month is zero, the tenth of the day is zero, the first of the day is zero, the tenth of the hour is zero, It is necessary to sequentially check whether the first place of the time is 2 or more, the number of steps of the program and the processing time become longer,
The judgment process at the time of power restoration is complicated. In the case of (2), similar reading of each part of the timepiece IC is required a plurality of times, and furthermore, a process of calculating the difference is required, which is further complicated.

The present invention has been made based on such a background, and it is possible to detect whether or not the power failure time has exceeded a predetermined time by a simple process in a short time and accurately. It is intended to provide a time detection control device.

[0008]

SUMMARY OF THE INVENTION In order to achieve the above object, the gist of the present invention is to provide a backup power supply.
(6) Time of year, month, day, hour, minute, and second to operate even during a power outage
Timing IC and battery backup RAM (12)
To determine whether the power outage time is within a predetermined time t,
Power failure time detection control device that performs control corresponding to each
In the event of a power failure , the power
Is written into the RAM (12), and the inverse value T of the t is written.
(I.e. 1 year -t) check as to set as the initial value of the timer started in the clock IC (15), the ones of the year of the clock IC (15) when the power recovery whether zero or not
ROM (14) storing a program to perform
Execute the program of ROM (14) by CPU (13)
When the power is restored, the identification data is stored in the RAM (12).
If the data cannot be read, the daily total data is deleted and the identification data is deleted.
If the data can be read, the clock IC (15)
Only when the first place of the year is not 0,
A power outage time detection control device characterized in that the power outage time is deleted .

[0009]

When there is a power failure, the processing means sets a value which has been reversed from one year for a predetermined time as an initial value of the start of timekeeping in the timekeeping means. In other words, if the predetermined time is 2 hours and the clock means measures time in units of year, month, day, hour, minute, and second, the clock means is set to December 31, 2000, 22:00:00. When the power is restored, it is determined whether the first place of the year among the time values of the timekeeping means is 0, and
If it is determined that the power outage time is within the predetermined time,
If not, it is determined that the power outage time is equal to or longer than the predetermined time, but this is a simple and accurate determination based on the clock value. That is, in the case of the previous example, the first place of the year is always 0 unless the power outage time reaches just 2 hours, and the first place in the year is not always 0 if the power outage time is 2 hours or more, The determination is completed only by reading the value.

[0010]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a power failure time detection control device according to an embodiment of the present invention. A one-chip CPU 13 having a battery backup RAM 12 built in on a substrate 11 constituting a main part of the device is shown in FIGS. A ROM 14 in which an operation program of the CPU 13 is written, a clock IC 15, a backup power supply 6 for backing up the clock IC and the RAM 12 in the event of a power failure, and the like are incorporated. A DC power supply circuit 17 is connected to the substrate 11.

The RAM 12 is storage means for storing daily data. The CPU 13 is constituted by a microprocessor or the like, and is a processing means of the present invention. The CPU 13 receives the power failure signal Ps input from the DC power supply circuit 17 and stores predetermined identification data in the RAM 1.
2 and a value which is reversed from one year by a predetermined time t is set in the clock IC 15 as an initial value for starting time measurement. If the identification data cannot be read from the RAM 12 when the power is restored, the daily total data is erased. If the identification data can be read, the daily total data is deleted only when the first place of the year of the time value of the clock IC 15 is not 0. The clock IC 15 measures time in units of year, month, day, hour, minute, and second, and is a timekeeping unit of the present invention.

A DC power supply circuit 17 is connected to an AC power supply, and is a DC power supply circuit for applying a drive voltage Vcc to the CPU 13 by closing a switch 18. The DC power supply circuit 17 sends the power failure signal PS for notifying of power-off and power-on to the CPU 13. Output. In addition, the power failure signal PS is transmitted to a later-described step S31.
Drive voltage Vc until the CPU 13 completes the processing of
In order that c does not fall, its output falls slightly before the power failure (power failure signal output) and its output rises when the power is turned on (power failure recovery signal output). In addition, the backup power supply 16 is formed of a battery having a small arrangement space such as a battery. Further, in the ROM 14, a value that is reversed from one year by the above-mentioned predetermined time t is registered in advance.

Next, the operation will be described. While the AC power of the DC power supply circuit 17 is being supplied, the CPU 13 performs a normal operation. That is, various data (storage data) such as the deposit amount of ball lending machines, the number of lending balls, the number of medals, etc. in a pachinko game hall are received from the outside (ball lending machines, etc.) and RAs are aggregated.
Store it in M12. FIG. 2 is a time chart showing the operation time of the CPU 13, that is, the ON signal of Vcc, data clear, power failure detection timing, and time setting timing. As shown on the left side of FIG. The power failure signal Ps is in the ON state, and the clock IC 15 does not measure time.

Then, as shown in the center position of FIG.
When the power is turned off at the time Tb (for example, at 22:00), the power failure signal Ps from the power supply circuit 17 falls immediately before, and in response to this, the CPU 13 performs the processing at the time of power off shown in FIG. That is, when there is a power failure signal (S31), R
The identification data (for example, “1234”) is written to AM2 (S32), and the above-mentioned value pre-written in the ROM 14, that is, the value reversed from one year by a predetermined time t (“00” when t is two hours). The CPU 13 reads out (23:00:00 'on December 31), sets this in the clock IC 5 as an initial value of the start of timekeeping, and instructs the start of timekeeping (S33).

Next, when the power supply Vcc rises as shown at the right side of FIG. 2, the power failure signal Ps also rises, and in response to this, the CPU 13 performs the processing at the time of power on (at the time of power restoration) shown in FIG. Do. That is, first, it is checked whether or not the identification data is in a good state in the RAM (S41).
If it cannot be read (or if it is not in a perfect state), the daily total data is cleared (S42). If the identification data in the RAM 2 remains in a good state (S4
1) Only when the first place of the year among the time values of the clock IC 15 is not 0, it is determined that the power outage time has passed the predetermined time t (2 hours) and the daily total data is cleared (S32).

Therefore, when the RAM 12 is sufficiently backed up and the daily data remains until the power failure is restored, the identification data registered in the same RAM 12 also remains and can be read out. The process is an accurate and simple determination based on the power failure time accurately measured by the IC 15. That is, when the predetermined time t is 2 hours, the first place of the year of the clock IC 15 is always 0 unless the power outage time does not reach exactly 2 hours or more,
If the power outage time is 2 hours or more, the first place of the year is not always 0, and the determination is completed only by reading the value of this one place.

The backup power supply 16 for the RAM 12
If the daily total data disappears or becomes unreadable by the time of restoration of the power failure due to, for example, exhaustion of the data to a predetermined level or less due to the elapse of a long time, the same RAM 1
Since the identification data registered in No. 2 is of course in the same state and cannot be read, the determination by the CPU 13 is a determination that the daily total data should be surely erased irrespective of the clock result of the clock IC 15. Unnecessary data retention is avoided.

As described above, according to the above-described apparatus, the power failure time can be detected with high accuracy, and the daily meter data can be processed based on the accurate determination. Is significantly reduced. It is needless to say that the above-described operation program of the CPU 13 is written in the ROM 14 and is sequentially read and executed by the CPU 13.

[0019]

As described above, according to the apparatus of the present invention, whether or not the power outage time exceeds the predetermined time can be accurately determined only by judging the first digit of the year of the clock means. For example, the processing at the time of the power failure of the daily total data in the pachinko game hall can be accurately performed in a very short time.

[Brief description of the drawings]

FIG. 1 is a block diagram of a power failure time detection control device according to an embodiment of the present invention.

FIG. 2 is a time chart of a power failure time detection control device according to an embodiment of the present invention.

FIG. 3 is an operation flowchart when power is turned off in one embodiment of the present invention.

FIG. 4 is an operation flowchart when power is restored in one embodiment of the present invention.

[Description of Signs] 11 ... Substrate 12 ... RAM 13 ... CPU (Processing Means) 14 ... ROM 15 ... Clock IC (Clock Means) 16 ... Backup Battery

Continuation of the front page (56) References JP-A-62-269253 (JP, A) JP-A-62-149391 (JP, U) (58) Fields investigated (Int. Cl. ⁶ , DB name) A63F 7 / 02 G06F 1/00 H02J 1/00

Claims (1)

(57) [Claims] 1. Operate even in case of power failure by backup power supply
A timekeeping IC and a battery
Backup RAM to determine if the power outage time is within the specified time t
Judge whether or not to perform control corresponding to each power failure.
The inter-detection control device receives a power failure signal at the time of a power failure and transmits predetermined identification data to the RA.
M, and the inverse value T of the above t (that is, 1 year−t)
Is set in the clock IC as the initial value of the time measurement start.
Both have a ROM storing a program for checking whether or not the first place of the year of the clock IC is 0 when the power is restored.
The ROM program is executed by the CPU and the power is restored.
If the identification data cannot be read from RAM at the time of old
Is a place where the daily data can be erased and the identification data can be read.
Have such in the first place is 0 of the year out of the case the timer value of the clock IC
A power outage time detection control device characterized in that the daily total data is deleted only when the time has elapsed.