JPH077079B2 - Equipment usage time measuring device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a time-of-use timer for displaying the time of use of various devices and, in particular, to a small and inexpensive electronic time-of-day timer.

[Conventional technology]

In a conventional electronic time-of-use timer, particularly a small and inexpensive time-of-use timer, an integrated value of the time-of-use measured is written and held in one memory.

[Problems to be Solved by the Invention]

For this reason, conventionally, since one memory is used, there is a high possibility that the memory is damaged or the writing content is changed due to noise or power fluctuation, and the reliability is low.

It is an object of the present invention to provide a time-of-use clock device that solves this drawback.

[Means for Solving the Problems]

In order to achieve the above-mentioned object, the present invention writes at least three storage memories (hereinafter referred to as memories) and the timekeeping contents to each of the memories at the time of power failure, and at the time of power restoration, reads the memory contents from the memories and reads the contents. The control unit for comparing the stored contents and determining the most coincident stored contents, and the display unit for displaying the determined stored contents are provided.

In addition to the above configuration, operation keys for sequentially reading the stored contents of each memory for each operation and displaying them on the display unit are provided.

[Action]

Normally, the integrated value of the usage time of the device is written in one of the memories and the integrated value is displayed on the display unit. When a power failure occurs, the stored contents of the written memory are also written to other memories. Then, when the power is restored, the stored contents of the memories are read out and compared, the most coincident stored contents are determined, and the determined stored contents are displayed on the display unit. By operating the operation keys, the stored contents of each memory are sequentially read, and the stored contents are displayed on the display unit each time the contents are read.

〔Example〕

Hereinafter, a preferred embodiment in which the present invention is applied to a time-of-use timer for measuring the time of use of a host computer will be described in detail with reference to the accompanying drawings.

Here, FIG. 1 is a schematic block diagram of the apparatus, FIG. 2 is a flow chart showing a control operation of power failure processing, and FIG.
FIG. 4 is a flow chart showing the control operation of power recovery processing, and FIG. 4 is a flow chart showing the control operation of test processing.

As shown in FIG. 1, the clock signal output from the host computer 1 provided with the clock means during use is input to the gate circuit 4 via the input circuit 3 of the usage time clock device 2. . The gate circuit 4 is opened upon receipt of the clock signal, and the reference time signal output from the reference time generation circuit 5 is input to the CPU 6 via the gate circuit 4. A counter for counting the reference time signal is provided in the CPU 6, and the reference time signal is integrated by this counter. Then, the integrated value is displayed on the display unit 7 which performs digital display of 6 digits in 7 segments by using liquid crystal. Also, the CPU6
The internal RAM is provided with three memories A, B, C for writing or reading the integrated value of the reference time signal according to a preset program.

The reset switch 8 provided on the time-of-use timer 2 is CP
This is for setting U6 in a reset state and performing a test display on the display unit 7. For this test display, for each digit in the blank state on the display unit 7, shift the number from "1" to "9" to the right digit, that is, one digit in order from the least significant digit, Numbers are displayed in all digits. When the display feed key 9, which is an operation key, is pressed down in the reset state, the CPU 6 causes each memory A,
The stored contents of B and C are sequentially displayed on the display unit 7. Further, the power supply state to the host computer 1 is detected by the power failure / recovery detection circuit 10 and sent to the CPU 6, and is controlled according to the detected power supply state.

Subsequently, the operation of the embodiment configured as described above will be described.

When the power supply state to the host computer 1 is normal, at the same time when the host computer 1 is used, a clock signal is sent to the gate circuit 4 via the input circuit 3 and the gate circuit 4 is opened to generate the reference time. The reference time signal from the circuit 5 is counted by the counter in the CPU 6 and integrated. Then, the integrated value of the use time is calculated by the three memories A, B,
Of the C, the data is written in the memory A and the display unit 7
In addition, display processing is performed for digital display in units of hours, minutes, and seconds. In addition, in this embodiment, three memories
Since A, B, and C are provided, if the stored contents of the two memories match, the stored contents are compared and the most matched.

Here, the control operation of the CPU 6 at the time of power failure will be described with reference to FIG. After the display processing as described above is performed (step 101), when the power failure / recovery detection circuit 10 detects the power failure state (step 102), the memory A, which is the integrated value of the usage time at that time, is stored. The contents are written in the other memories B and C (step 103), and the process is ended.

Next, the control operation of the CPU 6 at the time of power recovery will be described based on FIG. When the power failure state is restored and the power failure / power recovery detection circuit 10 detects the power recovery state (step 201), first, the stored contents of memories A and B are read (step 202), and the stored contents are compared. Determine if they match (step
203). If it is determined that they match, the stored contents are compared and the largest match is found. Therefore, the stored contents of the memory A are displayed on the display unit 7 as the stored contents at the time of power failure (step 204). Then, the integrated value of the usage time counted by the counter is written in the memory A, and the display process is digitally displayed on the display unit 7 (step 205).
The process ends.

On the other hand, when it is determined in step 203 that the stored contents of the memories A and B do not match, the stored contents of the memory C are read (step 206), and the stored contents and the previously read stored contents of the memory A are compared. It is compared and it is determined whether the two stored contents match (step 207). Here, if it is determined that they match, the stored contents are compared and the largest match is found. Therefore, the process proceeds to step 204, and the stored contents of the memory A are displayed on the display unit 7 as the stored contents at the time of power failure. In step 205, the accumulated value of the usage time counted by the counter is written in the memory A, and the display process is digitally displayed on the display unit 7, and the process is ended.

If it is determined in step 207 that the stored contents of the memories A and C do not match, the stored contents of the memories B and C are compared to determine whether the stored contents match (step 20).
8). If it is determined that they match, the stored contents are compared and the largest match is found. Therefore, while the stored contents of the memory B are displayed on the display unit 7 as the stored contents at the time of power failure, the same contents are stored in the memory A. To correct the different stored contents (step 209). Then, in step 205, the integrated value of the usage time counted by the counter is written in the memory A, and the display process is digitally displayed on the display unit 7 to end the process.

Further, if it is determined in step 208 that the stored contents of the memories B, C do not match, the stored contents of the memories A, B, C will all be different, so the accurate usage time during a power failure An alarm display indicating that the integrated value is not stored in each of the memories A, B, and C is displayed on the display unit 7 (step 210), and the process ends.

Next, the control operation of the CPU 6 in the test process for confirming the stored contents of the memories A, B and C will be described with reference to FIG. When the display feed key 9 is pressed down in the reset state in which the reset switch 8 is turned on (step 301) (step 302), first, the stored contents of the memory A are read out and displayed on the display unit 7 (step 303). ).

On the other hand, if it is determined in step 302 that the display advance key 9 cannot be depressed, the process proceeds to step 304, and a test display is performed on the display unit 7 in the blank state. After this test display is completed, "0" is displayed in the least significant digit and the count input is awaited. If there is a count input (step 305), "1" is displayed in the least significant digit of the display unit 7 (step 306), and the test process ends. Then, the above-described power outage process, which is a normal operation state, is performed.

When the display advance key 9 is depressed after the above-mentioned step 303 (step 307), the process proceeds to step 308, and the stored contents of the memory B are read out and displayed on the display section 7. On the other hand, if the display feed key 9 is not depressed after step 303, the process proceeds from step 307 to step 309, and if it is determined that neither the reset state nor the power failure state is found, the process returns to step 303 to display The stored contents of the memory A are continuously displayed on the section 7, and the process proceeds to step 307. On the other hand, if it is determined in step 309 that the reset state or the power outage state has occurred, the process ends. Then, the above-described power outage process, which is a normal operation state, is performed.

If the display advance key 9 is pressed down following step 308 (step 310), the process proceeds to step 311.
The stored contents of the memory C are read out and displayed on the display unit 7. If the display advance key 9 is not depressed after step 308, step 310 to step 3
When it is determined that the state is neither the reset state nor the power failure state, the process returns to step 308, the stored content of the memory B is continuously displayed on the display unit 7, and the process proceeds to step 310. On the other hand, if it is determined in step 312 that the reset state or the power outage state is reached, the process is terminated. Then, the above-described power outage process, which is a normal operation state, is performed.

Further, when the display advance key 9 is pressed down following the above-mentioned step 311, (step 313), the process returns to step 303 to display the stored contents of the memory A on the display unit 7, and the step 30
Proceed to 7. On the other hand, if the display advance key 9 is not depressed after the step 311, the process proceeds from the step 313 to the step 314, and if it is judged that neither the reset state nor the power failure state is found, the process returns to the step 311. The contents stored in the memory C are continuously displayed, and the process proceeds to step 313.
If it is determined in step 314 that the reset state or the power outage state has occurred, the process is terminated. Then, the above-described power outage process, which is a normal operation state, is performed.

In this way, with the display advance key 9, each memory A, B, C
By displaying the stored content of the above on the display unit 7, it becomes easy to investigate when an alarm is displayed in the power recovery process.

It should be noted that the present invention is not limited to the above-described embodiments, and for example, each memory A, B, C can be provided outside the CPU 6 instead of inside, and the number of memories A, B, C is three. The number is not limited to one, and four or more can be provided. For example, when five memories are provided, the stored contents of each memory are compared two by two as in the above-described embodiment, and the stored contents that are most matched (in this case, at least two and at most three). (If there is a match in the stored contents), it is displayed. Further, the display advance key 9 does not necessarily have to be provided.

〔effect〕

As is clear from the above description, according to the present invention,
By providing three or more memories, the risk of all memories being damaged at the same time is avoided, and the stored contents of each memory are compared when the power is restored and the most matched stored contents are determined and displayed on the display. Therefore, there is an effect that the reliability of the displayed memory content is also improved.

[Brief description of drawings]

FIG. 1 shows a preferred embodiment of the present invention, FIG. 1 is a schematic block diagram of the apparatus, FIG. 2 is a flow chart showing control operation of power failure processing, and FIG. 3 shows control operation of power recovery processing. FIG. 4 is a flow chart showing the control operation of the test process. 1 ... Host computer, 2 ... Used time measuring device,
6 ... CPU, 7 ... display, 8 ... reset switch,
9: Display feed key, 10: Power failure / power recovery detection circuit

Claims (2)

[Claims] 1. A clocking means for clocking the usage time of the device, and a storage memory for storing time data by the clocking means.
In a time-of-use clock device for equipment, which comprises a display unit for displaying time data based on the stored contents of the storage memory, at least three storage memories are provided as the storage memories, while the storage contents are stored in the storage memories at the time of power failure. When the power is restored, the stored contents are read out from each of the storage memories at the time of power recovery, and the read stored contents are compared to determine the most matched stored contents, and the display unit is determined by the control unit. A device for measuring the operating time of a device, comprising: a display unit for displaying stored contents. 2. An operation key for outputting a signal to the control unit each time it is operated is provided, and when a signal is input from this operation key, the control unit sequentially reads the stored contents of each storage memory for each signal input. The device-use time measuring device according to claim 1, characterized in that it is configured to display on a display unit.