JPH05317506A - Power failure time detecting device - Google Patents

Abstract

PURPOSE:To provide the power failure time detecting device which can detect whether the power failure time exceeds a prescribed time or not in a short time exactly with a simple processing. CONSTITUTION:This device is constituted of a time counting means 15 which is operated even at the time of the power failure by a backup power source, and executes time counting by each unit of year, month, day, hour, etc., in which year is the highest level, and a processing means 13 for setting a value obtained by going back from one year by the prescribed time to the time counting means 15 as an initial value for starting time counting at the time of the power failure, deciding whether the top of a year is '0' or not in a time counting value of the time counting means, when a power source is restored, deciding that the power failure time is within the prescribed time if it is '0', and deciding that power failure time exceeds the prescribed time unless it is '0'.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is for carrying out a process of deleting so-called daily total data when a power failure time (including artificial power-off time) exceeds a predetermined time at a pachinko game hall. The present invention relates to a device for detecting whether or not a power failure time has exceeded a predetermined time.

[0002]

2. Description of the Related Art A ball lending machine for pachinko games, a medal lending machine for various game machines, a money changer, etc.
On a daily basis, various types of totalization such as payment, the number of lent balls, the number of medals, etc. are performed, and the daily total data is stored in the RAM and retrieved as needed. Then, this daily total data is cleared for the new aggregation of the next day. The clearing of the daily total data is programmed to be performed after a lapse of a predetermined time t after the movement of the machine is stopped. Normally, for example, the daily total data is set to be cleared at about 2:00 pm, which is about two hours after the operation of the machine ends after the business ends at about 10:00 pm.

Then, the detection of whether or not the power failure time for the above processing has reached the predetermined time t or longer is detected by the CR circuit (which is composed of a large-capacity capacitor) that backs up the RAM in which the daily total data is registered. It was done based on the time constant. That is, the RAM is defined by the CR time constant.
Is set to operate for a predetermined time t at the time of power failure, and it is determined whether the identification data registered in the RAM at the time of power failure remains at the time of power restoration.

[0004]

However, since the large-capacity capacitor used in the above-mentioned conventional device has a problem in the accuracy of setting the time constant, the reliability of power failure time detection is poor and the power failure time is within the predetermined time. There is a drawback in that it is difficult to perform accurate processing of holding the data in the case of and clearing the data when the power failure time exceeds a predetermined time. That is, for example, when the CR time constant is shorter than the predetermined time due to an error, there is a problem that the daily total data to be held is cleared although the power failure time is actually shorter than the predetermined time.

As a means for solving this, a means for providing a timepiece IC that operates even during a power failure with a backup battery and determining whether or not the power failure time has exceeded a predetermined time t from the count value of this timepiece IC is considered. However, in this case, there is a problem in that the processing of the CPU or the like for making the judgment becomes complicated and the judgment takes a long time.

That is, the conventionally known processing procedure of this type of time detection by the clock IC is as follows: (1) The time data of the clock IC is cleared at the time of power failure (that is, 0).
(00: 00: 00: 00: 00: 00) is set), the time data is read when the power is restored and it is checked whether or not it is t or more. (2) Always operate the clock IC including the power failure. , The time data at the time of power failure is registered in the RAM that operates even during a power failure by the backup power supply, and then the time data of the clock IC at the time of power restoration and the time data at the time of power failure registered in the RAM are compared, and the difference is t or more. In the method of (1) among these, when checking whether the power failure time is, for example, 2 hours or more, as the processing at the time of power failure, the data set as described above is set. To determine if 2 hours have passed since
Is 0, the tenth place of the month is 0, the first place of the month is 0, the tenth place of the day is 0, the first place of the day is 0, or the tenth place of time is 0. It is necessary to check if the number one at the time is 2 or more in sequence, which increases the number of steps in the program and the processing time,
The judgment process when the power is restored becomes complicated. In the case of (2), the reading of each position of the same timepiece IC is required a plurality of times and the process of calculating the difference is also required, which is more complicated.

The present invention has been made on the basis of such a background, and it is possible to accurately detect whether or not a power failure time has exceeded a predetermined time in a short time and with a simple process. It is intended to provide a power failure time detection device.

[0008]

The gist of the present invention for achieving the above object is a power failure time detecting device for detecting whether or not a power failure time exceeds a predetermined time.
A clocking means (15) that operates even during a power failure and clocks in units such as year, month, day, and time with the highest year, and a value that reverses from the one year during the power failure for the predetermined time to the clocking means (15). It is set as an initial value of the start, and when the power is restored, it is determined whether or not the first place of the year in the timekeeping value of the timekeeping means is 0. If 0, it is determined that the power failure time is within the predetermined time, and 0 Otherwise, the power failure time detecting device is characterized by comprising a processing means (13) for judging that the power failure time has exceeded the predetermined time.

[0009]

When there is a power failure, the processing means sets a value, which has been reversed from the one year for a predetermined time, in the timekeeping means as an initial value for starting the timekeeping. That is, when the predetermined time is 2 hours and the time measuring means measures time by each unit of year / month / day / hour / minute / second, the time measuring means is set to Dec. 31, 2000 22:00:00. Then, when the power is restored, it is determined whether or not the first place of the year among the timekeeping values of the timekeeping means is 0,
If so, it is determined that the power failure time is within the predetermined time, and 0
Otherwise, it is determined that the power outage time has exceeded the predetermined time, which is a simple and accurate determination based on the time count value. That is, in the case of the previous example, unless the power failure time reaches exactly 2 hours, the first place of the year is always 0, and if the power failure time is 2 hours or more, the first place of the year is not always 0. The determination is completed simply by reading the value.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a power failure time detecting device according to an embodiment of the present invention. A 1-chip CPU 13 having a battery backup RAM 12 built-in on a substrate 11 which constitutes a main part of the device, and a CPU 13 shown in FIGS. The ROM 14, the timepiece IC 15, the backup power source 6 for backing up the timepiece IC 15 and the RAM 12 in the event of a power failure are incorporated. A DC power supply circuit 17 is connected to the board 11.

The RAM 12 is a storage means for storing daily total data. Further, the CPU 13 is constituted by a microprocessor or the like and is the processing means of the present invention. The CPU 13 receives the power failure signal Ps input from the DC power supply circuit 17 and outputs predetermined identification data to the RAM 1
In addition to writing to 2, the value reversed from one year for a predetermined time t is set in the clock IC 15 as the initial value of the clock start, and when the identification data cannot be read from the RAM 12 when the power is restored, the daily total data is erased. However, when the identification data can be read, the daily total data is erased only when the first digit of the year in the time count value of the clock IC 15 is not zero. Further, the clock IC 15 counts the time in units of year, month, day, hour, minute, and second, and is the time counting means of the present invention.

The DC power supply circuit 17 is a DC power supply circuit which is connected to an AC power supply and applies a drive voltage Vcc to the CPU 13 by closing a switch 18, and the CPU 13 is supplied with the power failure signal PS for notifying power off and power on. Output. The power outage signal PS is the same as in step S31 described later.
Drive voltage Vc until the CPU 13 completes the processing of
In order to prevent c from falling, its output falls slightly before the power failure (power failure signal output), and its output rises when the power is turned on (power failure recovery signal output). Further, the backup power supply 16 is made up of, for example, a battery or the like having a small arrangement space. Further, in the ROM 14, a value that has been reversed from one year for the above-described predetermined time t is registered in advance.

Next, the operation will be described. The CPU 13 operates normally while the AC power of the DC power supply circuit 17 is being supplied. In other words, while receiving various data (stored data) such as the deposit amount of the ball lending machine, etc., the number of balls lent out, the number of medals at the pachinko game hall from the outside (ball lending machine etc.)
Store in M12. 2 is a time chart showing the operating time of the CPU 13, that is, the Vcc ON signal and data clear, the power failure detection timing, and the time setting timing. As shown on the left side of FIG. The power failure signal Ps is in the ON state, and the clock IC 15 does not measure the time.

Then, as shown in the central position of FIG.
When the power is cut off at time Tb (for example, 22:00), the power failure signal Ps from the power supply circuit 17 falls immediately before, and in response to this, the CPU 13 performs the processing when the power is cut off as shown in FIG. That is, if there is a power failure signal (S31), R
The identification data (for example, "1234") is written to the AM2 (S32), and the above-mentioned value written in the ROM 14 in advance, that is, the value reversed from the one year by the predetermined time t (when t is 2 hours, the year is 00). The CPU 13 reads out 22:00:00 'on December 31st, sets it in the clock IC 5 as an initial value of the start of clocking, and commands the start of clocking (S33).

Next, when the power source Vcc rises as shown in the position on the right side of FIG. 2, the power failure signal Ps also rises, and in response to this, the CPU 13 carries out the processing at the time of power-on (when power is restored) shown in FIG. To do. That is, first, it is checked whether or not the identification data is in a good state in the RAM (S41),
If it cannot be read (or if it is not in a complete state), the daily total data is cleared (S42). If the identification data in the RAM 2 remains in good condition (S4
1) Only when the 1st place of the year is not 0 in the time count value of the clock IC 15, it is judged that the power failure time has exceeded the predetermined time t (2 hours), and the daily total data is cleared (S32).

Therefore, when the RAM 12 is sufficiently backed up and the daily total data remains until the power failure is restored, the identification data registered in the same RAM 12 naturally remains and can be read out. The process is based on accurate and simple determination based on the power failure time accurately measured by the IC 15. That is, when the predetermined time t is 2 hours, the first place in the year of the clock IC 15 is always 0 unless the power failure time reaches exactly 2 hours or more,
If the power failure time is 2 hours or more, the first place of the year is not always 0, and the determination is completed only by reading the value of this first place.

A backup power source 16 for the RAM 12 is also provided.
If the daily total data disappears or becomes unreadable by the time of power failure recovery due to consumption of below a certain level after a long time has passed, the same RAM1
The identification data registered in No. 2 is naturally in the same state and cannot be read out. Therefore, the determination by the CPU 13 is a determination that the daily total data should be surely deleted regardless of the time measurement result of the clock IC 15, Useless data retention can be avoided.

As described above, with the above apparatus, it is possible to accurately detect the power failure time and process the daily total data based on the accurate determination, and the complicated processing as in the past becomes unnecessary and the processing time becomes longer. Is significantly reduced. Needless to say, the above-mentioned operation program of the CPU 13 is written in the ROM 14 and sequentially read and executed by the CPU 13.

[0019]

As described above, according to the device of the present invention, whether or not the power failure time exceeds the predetermined time can be accurately performed only by determining the first digit of the year of the timing means. For example, it becomes possible to accurately perform daily power failure data processing in a pachinko game arcade in an extremely short time.

[Brief description of drawings]

FIG. 1 is a block diagram of a power failure time detection device according to an embodiment of the present invention.

FIG. 2 is a time chart of a power failure time detection device according to an embodiment of the present invention.

FIG. 3 is an operation flowchart when the power is off in the embodiment of the present invention.

FIG. 4 is an operation flowchart when power is restored in the embodiment of the present invention.

[Explanation of symbols]

 11 ... Substrate 12 ... RAM 13 ... CPU (Processing Means) 14 ... ROM 15 ... Clock IC (Time Measuring Means) 16 ... Backup Battery

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshio Hata 4-12 Atago Town, Hanamaki City, Iwate Prefecture

Claims (1)

[Claims] Claim: What is claimed is: 1. A power failure time detection device for detecting whether or not a power failure time has exceeded a predetermined time, and which operates even during a power failure, and measures time in each unit such as year, month, day and time, etc. with the highest year. When a power failure occurs, a value that has been reversed for one year from the above-mentioned predetermined time is set as the initial value of the timekeeping means in the timekeeping means, and when the power is restored, it is determined whether or not the first digit of the year among the timekeeping values of the timekeeping means is zero. If it is 0, it is determined that the power failure time is within the predetermined time, and if it is not 0, it is determined that the power failure time has exceeded the predetermined time.