JPH0517722U - Power failure compensator for computer - Google Patents

Abstract

(57) [Abstract] [Purpose] When the power of the computer is cut off and the power is restored, restart the computer with the memory data and time data of the computer in a normal state. At the same time, the purpose is to shorten the repair time even if it is necessary to repair the data. [Configuration] When the power supply of the computer is cut off and the power is restored after a certain time, the microprocessor CPU calculates the checksum of the static ram 1, and the calculation result matches the checksum at the time of power failure. If it is determined that the time difference between the power recovery time and the power failure time and the power supply backup time by the battery 3 are compared with each other, and if it is determined that the time difference is longer than the power supply backup time, a time abnormality flag is set and the clock IC2 It is determined that the time data of is wrong.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a power failure compensator for a computer having a power supply backup circuit for power failure compensation of a static ram and a timepiece integrated circuit (timepiece IC) with a battery or the like.

[0002]

[Prior Art]

 2. Description of the Related Art Conventionally, a power failure compensating device of a micro computer for compensating for a power failure of a static ram, a timepiece integrated circuit, etc. with a battery has a power supply backup circuit as shown in FIG. As shown in FIG. 2, the static ram 1 and the timepiece IC2 are connected to the battery 3, but normally a 5-volt voltage applied to the power supply terminal Vcc of the microprocessor CPU is supplied through the transistor TR1. Then, when the power supply of the microcomputer is cut off, the voltage of 5 V applied to the power supply terminal Vcc of the microprocessor CPU decreases, so that the transistor TR2 is turned off, and as a result, the transistor TR1 is also turned off. Therefore, the static ram 1 and the timepiece IC2 are supplied with the 5 volt voltage from the battery 3 instead of the above 5 volt voltage. However, since the amount of charge of the battery 3 is limited, the memory state of the static ram 1 becomes random after a lapse of a predetermined time, and the time of the timepiece IC2 becomes incorrect.

FIG. 3 shows an interruption process at the time of a power failure of the power failure compensating device of the microcomputer, and FIG. 4 shows a conventional power failure compensating flow. When the power supply of the microcomputer is cut off, an interrupt process is performed as shown in FIG. That is, when a power failure is detected, the checksum of the static ram 1 is calculated, the calculation result is recorded in the static ram 1, the registers are saved, and the halt state is set. Next, as shown in Fig. 4, when the power of the microcomputer is restored, when the restoration is detected, the checksum of the static ram 1 is calculated, and the calculation result is the above-mentioned division at the time of power failure. When it is determined that the checksum calculation result of static ram 1 calculated in the plug-in process matches, the saved registers are restored, while the checksum calculation result of static ram 1 is the same as that at the time of power failure. If not, make initial settings for memory and registers and then return to the main routine.

[0004]

[Problems to be solved by the device]

 The conventional power failure compensating device for a microcomputer described above compensates for power failure by the above-described operation. However, the power failure compensating operation in FIG. I can't tell. Therefore, in the power recovery state, the time of the clock IC2 may be incorrect although the static ram 1 is normal. This is because there is a difference in the data holding voltage between the static ram 1 and the timepiece IC2. Therefore, in the present invention, when the computer power is restored after power failure, it is checked whether or not the memory data of the static ram is normally retained, and the memory data is normally recovered. When it is judged that the data is held, it is possible to discriminate the deviation of the time data of the clock integrated circuit so that both the memory data and the time data at the time of power recovery are in the normal state. The technical issue to be solved is to restart the data.

[0005]

[Means for Solving the Problems]

 The technical means for solving the above-mentioned problems is a means for detecting a power failure of a power failure compensation device of a computer configured to backup the power supply to the static ram and the clock integrated circuit for a predetermined time at the time of power failure. Then, the means for detecting the power failure time, the means for detecting the power recovery, the means for detecting the power recovery time, and the checksum of the above-mentioned static ram at the time of power recovery are performed. The power backup time is the time from the power failure time to the power recovery time, with the method to determine whether the power is on and the checksum at power recovery is determined to match the checksum at power failure. When it is judged that the time is longer, the time abnormality flag is set and the time abnormality determining means for determining the deviation of the clock integrated circuit is provided.

[0006]

[Action]

 According to the computer power failure compensator having the above configuration, when the power supply of the computer is interrupted and the power is restored after a certain period of time, the static ram checksum is calculated when the power is restored, and as a result, when the power is restored. If it is determined that the checksum of the power supply coincides with the checksum at the time of power failure, the time abnormality determination means calculates the time from the power failure time to the power recovery time and determines that the time is longer than the power supply backup time. In this case, a time abnormality flag is set to discriminate the deviation of the clock integrated circuit.

[0007]

【Example】

 An embodiment of the present invention will now be described with reference to the flow chart of FIG. 1 and the power supply backup circuit of FIG. The flow chart of FIG. 1 shows a power failure compensation flow when the power source of the computer is interrupted and the power is restored after a lapse of a certain time. When the microprocessor CPU shown in FIG. 2 judges that the power of the computer is cut off and the power is restored after a certain time, the checksum of the static RAM 1 is calculated, and the value is shown in FIG. It is determined whether or not the checksum of the static RAM 1 calculated in the interrupt processing at the time of power failure matches. If the checksum after power recovery and the checksum after power failure do not match as a result of the judgment, the memory data of the static RAM 1 and the time data of the clock IC2 are cleared, and the initial value is reset. After setting the value, return to the main routine.

On the other hand, when it is determined that the checksum after the power recovery and the checksum after the power failure match, the data of the static ram 1 is normally held, so that the clock IC 2 Enter the check flow. Therefore, the power recovery time is read, the time difference between the power recovery time and the power failure time is calculated, and if it is determined that the time difference is shorter than the power-up time by the battery 3, the main routine is judged to be normal. Return to. On the contrary, when it is determined that the time difference is longer than the power source backup time, it is determined that the time data of the clock IC2 is out of order, a time abnormality flag is set, and then the main routine is returned.

As described above, if the static ram 1 data is normally retained, but the flag is set for the time or more, the static ram 1 data is cleared. Further, it is not necessary to perform further initial setting, and it is sufficient to correct the time data of the clock IC2.

[0010]

[Effect of the device]

 As described above, according to the present invention, when power is restored after the power of the computer is restored, it is checked whether or not the memory data of the static RAM is normally retained, and the memory data is stored. If it is determined that the clock data is normally held, the time integrated data of the clock integrated circuit can be discriminated so that the computer can be reset by correcting only the time data. -There is an effect that the recovery time due to a power outage can be shortened.

[Brief description of drawings]

FIG. 1 is a flowchart of power failure compensation according to an embodiment of the present invention.

FIG. 2 is a power supply backup circuit diagram.

FIG. 3 is an interrupt flow chart at the time of power failure.

FIG. 4 is a conventional power failure compensation flowchart.

[Explanation of symbols]

 1 Static RAM 2 Watch IC 3 Battery CPU Microprocessor TR1 transistor TR2 transistor

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Claims (1)

[Scope of utility model registration request] 1. A power failure compensating device for a computer configured to backup the power supply of a static ram and a clock integrated circuit for a predetermined time in the event of a power failure, wherein a means for detecting a power failure and a power failure time are detected. Means, a means for detecting a power recovery, a means for detecting a power recovery time, and a checksum of the static ram at the time of power recovery to determine whether or not the checksum at the time of power failure matches. And the checksum at power recovery is judged to be the same as the checksum at power failure, and if the time from power failure to power recovery is longer than the power backup time, the time difference A power failure compensating device for a computer, comprising: a time abnormality determining means for setting a flag to determine whether the clock integrated circuit is out of order.