JP2851352B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary of the Invention] A semiconductor integrated circuit that can arbitrarily set either a high-potential output or a low-potential output is described. The first and second n-channel MOS transistors, one of which is depleted and the other of which is enhanced, are connected in series by enabling potential selection without using a potential. And the low potential, the series connection point is an output terminal, the gate is commonly connected to the low potential,
The output terminal outputs either a high potential or a low potential depending on whether one of the first and second n-channel MOS transistors is to be depleted.

[Industrial applications]

The present invention relates to a semiconductor integrated circuit, and more particularly to a potential clip function that can selectively set either a high-potential output or a low-potential output, which is useful for an optional circuit that arbitrarily sets pull-up or pull-down of an internal node or an external terminal. Is set to a semiconductor integrated circuit having.

[Prior Art] Pull-up option circuits Conventional examples include circuits shown in FIGS. 3 (a), (b) and (c). Figure 3 in (a), n-channel MOS transistor Q ₂ is a transistor for pull-up setting an internal node or external terminal T, the transistor by a mask option
Q ₂ is either depletion or enhancement. In the former case, the terminal T is pulled up to the power supply Vcc by the transistor Q ₂ (now equivalent to a resistor), and in the latter case Q ₂
Is off, the terminal T is not pulled up to Vcc, and the circuit becomes an open drain. Q ₁ is an n-channel MOS transistor.

In FIG. 3 (b), the terminal T is a p-channel MOS transistor Q ₃ is pulled up set to the power supply Vcc. Q ₃ is always on, and therefore the pull-up is always done, not to open drain.

FIG. 3 (c) shows a combination of (a) and (b), wherein n-channel MOS transistors Q ₁ and Q ₂ and a p-channel MOS transistor are connected as shown. In this circuit, in either the transistor Q ₂ in either depletion or enhancement, it sets the with / without pull-up resistor Q _3. Depletion transistor Q ₂
Since the resistance value is difficult to precisely control in a semiconductor manufacturing process, which is a simple switch, the resistance value is to have the small p-channel transistor Q ₃ variation due to process. Further, in this circuit, there is no such thing that the voltage of the terminal T is limited to Vcc or lower as shown in FIG. 1B (Japanese Patent Laid-Open No. 63-146460).

[Problems to be solved by the invention]

In the conventional circuit shown in FIG. 3, only the presence / absence of pull-up can be set. However, depending on the application, it is desired that pull-down or both pull-up and pull-down can be arbitrarily set. Many ROM memory cells are pull-down option circuits.

In conventional one-chip microcomputers, enhanced /
Built-in user ROM made of a combination of depletion type transistors and pull-up / pull-down
In many cases, an optional circuit is provided. For such a user ROM, conventionally, arbitrary program data is printed using an I.I. (Ion Injection) mask, and the optional circuit portion is connected to an external terminal using an aluminum wiring mask. Since two types of masks were required for setting options such as pull-up / pull-down, it was necessary to create two masks, and the management of those masks increased costs and complicated process process management. There was such a problem.

Another object of the present invention is to provide an option circuit which improves such a point and does not cause a complicated manufacturing process.

[Means for solving the problem]

FIG. 1 shows an option circuit provided with a potential clipping circuit 10 according to the present invention. The potential clipping circuit 10 connects the n-channel MOS transistors Q ₅ and Q ₆ in series, connects between the high potential Vcc of the power supply and the low potential GND (ground), and sets a series connection point as an output terminal OUT. The gates of the transistors Q ₅ and Q ₆ are commonly connected to a low potential GND.

One of the transistors Q ₅ and Q ₆ is decremented by II or the like, and the other is enhancement. This makes it possible to realize a potential clipping circuit that selects either the high potential Vcc or the low potential GND for the potential of the output terminal OUT without using a wiring mask, burns the program data of the user ROM, and pulls up / down the external terminal. And the like can be manufactured by using only one I / I mask.

[Action]

In potential clipping circuit 10 of the present invention shown in FIG. 1, when the transistor Q ₆ with 1-1 (Ion Injection) mask depression, Q ₅ is an enhancement, a Q ₆ on, Q ₅ off, the output terminal OUT a high potential Vcc of the power source by the transistor Q ₆ is clipped, the depletion transistor Q ₅ with I · I (Ion Injection) mask on the contrary, if the Q ₆ in the enhancement, Q ₅ on a Q ₆ off, the output terminal OUT ground low potential G
ND is clipped. That is, the potential clipping circuit 10 according to the present invention selects whether the potential output to the output terminal OUT is a high potential or a low potential using an I · I (Ion Injection) mask.

〔Example〕

FIGS. 2A, 2B and 2C show examples of use of the potential clipping circuit 10 according to the present invention in FIG.

In FIG. 2A, p is applied between the terminal T and the power supply potential Vcc.
Connect channel MOS transistors Q _7, and controls the gate with the output terminal OUT of the voltage clipping circuit 10 of FIG. 1. When the output terminal OUT of the circuit 10 clips the high potential, the transistor Q ₈ is off, the terminal T open state is selected. When addition of the output terminal OUT of the circuit 10 on the contrary is clipped to a high potential, the transistor Q ₈ is turned on,
The terminal T acts so as to be pulled down to the ground low potential GND.

Table 1 shows the relationship between the combination of enhancement / depletion of the transistors Q ₅ and Q ₆ in the potential clipping circuit 10 and the electricity clipped to the output terminal OUT.

FIG. 2C shows an example in which the potential clipping circuit 10 of FIG. 1 is used for gate control. Since the gate G is a NAND gate, when the output of the circuit 10 is H, the signal S is inverted and passed, and this signal is returned to the original H / L by the inverter I and goes out. When the output of the circuit 10 is L, the output of the NAND gate G is fixed at H, and the output of the inverter I is fixed at L. The former is a state in which the gate G is open, and the latter is a state in which the gate G is closed. This gate opening and closing can be set by the high potential output / low potential output setting of the circuit 10. Gate G may be a NOR gate.

Since the electric clip circuit 10 can be set to either a high potential (H level) output or a low potential (L level) output, as shown in FIG.
Compared to those that can only be set in the logic gate, it is more suitable for controlling the logic gate as shown in FIG. 2 (c).

〔The invention's effect〕

As described above, according to the present invention, as a means for selecting an output potential of the potential clipping circuit in the option circuit,
Since a high potential or a low potential can be selected without using a wiring mask, a one-chip microcomputer or the like having a built-in mask ROM (user ROM) burns the program data of the user ROM onto a wafer (I / I (Ion Injection) mask). Since it becomes possible to share the wiring mask, which is required every time the selection of the option circuit is changed, the cost reduction effect can be obtained.
The need to manage two masks, an I mask and a wiring mask, can be managed by one mask, so that advantages such as simplification of process management can be obtained.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention, FIG. 2 is a circuit diagram showing an embodiment of the present invention, and FIG. 3 is a circuit diagram showing a conventional example. In FIG. 1, Q ₅ and Q ₆ are first and second n-channel MOS transistors, Vcc is a power supply high potential, and GND is the same low potential.

Claims (1)

(57) [Claims] 1. A first and a second n-channel MOS transistor, one of which is depletion and the other of which is enhancement, are connected in series and connected between a high potential and a low potential of a power supply.
A semiconductor integrated circuit having the series connection point as an output terminal and a gate commonly connected to the low potential, wherein the output terminal depends on which of the first and second n-channel MOS transistors is to be depleted. Wherein a high potential or a low potential is output from the semiconductor integrated circuit.