JPH03242022A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent the manufacturing process from being complicated and to attain accurate pull-up/pull-down by adopting a depletion type MOS transistor(TR) for any of two n-channel MOS TRs to form a pull-up or pull-down circuit. CONSTITUTION:N-channel MOS TRs Q5, Q6 are employed and they are connected in series between a high voltage power supply Vcc and a low voltage power supply GND, a series connecting point is used as an output terminal OUT and gates of the TRs Q5, Q6 are connected in common to the low voltage power supply GND. A depletion type TR is employed for one of the TRs Q5, Q6 and enhancement type TR is adopted for the other to manufacture a pull-up/ pull-down circuit. Thus, accurate pull-up/pull-down is implemented and the manufacturing process is not complicated for the pull-up/pull-down circuit.

Description

[Detailed Description of the Invention] [Summary of the Invention] Regarding an optional circuit in which pull-up or pull-down can be arbitrarily set, there is provided a pull-up/pull-down that allows accurate pull-up/pull-down and does not complicate the manufacturing process. The purpose is also to provide an optional circuit. 1. Second n-channel MOS transistors are connected in series and connected between a high potential and a low potential of the power supply, the series connection point is the output terminal, the gates are commonly connected to the low potential of the power supply, and the first or second n-channel MOS transistor is By depressing the n-channel MOS transistor, a pull amplifier or a pull-down circuit is constructed.

[Industrial application field]

The present invention relates to a semiconductor integrated circuit, and particularly to an option circuit in which a pull amplifier or pull-down can be arbitrarily set.

Since it is common practice to pull up or pull down a node or terminal, and it is undecided whether it is a pull-up or pull-down, it is desirable to have a pull-up/pull-down option circuit that can be easily changed to either. There is.

[Conventional technology]

A conventional example of a pull-up option circuit is the circuit shown in FIG. In (a), the n-channel MOS transistor Q2 is set to depletion or enhancement by the mask option, and in the former case, the terminal T is hair-knobbed by the power supply VCCCC by the transistor Q (now equivalent to a resistor), and in the latter case, Q2 is off, and the terminal T is not pulled up to VCC, and this circuit becomes an oven drain. Ql
is an n-channel MOS transistor.

In FIG. 3(b), the terminal T is connected to the power source ■ by the P-channel MOS transistor Q3. , Hebrew amp.

Q is always on, so it always pulls up and never oven drains.

In FIG. 3(C), these are used together, and n-channel MOS transistors Q, , Q, and P-channel MOS transistors are connected as shown. In this circuit, presence/absence of pull-up resistor Q3 is set by depletion/enhancement of transistor Q2. Since it is difficult to accurately control the resistance value of the depletion transistor Qz in a semiconductor manufacturing process, this is a switch, and the resistance value is given by a p-channel transistor Q, which has little variation depending on the process. Also, in this circuit, the voltage at terminal T is not limited to below VCC as in (middle).
(Japanese Unexamined Patent Publication No. 146460/1983).

[Problem to be solved by the invention]

The circuit shown in FIG. 3 only has pull-up presence/absence. Depending on the application, it is desirable that pulldown or both pullup and pulldown can be set arbitrarily. Many ROM memory cells are pull-down option circuits.

In devices such as one-chip microcontrollers that have a built-in user ROM made of a combination of enhancement/depression type transistors and a pull-up/pull-down option circuit, the user ROM has traditionally been an I
・I (Ion Injecti.

n) Masks and option circuits require two types of masks, such as aluminum wiring or contact masks, and since two masks are made, there are problems such as increased costs and complicated process steps.

Another object of the present invention is to improve the above points and provide a pull-up/pull-down option circuit that can perform pull-up/pull-down accurately and does not complicate the manufacturing process.

[Means to solve the problem]

As shown in FIG. 1, in the present invention, n-channel MOS transistors Q9. Q, and connect them in series,
Connected between power supply high potential VCC and power supply low potential GND,
The series connection point is the output terminal OUT, and the transistors Q, ,Q
, are commonly connected to the power supply low potential GND.

One of the transistors Qs and Q- is depleted by I-1, and the other is enhanced.

[Effect]

This circuit can be set to pull-up or pull-down as desired. That is, if transistor Q is set to depletion and Q5 is set to enhancement, Qb is on, Q is off,
The output terminal OUT is connected to the power supply high potential VC by the transistor Q.
It is pulled up to C, and conversely, transistor Q is depleted and Q6 is enhanced.
S is on, Q6 is off, and the output terminal OUT is at the power supply low potential G.
Pulled down to ND.

Depletion/enhancement can be selected using an ion implantation mask. Therefore, when a ROM memory cell is written using masks 1 and 2, a ROM cell and a pull-up/pull-down circuit can be manufactured with one mask.

〔Example〕

2 shows various usage examples of the pull-up/pull-down circuit 10 shown in FIG. 1. In (a), a p-channel MOS transistor Q7 is connected between the terminal T and the power supply potential VCC, and its gate is connected to the It is controlled by the output of the circuit 10. When this circuit 10 is set to pull up and produces an H level output, transistor Q is off and terminal T is not pulled up.

Conversely, when the circuit 10 is set to pull down and produces an L level output, the transistor Q7 is on and the terminal T is pulled up.

In FIG. 3(a), when Q2 is turned on or off, the terminal T has blue or blue, but since the n-channel transistor Q2 is used, there is a large variation in resistance value. This point is second
In Figure 2(a), since a p-channel transistor Q is used, the variation in resistance value is small, and moreover, as shown in Figure 2(b)
Not only with pull-up as in
/L can be used with or without pull-up. In addition, in Fig. 3(C), you can select with/without pull-up, but since transistors Q, Q, are connected in series, if you use the resistor RQ of transistor Q, the resistor RQ of transistor Qt is RQz<<RQ, and even if this is done, the resistance between Vcc and T will be RQ 3 + RQ t. Figure 2(a)
The resistance between Vcc and T is only the resistance of transistor Q7.

FIG. 2(b) is similar, but an n-channel MOS transistor Q is connected between the output terminal T and the low potential of the power supply.

By connecting this gate and controlling this gate with circuit 10 of FIG. 1, it becomes a pull-down option. QII+QIz are P-channel and n-channel MOS transistors at the output stage. Enhancement of transistor Q, ~Q, /
The relationship between the depressigon and the pull amplifier/pull down of the terminal T is shown in the table below. Table 1 shows the case where the pull-amp transistor Q is optional, and Table 2 shows the case where the pull-down transistor Q is optional.

Table 1 Table 2 There may be multiple input/output terminals, in which case pull-up/pull-down transistors Q, /Q.

Although there are a plurality of circuits, the circuit 10 of FIG. 1 may have only i in common.

FIG. 2(C) shows an example in which this circuit 10 is used for gate control. Since G is a Nants gate, when the output of this circuit 10 is H, the signal S is inverted and left behind. is returned to the original H/L by inverter I and leaves. This circuit lO
When the output of is L, the output of Nandt gate G is fixed to H, and the output of inverter 2 is fixed to L. The former is the state where the gate G is open, and the latter is the state where the gate G is closed.
This gate opening/closing can be set by the pull-up/pull-down settings of this circuit IO. Gate G may be a Noah gate.

This circuit 10 can be set to either a pull amplifier or a pull-down, that is, an H-level output or an L-level output, and can be set not only to pull-up or off (high impedance) as shown in FIG. ) is suitable for controlling logic gates such as

In the conventional circuit, a changeover switch is used instead of this circuit lOO, and this switch connects one input end of the gate G to the power supply VCC or the ground.In the fixed type, the switch is wired or not, and in the semiconductor process This will be done using a wiring mask.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to provide an obcisin circuit that can be set to either pull-up or pull-down in the impurity introduction process, and when used in a mask ROM etc., it can be used in common with the impurity introduction mask of a memory cell, simplifying the process. It also has the advantage of being able to be digitized.

[Brief explanation of drawings]

FIG. 1 is a principle diagram of the present invention, FIG. 2 is a circuit diagram showing an embodiment of the present invention, and FIG. 3 is a circuit diagram showing a conventional example. -5°. In FIG. 1, Qs+Q is 1. In the second n-channel MOS transistor, VCC is at the high potential of the power supply, and GND is at the same low potential. Principle diagram of the present invention Figure 1 Applicant: Fujitsu Limited

Claims (1)

[Claims] First, first, and second n-channel MOS transistors (Q_
5, Q_6) are connected in series between the high potential and low potential of the power supply, the series connection point is the output terminal, the gate is commonly connected to the low potential of the power supply, and the first or second n-channel MOS A semiconductor integrated circuit characterized by forming a pull-up or pull-down circuit by depressing a transistor.