JPH04132311A - Input buffer - Google Patents

Abstract

PURPOSE:To utilize the input signal of various levels such as TTL or CMOS in common by providing a 3rd MOS transistor(TR) connected in parallel with any of 1st and 2nd MOS TRs via a connection terminal to the input buffer. CONSTITUTION:A series connection between a P-channel MOS TR 1 and an N-channel MOS TR 2 is provided on the input buffer and further an N-channel MOS TR 4 is connected respectively to an input terminal 6 and a common connecting point via connection terminals 3, 5. An inverter 7 is connected to the common connecting point as its input and its output is connected to an output terminal 8. When the TR 4 is not in use, the connection terminals 3, 5 are opened, and when the TR 4 is in use, the terminals 4, 5 are jumpered. Thus, different input levels such as TTL and CMOS are used in common.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an input buffer, and more particularly to an input buffer whose logic threshold voltage can be switched in accordance with the level of an input signal.

[Conventional technology]

As the input level of the conventional input buffer, vIL=0.
3 TT that satisfies Vno=VtL=2.2 VDn
L(Translstor-Translstor L
ologic) level, VIL=0.5 VDD, VI
There was a C (complementary type) MOS level with L=0.5 Vno, etc., and input buffers were used depending on the input level of each pin.

[Problem to be solved by the invention]

In this way, in the past, each input buffer T was used differently depending on the input level of one IC pin, so it was not possible to respond to changes in the use of peripheral devices that were accompanied by fluctuations in the input level.

An object of the present invention is to solve the problems mentioned above.
An object of the present invention is to provide an input buffer that allows input signals of various levels such as L and CMOS to be used in common.

[Means to solve the problem]

The configuration of the present invention includes complementary first . a second series body of MOS transistors, an inverter whose input is a common connection point of the series body; and an input terminal to which the gates of the second transistors are commonly connected. The present invention is characterized in that a third MOS transistor is provided in parallel with one of the second MOS transistors and connected via a connection terminal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing a large power buffer according to an embodiment of the present invention.

In FIG. 1, the input buffer of this embodiment includes a series body of a P-channel type MOSL transistor 1 and an N-channel type MOS transistor 2, and further includes an N-channel type MOSL transistor 1 and an N-channel type MOS transistor 2.
Transistors 4 are connected via connection terminals 3.5 to respective input terminals 6. Connected to a common connection point. An inverter 7 is provided which uses this common connection point as an input, and its output is sent to an output terminal 8.
Connect to. When the transistor 4 is not required, the connecting terminal 3.5 is left open, and when necessary, a short-circuit wiring is provided.

In this embodiment, it is a CMOS level manual buffer.

Focusing on the fact that the TTL level is determined by the ratio of the dimension (= gate width / gate length) of the Kabaka buffer transistor, the dimension of P channel transistor 1 is fixed and adjusted to the CMOS level and TTL level. N-channel transistors 2 and 4 are configured in parallel,
It consists of a circuit that switches the logic threshold level of CMOS and TTL using a photo-etching pattern during the manufacturing process.

For example, the dimension (=gate width/gate length) of the transistor in Fig. 1 is 10 μm/1
．． The 5 μm sF transistor 2 is 5 μm/1.5 μm, and the transistor 4 is 45 μm/1.5 μm.

In FIG. 1, if the connection terminals 3 and 5 are ovens,
Transistors 1, 2. A CMOS level manual buffer consisting of an inverter 7 is constructed, and when the connecting terminals 3 and 5 are closed with a photo-etching pattern in the manufacturing process (for example, aluminum wiring process), a TTL level manual buffer 7 is formed.

In the above embodiment, a photo-etched pattern in the manufacturing process is used as a switching means, but other switching circuits may be used.

According to this embodiment, in a high-power buffer device connected to an input pin of a semiconductor integrated circuit element, the logic threshold level can be determined by a photo-etching pattern in the manufacturing process in accordance with the input level of TTL, CMOS, etc. .

〔Effect of the invention〕

As explained above, according to the present invention, TTL and CMO
It is possible to use different input caberels such as S in common, it is possible to respond to changes in the specifications of peripheral devices, and there are advantages such as ease of design such as cell-based design.

1...P channel MO8 transistor, 2, 4...
N-channel MOS transistor, 3, 5... connection terminal, 7... inverter, 6... input terminal, 8... output terminal.

Claims (1)

[Claims] a series body of complementary first and second MOS transistors;
In the input buffer, the input buffer includes an inverter whose input is a common connection point of the series body, and an input terminal to which the gates of the first and second transistors are commonly connected. An input buffer characterized in that a third MOS transistor is provided in parallel with the first transistor through a connection terminal.