JP2838792B2 - Liquid crystal display manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a liquid crystal display having a thin film transistor array in which a gate insulating film or a part of the gate insulating film uses a Ta (tantalum) anodic oxide film.

[0002]

2. Description of the Related Art In recent years, as a thin image display, a liquid crystal matrix display, particularly a so-called active matrix type liquid crystal display having a switching element for each pixel, has been researched and developed in various places.

FIG . 4 schematically shows an example of a circuit configuration of the active matrix type liquid crystal display.

When, for example, Xi is selected from among the gate wirings 4, the gates of MIS type thin film transistors (hereinafter referred to as TFTs) 21 connected thereto are turned on all at once,
Through the source of these turned-on TFTs, source wiring 1
From 2, the signal voltage corresponding to the image information is transmitted to the drain of the TFT 21. A pixel electrode 13 is connected to the drain, and the light transmittance of the liquid crystal layer 22 is changed by a voltage difference between the pixel electrode 13 and a counter electrode 23 formed on the other substrate with the liquid crystal layer 22 interposed therebetween. To display images.

When Xi is in the non-selected state, the gate of the TFT 21 connected thereto is turned off, Xi + 1 is subsequently selected, and the same operation as described above is performed. Even after the gate is turned off, the potential difference between the pixel electrode 13 and the counter electrode 23 is stored in the liquid crystal layer 22 until the next time the same gate wiring is selected. The layer will be driven statically, and a high-contrast display can be obtained. By the way, in order to reduce the insulation failure of the gate insulating film, a TFT using a Ta anodic oxide film as a part of the gate insulating film or the gate insulating film has been proposed.

FIGS. 5 and 6 show a TF having the above structure .
1 shows an amorphous silicon TFT as an example of T. In the drawing, 1 is an insulating substrate, 6 is a gate electrode using Ta, 5 is a Ta anodic oxide film formed by anodizing Ta, 7 is a silicon nitride film,
The anodic oxide film 5 and the silicon nitride film 7 form a gate insulating film. 8 is an amorphous silicon film, 9 is a protective insulating film, 10 is a source electrode, 11 is a drain electrode, 12 is a source wiring, and 13 is a pixel electrode.

[0007] Insulation failure of the gate insulating film mostly occurs at the step of the end of the gate electrode 6. When the Ta anodic oxide film 5 is used as shown in FIG. And source electrode 10 and between gate electrode 6 and drain electrode 11
The insulation failure between them is greatly reduced. By the way, usually
Since the gate electrode and the gate wiring are formed by the same process,
Ta is also used for the gate wiring.

[0008]

Since the resistivity of Ta is as high as 15 ohm-cm, the time constant between the resistance of the gate wiring and the capacitance component connected to the gate wiring becomes large, and
The rise and fall characteristics of the signal applied to the gate wiring deteriorate, and a normal signal is not transmitted to the gate electrode. As a result, it has been a cause of deteriorating the display characteristics of the liquid crystal display. In particular, when the size of the liquid crystal display is increased and the length of the gate wiring is increased, the above problem becomes more serious. When the thickness of Ta is increased in order to reduce the resistance of the gate wiring, the end of the gate electrode has a high step, and the step coverage is deteriorated. As a result, insulation failure at the step increases. I do. Therefore, it was not possible to increase the thickness of Ta from the viewpoint of measures against insulation failure, which is the purpose of using the Ta anodic oxide film.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and has as its object to reduce the insulation failure by using a Ta anodic oxide film and reduce the resistance of the gate wiring.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, a gate electrode of a thin film transistor formed on a transparent substrate is formed of Ta, and a gate insulating film is formed of a Ta anodic oxide film. The gate electrode is formed by a Ta wiring covering the gate electrode.
By forming the wiring a in the same step, the resistance of the gate wiring is reduced and the step is simplified.

Further, after forming a metal wiring to be a part of the gate wiring with a metal having a lower resistance than Ta on the transparent substrate, a Ta wiring is formed so as to cover the metal wiring to form a gate wiring and a gate electrode. A Ta electrode is formed at a desired position, and the Ta wiring and the Ta electrode are anodized to a desired thickness from the surface to form a Ta anodic oxide film. And
After forming a silicon layer on the Ta insulating film with the Ta anodic oxide film at least as a part of the gate insulating film, a source electrode and a drain electrode are formed, and a source wiring connecting the source electrodes is formed. Forming and forming a pixel electrode connected to the drain electrode reduces insulation failure and reduces gate wiring resistance. By forming the metal wiring except for the intersection with the source wiring, disconnection of the source wiring is prevented.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

1 to 3, reference numeral 1 denotes an insulating substrate, 2 denotes metal wiring, 3 denotes Ta wiring, 4 denotes metal wiring 2 and Ta wiring 3
And 5, a Ta wiring, a Ta anodic oxide film,
6 is a gate electrode, 7 is a silicon nitride layer, 8 is an amorphous silicon layer, 9 is a protective insulating layer, 10 is a source electrode, 11 is a drain electrode, 12 is a source wiring, and 13 is a pixel electrode. It is.

Hereinafter, the manufacturing process will be described with reference to these drawings.

(A) W (tungsten) is deposited on an insulating substrate 1 made of glass or the like by 150 nm by sputtering and patterned by dry etching to form a metal wiring 2. Here, as shown in FIG.
Then, the metal wiring 2 is crossed with the gate wiring 4 and the source wiring 12.
It is formed in a part other than the part.

(B) Ta is deposited to a thickness of 200 nm by sputtering, and is patterned by dry etching.
Then, a Ta wiring 3 is formed, and the Ta wiring 3 is anodized at a formation voltage of 100 volts to form a Ta anodic oxide film 5 to be a part of the gate insulating layer. At this time, the thickness of the Ta wiring 3 is 100 nanometers, and the thickness of the Ta anodic oxide film 5 is 200 nanometers.

(C) A silicon nitride film 7, an amorphous silicon film 8, and a protective insulating film 9 are deposited, and the protective insulating film 9 is patterned into a predetermined shape. The gate insulating film is made of Ta.
An anodic oxide film 5 and a silicon nitride film 7 are formed.

(D) An n-type silicon film and Ti (titanium) are deposited, and these and the amorphous silicon film 8 are selectively removed to form a source electrode 10 and a drain electrode 10 of the n-type silicon layer and Ti. 11 is formed.

(E) After depositing a transparent conductive film, it is patterned to form a source wiring 12 and a pixel electrode 13.

In the thin film transistor array formed as described above, the gate wiring 4 has a metal wiring 2 using low resistance W (resistivity 5.5 ohm-cm), and the metal wiring 2
, The resistance of the gate wiring 4 is reduced, and the rise and fall characteristics of the signal applied to the gate electrode 6 are improved. Further, since the thickness of Ta is thin, there is no problem of step coverage.

Further, in this embodiment, the metal wire 2 gate - is formed in a portion other than the intersections of the scan lines 12 - DOO wiring 4 and source. With such a structure, the total thickness of the gate wiring 4 at the intersection does not locally increase, so that the source wiring 12 is disconnected at the intersection or the gate wiring 4 is not connected. Insulation failure between the source wirings 12 is reduced. At the intersection, the gate wiring 4 is formed only by the Ta wiring 3, but this part is very small in comparison with the entire length of the gate wiring 4, and the resistance of the gate wiring 4 is small. Hardly increases.

The metal used for the metal wiring is preferably a high melting point metal or an alloy of high melting point metals. In addition to W used in the above embodiment, Mo (molybdenum), W / Mo alloy, W /
A Ta alloy Mo / Ta alloy or the like can be used.

[0023]

A part of the gate wiring or the gate wiring is T
Since it is formed by a metal wiring using a metal having a lower resistivity than a and a Ta wiring covering this metal wiring,
The wiring resistance decreases. As a result, the rising and falling characteristics of the signal applied to the gate electrode are improved, and the display quality can be improved.

Further, the gate electrode is formed only by the Ta electrode, and the gate wiring is formed by a metal wiring using a metal having a lower resistivity than Ta and a Ta wiring covering this metal wiring. The resistance of the gate wiring can be reduced without changing the configuration of the conventional device. In addition, since an entire region of the Ta wiring and the Ta electrode is collectively anodized to form an insulating film covering the gate wiring and a gate insulating film, complicated steps such as exposure and etching are not required.

In addition, of the gate wiring, the intersection with the source wiring is formed only of the Ta wiring, and the gate wiring other than the intersection is formed of a metal wiring using a metal having a lower resistivity than Ta. the formed by the Ta wiring covering the metal wiring
Therefore, the total film thickness does not locally increase at the intersection,
Seo at intersections for - disconnection of the scan wirings or gate - DOO wiring and source - insulation failure is reduced between the scan lines, thereby improving the yield.

[Brief description of the drawings]

FIG. 1 is a plan view of a main part of a liquid crystal display formed by using a method according to a first embodiment of the present invention.

FIG. 2 is a sectional view taken along the line AA of FIG. 1 for illustrating a process of the first embodiment.

FIG. 3 is a sectional view taken along the line BB of FIG. 1 for illustrating a process of the first embodiment.

FIG. 4 is an electric circuit diagram showing a configuration example of an active matrix type liquid crystal display;

FIG. 5 is a plan view of a main part of a conventional liquid crystal display.

FIG. 6 is a cross-sectional view of a thin film transistor using a Ta anodic oxide film.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 2 ... Metal wiring 3 ... Ta wiring 4 ... Gate wiring 5 ... Ta anodic oxide film 6 ... Gate electrode 10 ... Source electrode 12 ... Source wiring

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ identification code FI H01L 29/78 617W (58) Investigated field (Int.Cl. ⁶ , DB name) G02F 1/136 500

Claims (2)

(57) [Claims] 1. A method of manufacturing a liquid crystal display comprising a thin film transistor array formed on a transparent substrate and a pixel electrode connected to each thin film transistor, wherein the gate electrode of the thin film transistor is made of Ta (tantalum).
And at least part of the gate insulating film is made of T
a a gate line connecting the gate electrodes of the thin film transistors is formed of a metal line made of a metal having a lower resistance than Ta and a Ta line covering the metal line; and the gate electrode and the Ta line Formed in the same process,
The metal wiring is formed excluding the intersection with the source wiring.
A method of manufacturing a liquid crystal display. 2. A method of manufacturing a liquid crystal display comprising forming a thin film transistor array on a transparent substrate and connecting a pixel electrode to each thin film transistor, wherein the glass substrate has a gate wiring formed of a metal having a lower resistance than Ta (tantalum). Forming a Ta wiring so as to cover the metal wiring and forming a Ta electrode at a position to be a gate electrode; and forming the Ta wiring and the Ta electrode from a surface. Forming a Ta anodic oxide film by anodic oxidation to a thickness; forming a silicon layer on the gate insulating film using the Ta anodic oxide film of the Ta electrode as at least a part of the gate insulating film; And forming a drain electrode, and forming a source line connecting the source electrodes to each other. Possess and forming a pixel electrode connected to the drain electrode, the metal wiring, and the source wiring
A method for manufacturing a liquid crystal display, wherein the liquid crystal display is formed excluding the intersection of