JP2831741B2 - Storage Element Allocation Support Device in Architecture Synthesis System - Google Patents

Description

The present invention relates to a storage element allocation support device in an architecture synthesis system that supports hardware architecture design.

(Prior Art) In recent years, with the increase in the scale of digital systems, various CAD systems for the purpose of improving design efficiency have been developed. In particular, recently, as a system that supports functional design from a higher level, an architecture synthesis system that generates a hardware configuration for realizing the algorithm by inputting a specification represented by a software algorithm has appeared. .

Usually, in this architecture synthesis system,
The designer pays attention to only the processing algorithm to be realized without being conscious of the specific hardware configuration, and describes the hardware specifications using the same syntax as that of a general-purpose programming language. Then, the system inputs such a specification description, extracts the order and parallelism of the operations included in the specification description, determines the execution order of the operations (scheduling), and performs the operations in accordance with the execution order. Allocating hardware resources necessary for the operation, that is, computing units, registers, and transfer paths (data path allocation). A series of processes for these scheduling and data path assignment are automatically performed according to a certain algorithm without intervention of a designer. For example, regarding the assignment of storage elements, the clique division method described in the following documents 1) and 2)
By the left-edge method, a period during which the variable is valid (lifetime) is calculated, and those having no overlapping lifetime are mechanically merged.

Reference 1) MCMcFarland.ACParker, R.Camposano, “Tutorial
on High-Level Synthesis ", 25th ACM / IEEE Design Aut
omation Conference, 1988, pp330-336. Reference 2) CJTseng, DPSiewiorek, “Automated Synthesis of
Data Paths in Digital Systems ", IEEE Transactions
on Computer-Aided Design, Vol.CAD-5, NO3, JULY 198
6, pp379-395. However, in the assignment of storage elements, the shape of the required transfer path changes by sharing the storage elements. Specifically, a selector is required for the input part of the storage element, and The problem is that the number of fan-outs increases, and it is necessary to perform sharing while taking into account the trade-off with these effects. However, there is a problem that an appropriate data path is not generated as a result of sharing.

In particular, in the above method, each variable is shared as much as possible, so that a variable selected at the beginning of the process is shared a lot, and the transfer path of the storage element corresponding to that variable is performed. Becomes more complex, while variables chosen later in the process are less shared,
There is a problem that the data path configuration becomes unbalanced.

Also, since all sharing processing is left to the system, "it seems better to use the same register for variables x and y", or "I want to implement variables x and y with the same register", or " The variables x and y should not be realized by the same register. " Further, it is impossible to adopt a design method in which a designer performs trial and error while configuring the data path while also considering the influence after sharing the storage element.

As a result, there is a problem that the conventional architecture synthesis system is difficult to use for actual design.

(Problems to be Solved by the Invention) As described above, in the conventional architecture synthesis system, the designer cannot intervene in the data path allocation, and cannot generate the data path intended by the designer. There was a problem.

Therefore, an object of the present invention is to provide a storage element allocation support device in an architecture synthesis system, particularly in an architecture synthesis system capable of generating a data path intended by a designer in a process of allocating storage elements.

[Means for Solving the Problems] According to the present invention for solving the above problems, a hardware specification description is input, the order and parallelism of operations included in the description are extracted, and scheduling and data paths are performed. In a storage element allocation support device in an architecture synthesis system for performing allocation, as a means for allocating storage elements, a scheduling result storage means for storing an execution schedule of an operation, a hardware resource storage means for storing necessary hardware resources, a variable or Storage element designating means for designating a set of storage elements, sharability detecting means for detecting a set of elements in which the storage element can be shared in the variable or the set of storage elements, and detection for displaying a detection result of the means Result display means, assignment designating means for designating the assignment of storage elements, It characterized by having an allocation execution means for performing allocation of storage elements as a target a specified set by Jooyobi the shared possibility detection means detects that said storage element specifying means based on.

(Operation) In the storage element allocation support apparatus in the architecture synthesis system of the present invention, when a designer specifies a variable or a set of storage elements, the storage result is based on the information stored in the scheduling result storage means and the hardware resource storage means. , The sharability detecting means detects a sharable set among the variables or elements of the set of storage elements, and presents the contents. As a result, the designer can obtain information as to which of the specified variables and storage elements can be shared, and can allocate storage elements as intended based on this information. .

(Example) Hereinafter, an example of the present invention is described based on a drawing. FIG. 1 is a block diagram showing a configuration of a storage element allocation support device in an architecture synthesis system according to one embodiment of the present invention.

The storage element allocation support device of this example includes a scheduling result storage unit 1 that stores an execution schedule of an operation of an architecture synthesis system, a hardware resource storage unit 2 that stores necessary hardware resources, and a variable or storage element. A storage element specifying unit 3 for specifying a set, a sharability detecting unit 4 for detecting a set of variables or a set of elements that can share storage elements in a set of storage elements, and a detection result of the means 4 are displayed. A detection result display unit 5, an assignment designation unit 6 for designating the assignment of storage elements, and a set designated by the storage element designation unit 3 based on the designation of the means 6 and the detection result of the sharability detection unit 4 And an assignment execution unit 7 for assigning a storage element to the target.
Further, the storage element allocation support device of the present example includes a lifetime analysis unit 8 disposed between the scheduling result storage unit 1 and the storage element designation unit 3, and a control information display unit 9
And a data path display unit 10 connected to the hardware resource storage unit 2.

The scheduling result storage unit 1 stores operations executed in each step of the architecture synthesis system in a directed graph as shown in FIG. The suffix M of the reference sign means that it is a memory.

In the directed graph shown in FIG. 2, nodes represent operations, and edges represent data flows. Node is third
As shown in the legend in the figure, the attributes include a type of the operation, a step for executing the operation, a unique number (id) of the operation unit for executing the operation, a variable name for storing the result, and a description column for the bit width thereof. The operation type I node represents an input variable, and the operation type O node represents an output variable. A part where the attribute is blank in a part of the storage element name or the computing unit id indicates that the attribute has not been given yet. The steps for the input and output nodes are both set to 0.

The hardware resource storage unit 2 stores information on the assigned computing units and storage elements as shown in FIG. That is, as shown in FIG. 5 as a legend, the operation of the scheduling result storage unit 1 using each arithmetic unit,
Scheduling result storage unit 1 stored in each storage element
Is stored.

As shown in FIG. 6, the control information display unit 9 displays the contents of the scheduling result storage unit 1 on a CRT in a graph format. The suffix D of the reference sign means a screen. As shown as a legend in FIG. 7, in this display, the node indicates an operation type, and in both examples, a step number and an operation unit id are displayed, respectively. A variable name is displayed below the node.

As shown in FIG. 8, the data path display unit 10 displays, on the CRT, a data path for executing the operation of the scheduling result storage unit 1 using the resources of the hardware resource storage unit 2. In this display, variables whose storage elements are not shared are displayed as storage elements having the same names as the variable names, except for input / output variables. Also,
It is considered that an input variable referred to in a plurality of steps such as “e” needs a storage element to hold a value, and is displayed as a storage element having the same name as the variable name.

The storage element specification unit 3 is a part for specifying a variable or a storage element that the designer wants to know about the sharability.

The lifetime analysis unit 8 analyzes the lifetime of a variable or a storage element given by the storage element designating unit 3.

The sharability detection unit 4 detects a sharable combination based on the lifetime analysis result for the variable or storage element specified by the storage element specification unit 3. The result is displayed on the CRT by the detection result display unit 5.

The assignment specifying section 6 is a section in which a designer issues a storage element assignment instruction based on the detection result by the sharability detecting section 4.

The assignment execution unit 7 assigns storage elements based on the designation of the assignment designation unit 6, and changes the contents of the scheduling result storage unit 1 and the hardware resource storage unit 2.

In the above configuration, the scheduling result storage unit 1,
Considering the case where the information shown in FIGS. 2 and 4 is stored in the hardware resource storage unit 2, a specific example will be described below.

Now, it is assumed that the designer designates a variable in the storage element specifying unit 3 with the command of FIG. 9 that the user wants to check the sharability while viewing the display of FIGS.
The command shown in FIG. 9 indicates that a sharable combination is to be obtained for the variables e, f, h, i, j.

Then, the lifetime analysis unit 8 finds a step in which substitution and reference are performed for the specified variables e, f, h, i, j, and creates a lifetime table LTT shown in FIG. That is, first, as shown in FIG. 10, a table LT is created in which a symbol d is inserted in a step in which a value is substituted for each variable and a symbol r is inserted in a step in which a reference is made. Tenth
The horizontal direction in the figure represents a variable or an assigned storage element, and the vertical direction represents a step of executing an operation.

Next, for each variable in FIG. 10, following step 1 in order, as shown in FIG. 11, the symbol L is assigned to the interval [d, r], the symbol D is assigned to the interval [r, d], and the interval [r , r], the symbol L is entered into the remaining portion, and a lifetime table LTT is created.

The sharability detecting section 4 detects a set of sharable variables from the lifetime table LTT of FIG. 11, and the detection result display section 5 displays this as a graph as shown in FIG.

 Fig. 12 shows the algorithm for creating a graph.

That is, in step 1201, the lifetime table LTT
Is a variable that appears in yj (j = 1... N), and a node corresponding to this is created.
The following processing is executed until j <N in 1203.

First, in step 1204, it is determined whether or not one period has the symbol L of the variable yj.
07, j = j + 1 is set, but if there is not one, step 1205 is reached, and k = j + 1 is set, step 1206
Move to.

In step 1206, k <N is determined, and if k <N is not satisfied, the process proceeds to step 1206.

If k <N is determined in step 1206, step 1207
And the variables yj and yk are set to the following <Rule 1> or <Rule 2>
Consider whether or not> is satisfied.

<Rule 1> In the columns of the variables yj and yk, the periods having the symbol L do not overlap.

<Rule 2> In the column of the variables yj and yk, there are steps having the symbol L, and for all these steps, the variable yj ends L at this step, and the variable yk changes from this step to L
Begins.

If rule 1 or 2 is satisfied in step 1207, the process proceeds to step 1208, where nodes yj and yk are connected. If not satisfied, k = k in step 1209
Return to step 1206 as +1.

In FIG. 13, the nodes of the graph represent variables, and the edges represent that the variables at both ends can share storage elements. According to this graph, the designer indicates that there is no variable that can be shared with e for the variable specified by the command.
Information such as "i, f, h can be shared" can be obtained.

Now, the designer can designate a variable to be shared by a command as shown in FIG. 14 while viewing the display as shown in FIG. 6 or FIG. 8 and FIG. The command in FIG. 14 indicates that the variables i, f, and h are stored in a register named R1.

Therefore, assuming that the command shown in FIG. 14 is instructed, the assignment execution unit 7 first checks that there are edges connecting the variables shown in FIG. 13, and there is no such edge. In this case, or when there is no node representing the specified variable, it is assumed that the input in the assignment specifying unit 6 has been erroneous, and an error message is output on the CRT. That is, the operand of the search command is limited to a subset of the variables displayed by the detection result display unit 5 at that time.

In FIG. 13, since i and f, i and h, and f and h are connected to each other, the assignment execution unit 7 assumes that the input is correct, and according to the command in FIG. Then, the contents of the hardware resource storage unit 2 are corrected.

FIGS. 15 and 16 show the storage contents of both storage units 1 and 2 as a result. In FIG. 15, a register name R1 is set to a node corresponding to the variables i, f, h, and in FIG. 16, the register R1 is added as a resource. FIG. 17 shows an example in which the information shown in FIGS. 15 and 16 is displayed by the data path display unit 10. As described above, the data display unit 10 allows the designer to confirm the data path as a result of sharing the storage element.

Here, when the memory element specifying unit 3 checks whether there are any more sharable variables by inputting a command as shown in FIG. 18, R1 is regarded as the variables i, f, h. The time analysis unit 8 uses the life time table LT shown in FIG.
T is generated, and the detection result display unit 5 displays a graph including only isolated points on the CRT as shown in FIG. As a result, it is understood that the storage elements cannot be shared any more.

The display format in the detection result display section 5 is not limited to the graph shown in FIG. 13, but may be a table format such as a matrix shown in FIG. In the matrix of FIG. 21, a column with a circle indicates that variables or storage elements corresponding to the row and column can be shared. Further, the detection result display unit 5 may sequentially list the variables designated by the storage element designation unit 3 or those which can be shared with the storage elements. Further, when the number of designated variables or storage elements is large, the number is divided into n times and m times,
For example, every time the designer inputs with the return key, the next n
You can also display results for individual variables.

In this example, it is possible to inquire the system as to whether or not specific variables and storage elements can be shared, and to know their sharability. Therefore, based on the result of this inquiry, it is possible to perform trial and error allocation of storage elements.

In the above embodiment, when the storage element is shared,
Although the assignment is specified again in the assignment specifying unit 6 separately from the storage element specifying unit 3, in the sharability detecting unit 4, the variable and the storage element specified by one command in the storage element specifying unit 3 are the same. When it is determined that the assignment can be realized by the storage element, the assignment execution unit 7 can be automatically started.

Also, conventional automatic methods can be used in combination. In other words, for the part that the designer considers to be "such a configuration must be made" or the like, the storage element specifying unit 3 makes an inquiry to check the sharability, and then manually specifies it in the allocation specifying unit 7. If the other parts are appropriately assigned by the system using a conventional algorithm, storage elements can be efficiently assigned according to the intention of the designer.

Further, in this case, the designer can specify in the assignment specifying section 6 that the sharing in the subsequent processing is prohibited. For example, when the designer looks at the graph of the determination result of FIG. 13 and the display of FIG. 8, and thinks that “I do not want the variables i and h to be shared,” By designating umrg i, h; to that effect, the id of the node whose sharing is prohibited is set as the attribute of the node of the variable i, h in the scheduling result storage unit 1 in the assignment execution unit 6 (for example, 21st
The node 10 shown in the figure is set to 7 and the node 7 is set to 10), and in the subsequent processing, it can be determined whether or not to perform sharing by referring to this attribute information.

In addition, the system can automatically assign only variables and storage elements specified by a single command in the storage element specifying unit 3 by the designer using a conventional algorithm. As a result, it becomes possible to control a range to be shared by the system.

The present invention is not limited to the above embodiment, and can be appropriately modified and implemented without departing from the gist thereof.

[Effects of the Invention] As described above in detail, according to the present invention, based on an input of a storage element desired to be shared, it is determined whether or not the sharing is actually possible, and then the combination is appropriately determined. Since it is a storage element allocation support device in an architecture synthesis system that is presented and accepts an arbitrary sharing designation, it is possible to easily design a storage element allocation as intended by a designer.

[Brief description of the drawings]

FIG. 1 is a block diagram of a storage element allocation support device in an architecture synthesis system according to one embodiment of the present invention;
FIG. 2 is an explanatory diagram of storage contents of a scheduling storage unit,
FIG. 3 is an explanatory diagram of the legend, FIG. 4 is an explanatory diagram showing contents stored in a hardware resource storage unit, FIG. 5 is an explanatory diagram of the legend, and FIG. 6 is a display example of a control information display unit. FIG. 7 is an explanatory diagram of the legend, FIG. 8 is an explanatory diagram of a display example of a data path display unit, FIG. 9 is an explanatory diagram of a command in a storage element designating unit, and FIG. Diagram for the table for FIG. 11, FIG. 11 is a diagram for explaining the lifetime table, FIG. 12 is a flowchart showing a procedure for creating a graph indicating sharability, FIG. 13 is a diagram for explaining a display example of a detection result display section FIG. 14 is an explanatory diagram of a command for sharing a storage element of an assignment specifying unit, FIG. 15 is an explanatory diagram of storage contents of a scheduling result storage unit after execution of a sharing command, and FIG. Explanatory drawing of the storage contents of the ware resource storage unit FIG. 17 is an explanatory diagram of a display example of a data path display section after executing the command, FIG. 18 is an explanatory diagram of a command for checking sharability, FIG. 19 is an explanatory diagram of a lifetime analysis result, FIG. FIG. 21 is an explanatory view showing a display example when there is no possibility of sharing the detection result display section, and FIG. 21 is an explanatory view showing another display example of the detection result display section. DESCRIPTION OF SYMBOLS 1 ... Scheduling result storage part 2 ... Hardware resource storage part 3 ... Storage element designation part 4 ... Shareability detection part 5 ... Detection result display part 6 ... Assignment designation part 7 ... Assignment execution part 8 ...... Lifetime analysis unit 9 Control information display unit 10 Data path display unit

Claims (2)

(57) [Claims] 1. A storage element allocation support device in an architecture synthesis system that inputs a hardware specification description, extracts the order and parallelism of operations included in the description, and performs scheduling and data path allocation. Means, a scheduling result storage means for storing an execution schedule of the operation, a hardware resource storage means for storing necessary hardware resources, a storage element designating means for designating a set of variables or storage elements, Sharability detecting means for detecting a set of elements which can share storage elements in a set, detection result display means for displaying detection results of the means, allocation specifying means for specifying allocation of storage elements, The storage based on the designation and the detection result of the sharability detection means. Storage element assigned supporting device in the architecture synthesis system, characterized in that with assignment execution means for performing allocation of storage elements as a target a specified set by element specifying means. 2. The storage element allocation support device in an architecture synthesis system according to claim 1, wherein, when said architecture synthesis system includes means for automatically allocating storage elements, said allocation designation means includes a variable or a storage element. A storage element allocation support device in an architecture synthesis system characterized in that designation for prohibiting sharing of a storage element can be performed.