JP3394353B2 - Machine instruction scheduling device - Google Patents

Description

Detailed Description of the Invention

[0001]

The present invention relates to relates to a technique for translating a source program into the object program, to machine language instruction scheduling system to improve the execution efficiency of the object program by particular reorder machine instructions.

[0002]

2. Description of the Related Art In recent years, in electronic computers, high-speed hardware has been developed in order to perform information processing at a higher speed, and the high-speed performance is extracted as much as possible to execute programs more efficiently. The software technology for it has also been developed.

As one of such software technologies, there is a machine language instruction sequence scheduling technology in an optimizing section of a compiler, and the following conventional technology of this type is known. .

From the machine language instruction sequence before optimization,
Based on the data dependency between the machine language instructions, all machine language instructions in the schedulable state in which the machine language instructions that must be executed first are already scheduled are extracted.

When a machine language instruction that is in a schedulable state is extracted, the instruction issuance timing is set to the earliest when the instruction issuance timing is set to a timing at which the already-scheduled machine language instruction does not conflict with resources. Select one of the available machine language instructions and schedule the selected machine language instruction next to the already scheduled machine language instruction. The above processing is repeated until all machine language instructions are scheduled. in this way,
By changing the order of the machine language instructions, it is possible to generate a machine language instruction sequence with less hardware interlock (internal stop) and high execution efficiency. Here, the earliest instruction issuance timing that does not cause a resource conflict with a machine language instruction that has already been scheduled is obtained by using a resource request table as shown in FIG. The resource request table is provided for each machine language instruction and describes the resources required by the corresponding machine language instruction in machine clock units. The resource request table shown in FIG. The resource A is used at the machine clock 0,1 machine clocks after the execution start, the resource B is made at the machine clock one machine clock after the execution start, and the resource C is made at the machine clock 0,1,2 machine clocks after the execution start. , The resource D is required at the machine clock a few machine clocks after the start of execution.

[0006]

By the way, in order to create the resource request table as described above, it is necessary to determine what kind of resource is required when each machine language instruction is executed in detail of the hardware. It is necessary to investigate up to. However, it is difficult to accurately check the resource information down to the details of the hardware, and it is difficult to create a complete resource request table for all machine language instructions.

Therefore, even if it is determined that the scheduled machine language instruction X does not conflict with the resource based on the resource request table and the machine language instruction Y is scheduled next to the machine language instruction X, the resource request table Is not perfect, a resource conflict may occur between the machine language instruction X and the machine language instruction Y at the time of execution, and an interlock may occur. In such a case, if there is a machine language instruction Z that is in a schedulable state in which there is no resource conflict with the machine language instructions X and Y, the machine language instruction Z is scheduled next to the machine language instruction X. By scheduling the machine language instruction Y next to the machine language instruction Z, the execution efficiency of the target program can be improved. However, in the above-described conventional technique, the machine language instruction is only scheduled based on the content of the resource request table so that the resource contention does not occur. If you decide that you can schedule, it is impossible to do the above.

Therefore, an object of the present invention is to generate a machine language instruction sequence with less interlocking as compared with the case of only scheduling machine language instructions so that resource contention does not occur. word instruction scheduling
To provide a device .

As a related technique, Japanese Patent Publication No. Sho 62-52.
No. 899, a process of determining the size m and the number n under the condition that the product of the size m of the vector register and the number n of the vector register is constant,
Create an execution time chart based on the simulation of the operation timing and each operation time on multiple computing units of a temporary object program that performs the processing specified by the program, and from the execution time chart in the real time direction. To find an empty computing unit and create an object program by scheduling instructions so that the empty time of the computing unit is allocated to the execution of other instructions. Size m and number n
An object program optimizing method for obtaining an object program with the shortest total execution time by performing and while changing m and n within a certain range is shown.

The object program optimizing method described above is the maximum to find out what kind of division is optimal in a computer system in which division of the size and number of vector registers can be freely set. In order to obtain the optimum object program in any state, the objective is to "simulate the operation timing on multiple arithmetic units and the operating time on each arithmetic unit." Based on this, an execution time chart is created. From this execution time chart, a vacant arithmetic unit in the time axis direction is found, and another instruction is moved to this. " However, the above-mentioned object program optimizing method has no description about which instruction is used by each arithmetic unit and how to track the empty state of the arithmetic unit in the time axis direction. Further, in the above object program optimization method, exclusive control of resource competition is performed by finding an idle computing unit based on the execution time chart and allocating the idle time of the computing unit to the execution of another instruction. Therefore, if the execution time chart is not accurate, the same problem as the above-mentioned conventional technique occurs.

Further, Japanese Laid-Open Patent Publication No. 3-242731 discloses a source program interpreting means for interpreting a source program and expanding it into an intermediate code, and a serial assembly instruction in which instructions to be executed by respective arithmetic units are arranged in series. Serial assembly instruction sequence generating means for generating a sequence from intermediate code,
Resource allocation means for allocating hardware resources to each data appearing in the program, and after resource allocation is completed,
A compile processing method including a parallel assembly generation means for generating a parallel assembly instruction string is shown. Here, in the parallel assembly generation means, for the serial assembly instruction string, first, the data dependency analysis unit analyzes the mutual dependency of the data appearing in the instruction and expresses it as a directed graph, and then the instruction parallelization is performed. In the processing unit, a parallel assembly instruction string, which is the target program, is generated by determining the arithmetic unit for executing each instruction and the clock for executing the instruction. However, in the above-mentioned compile processing method, the control range of the instruction issue timing is
A relationship between instructions that have a data dependency relationship, which does not have a data dependency relationship, but which limits the instruction issue timing (for example, instruction A
There is a problem that the instruction issue timing cannot be controlled on the basis of the instruction B appearing next to the instruction B, which starts execution 3 machine clocks after the execution start of the instruction A).

[0012]

A machine language instruction scale according to the present invention
In the machine language instruction scheduling device of the compiling device, the jailing device schedules a sequence of machine language instruction sequences generated based on a source program so as to improve the execution efficiency of the program. From the schedule candidate instruction extracting means for extracting all the machine language instructions in the schedulable state, and a resource request table in which the resources necessary for executing the machine language instruction are described in machine clock units for each machine language instruction. If the machine language instructions between instruction issue timing timing map table constraint information is described that indicates constraints, said schedule candidate instruction extraction unit extracts each machine instructions
The current schedule for one of the machine instructions
Schedule on the machine clock trying to
Judge whether there is a conflict between the existing machine instructions and resources
However, if it is determined that there will be no competition for resources,
Language instructions and scheduled machine language instructions
Between machine language instructions indicated by constraint information in the memory map table
Whether or not the constraint of the instruction issuance timing is satisfied
And, when it is judged that the constraint is satisfied, the machine language
Instructions are scheduled after scheduled machine instructions
And a control means for performing a schedule process for
The control means determines whether or not competition for the resources will occur.
If it is determined that competition for resources will occur,
The schedule candidate instruction extracting means other than the machine language instruction is
Judge whether there is an extracted machine language instruction, and if there is,
Perform the schedule process for any of the
If not, advance the machine clock by one and restart.
The machine extracted by the schedule candidate instruction extracting means
The schedule process for any of the word commands
To determine whether or not the above constraints are satisfied.
When it is determined that the constraints are not satisfied,
The schedule candidate instruction extraction means other than the machine language instruction is extracted.
Judge whether there is a machine language instruction issued, and if so,
For any of the above, perform the schedule process,
If not, advance the machine clock by one and then again.
Machine language instruction extracted by the schedule candidate instruction extraction means
Perform the schedule process for any of the
It is characterized by

[0013]

The candidate candidate instruction extracting means extracts all machine language instructions in the schedulable state from the machine language instruction sequence, and the resource request exclusive control means makes the resource request table.
Schedule candidate instruction extraction means based on the contents of the bull
The current schedule from the machine language instructions extracted by
Scheduled machine at the machine clock you are looking at
One machine language instruction at a time without conflict between machine language instructions and resources
Sequential selection of scheduled machine instructions and resources
If all machine language instructions that do not cause conflicts are selected,
Advance the machine clock to try Joule by one, and issue Thailand
The resource control means has been selected by the resource request exclusive control means.
Machine language instructions and scheduled machine language instructions
Between machine language instructions indicated by constraint information in the memory map table
Judging that the instruction issue timing constraint of
The machine language instruction selected by the resource request exclusive control means.
To schedule a decree to the next scheduled machine language instruction.

[0014]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. An instruction scheduling device ( instruction scheduler ) 1 of this embodiment comprises a data dependence graph creating means 2 for creating a data dependence graph 3 and a schedule candidate instruction 5. It is composed of a schedule candidate command extracting means 4 for extracting the control information and a control means 6.

The data dependence graph creating means 2 has a function of creating a data dependence graph 3 based on a machine language instruction sequence 9 generated by performing syntax analysis, semantic analysis, etc. on a source program. Here, the machine language instruction sequence 9
The sequence of each machine language instruction of is the same as the sequence of the corresponding instructions in the source program.

The schedule candidate instruction extracting means 4 is a data dependence graph 3 created by the data dependence graph creating means 2.
Based on the above, it has a function of extracting, as a schedule candidate instruction 5, information indicating a machine language instruction that can be scheduled in the machine clock currently being scheduled.

The control means 6 is composed of a resource request exclusive control means 7 and an issuance timing control means 8 and uses them to select a machine language instruction whose instruction issuance timing has already been scheduled from among the schedule candidate instructions 5. When the timing at which resource conflict does not occur and the constraint of the instruction issue timing with the already scheduled machine language instruction is satisfied, the machine language instruction that can make the instruction issue timing the earliest is 1 Choose one,
It has a function of scheduling the selected machine language instruction next to the already scheduled machine language instruction.

The resource request exclusion control means 7 includes a resource request exclusion controller 71 and resource request tables 72-1 to 72-m.
And a resource request blackboard 73.

The resource request tables 72-1 to 72-m are
The resource request tables 72-1 to 72-m are provided for each machine language instruction. As shown in FIG. 12, the resources required for executing the corresponding machine language instruction are stored in the machine clock. It is described in units.

On the resource request blackboard 73, the contents of the resource request table corresponding to the scheduled machine language instructions are registered in the order of schedule.

The resource request exclusive control unit 71, based on the contents of the resource request tables 72-1 to 72-m and the contents of the resource request blackboard 73, selects the machine currently trying to schedule from among the schedule candidate instructions 5. Function to sequentially select machine language instructions that do not cause resource conflict with already scheduled machine language instructions in clock, machine language instruction that does not cause resource conflict with already scheduled machine language instructions When all are selected, it has a function of advancing the machine clock by one to try the schedule, a function of registering the contents of the resource request table corresponding to the scheduled machine language instruction on the resource request blackboard 73, and the like.

The issue timing control means 8 includes a timing control section 81 and timing map tables 82-1 to 82-1.
2-n, a timing map blackboard 83, and a schedule table 84.

Timing map tables 82-1 to 82-2
-N is provided for a machine language instruction which has an instruction issue timing constraint with other machine language instructions and causes an interlock when the machine language instruction is issued without satisfying the constraint. FIG. 2 is a diagram showing a configuration example of the timing map table 82-i for a certain machine language instruction i, which is composed of an elapsed timing unit 21 and an issuance inhibition timing unit 22.

In the progress timing section 21, the machine language instruction i
Describes the elapsed timing from when the is issued until the execution ends. In the example of FIG. 2, the timing 0, 1, 2, 3 machine clocks after the machine language instruction i is issued is represented by i0, i1, i2, i3. If the machine language instruction i does not restrict the instruction issue timing of another machine language instruction, the elapsed timing unit 21 is not necessary.

Further, the issue suppression timing section 22 describes the timing of machine language instructions which are not allowed to overlap in issuing the machine language instruction i. The example of this FIG.
The instruction issue timing of the machine language instruction i should not overlap with the timing j0, j1, j2 0,1, 2 machine clocks after the machine language instruction j is issued, and 0 machine after the instruction k is issued. Timing after clock k
It indicates that it should not overlap with zero. If the issue timing of the machine language instruction i is not restricted by another machine language instruction, the issue suppression timing unit 2
2 is unnecessary.

The timing map tables 82-1 to 82-n having the above-described structure and contents are obtained by, for example, extracting the constraint of instruction issue timing between machine language instructions described in a hardware manual or the like. Created. It should be noted that the above-mentioned restrictions on the instruction issue timing between machine language instructions are ultimately due to some kind of resource competition, and it may be possible to express them in the resource request table. It is possible that resource information cannot be accurately examined from the standpoint of doing so to the details of the hardware. In such a case, it is possible to compensate for the incompleteness of the resource request table by using the timing map table and considering the constraint of the instruction issue timing between machine language instructions.

On the timing map blackboard 83, the contents of the timing map table corresponding to the scheduled machine language instructions are registered in the order of schedule.

In the schedule table 84, a scheduled machine language instruction and a machine clock that schedules the machine language instruction are registered.

The timing controller 81 controls the resource request exclusion controller 7 based on the contents of the timing map tables 82-1 to 82-n and the contents of the timing map blackboard 83.
When it is determined that the machine language instruction selected in 1 and the already scheduled machine language instruction satisfy the constraint of the instruction issue timing between the machine language instructions, the resource request exclusive control unit 71 selects them. It has a function of registering a machine language instruction and a machine clock that schedules the machine language instruction in the schedule table 84, a function of registering the contents of the timing map table corresponding to the scheduled machine language instruction in the timing map blackboard 83, and the like.

FIG. 3 is a flow chart showing a processing example of the control means 6, and in the present embodiment, the case where the machine language instruction sequence shown in FIG. 4 is input to the instruction scheduler 1 as the machine language instruction sequence 9 will be described below as an example. The operation will be described. The machine language instruction sequence 9 shown in FIG. 4 is obtained by converting the instructions in the source program shown in FIG. 5 into machine language instructions in the same order.

First, each machine language instruction shown in FIG. 4 will be described, and the resource request table corresponding to each machine language instruction shown in FIG. 4 and the second, third, and fifth shown in FIG. The timing map table corresponding to the sixth and sixth machine language instructions will be described.

The first machine language instruction "LD% in FIG. 4"
0, A ″ is an instruction to load a value from the storage area assigned to the variable A into the register with register number 0, and the resource request table corresponding to this machine language instruction is, for example,
It has the contents shown in FIG. In the resource request table shown in FIG. 6 (A), the machine language instruction described above has the resource i at the machine clock 0 machine clock after the start of execution.
For nst-slot, the resource m-bus and the resource reg0 are set at the machine clock 0,1 machine clocks after the start of execution.
Indicates that you need and. Where resource i
The nst-slot is an m-bu resource for exclusive control so that a plurality of machine language instructions are not issued in one machine clock.
s is the memory bus between the storage area and the register, reg0
Indicates the register with register number 0.

The second machine language instruction "MUL" in FIG.
% 1,% 0,2 "is an instruction to store the result of multiplying the contents of the register of register number 0 by 2 in the register of register number 1. The resource request table corresponding to this machine language instruction is, for example, It has the contents shown in FIG.
In the resource request table shown in FIG. 6 (B), the machine instructions described above are resources inst-slot, mulr, reg at a machine clock 0 machine clock after the start of execution.
0 indicates that the resource reg1 is required at the machine clock 0,1 machine clocks after the start of execution, and the resource addr is required at the machine clock one machine clock after the start of execution. Here, the resource mulr is a multiplier,
The resource addr indicates an adder, and the resource reg1 indicates the register of register number 1. Further, the timing map table corresponding to the machine language instruction is, for example, as shown in FIG.
It has the contents shown in (A). Where mul0, m
ul1 and mul2 indicate the elapsed timings of the machine language instructions described above, and the timings 0, 1 and 2 machine clocks after the start of execution of the machine language instructions, respectively.

The third machine language instruction "ST% in FIG. 4"
1, X ”is the contents of the register of register number 1 being variable X
The resource request table corresponding to this machine language instruction has the content shown in FIG. 6C, for example. In the resource request table shown in FIG. 6 (C), the machine language instruction described above has resources in at the machine clock 0 machine clock after the start of execution.
It is shown that the resource m-bus is required for the machine clock 0,1 machine clocks after the start of execution of st-slot, reg1. Further, the timing map table corresponding to the above machine language instruction has, for example, the content shown in FIG. 7B, and this timing map table issues the machine language instruction according to ADD.
Two machine clocks after the start of instruction execution and MUL
It indicates that it must be executed 3 machine clocks after the start of execution of the instruction.

The fourth machine language instruction "LD%" in FIG.
2, B ″ is an instruction to load a value from the storage area assigned to the variable B to the register of register number 2, and the resource request table corresponding to this machine language instruction is, for example,
It has the contents shown in FIG. The meaning of this resource request table is almost the same as the meaning of the resource request table of FIG.

The fifth machine language instruction "ADD" in FIG.
"% 3,% 0,% 2" is an instruction for storing the sum of the contents of the register of register number 0 and the contents of the register of register number 2 in the register of register number 3, and corresponds to this machine language instruction. The resource request table is, for example, as shown in FIG.
It has the contents shown in (E). In the resource request table shown in FIG. 6 (E), the resource inst- is started at the machine clock 0 machine clock after the execution start of the machine language instruction.
This indicates that slot, addr, reg3, reg0, and reg2 are required. The timing map table corresponding to the above machine language instruction has, for example, the content shown in FIG. Where ad
d0 and add1 indicate elapsed timings of the machine language instructions, respectively, timings 0 and 1 machine clocks after the start of execution of the machine language instructions.

The sixth machine language instruction "ST%" in FIG.
3, Y ”is the variable Y for the contents of the register of register number 3.
A machine language instruction to be stored in the storage area allocated to the resource request table corresponding to this machine language instruction has, for example, the contents shown in FIG. 6 (F). This Figure 6
In the resource request table shown in (F), the machine language instruction requires the resources inst-slot, reg3 at the machine clock 0 machine clock after the start of execution.
This indicates that the resource m-bus is required at the machine clock that is 0,1 machine clocks after the start of execution.
The timing map table corresponding to the machine language instruction has, for example, the content shown in FIG.
This timing map table indicates that the machine language instruction must be issued two machine clocks after the start of execution of the ADD instruction and three machine clocks after the start of execution of the MUL instruction.

Next, the operation when the machine language instruction sequence 9 shown in FIG. 4 is input to the instruction scheduler 1 will be described.

When the machine language instruction sequence 9 shown in FIG. 4 is input, the data dependency graph creating means 2 in the instruction scheduler 1 is a diagram showing the data dependency relationship between the machine language instructions in the machine language instruction sequence 9. A data dependence graph 3 shown in 8 is created.

In FIG. 8, nodes N1 to N6 correspond to the first to sixth machine language instructions shown in FIG. 4, respectively, and the line segment connecting the nodes is the upper node. The result of the machine language instruction corresponding to is the data dependency that the machine language instruction corresponding to the lower node refers to.

FIG. 9 is a diagram showing an example of the contents of the nodes N1 to N6. The node number 901, the instruction pointer 902,
Resource request table pointer 903, timing map table pointer 904, definition node pointer 905
, Reference node pointer 906, and number of remaining nodes 907
And are set.

The node number 901 is a number uniquely indicating the node. The instruction pointer 902 is a pointer to a character string of a machine language instruction corresponding to the node. The resource request table pointer 903 is a pointer to the resource request table corresponding to the machine language instruction pointed to by the instruction pointer 902. The timing map table pointer 904 is a pointer to the timing map table corresponding to the machine language instruction pointed to by the instruction pointer 902. The definition node pointer 905 is
The machine language instruction corresponding to that node is a pointer to the node corresponding to the machine language instruction that refers to the result. The reference node pointer 906 is a pointer to the node corresponding to the machine language instruction that refers to the result of the machine language instruction corresponding to that node. The number of remaining nodes 907 indicates the number of unscheduled machine language instructions (the number of nodes) among the machine language instructions whose results are referenced by the machine language instruction corresponding to the node.

FIG. 10 is a diagram showing an example of the contents of the node N5 corresponding to the fifth machine language instruction shown in FIG.
The node number 901 of this node N5 is "5".
Is the fifth instruction in the machine language instruction sequence 9 as the instruction pointer 902.
The character string of the th machine language instruction "ADD% 3,% 0,%
The pointer to 2 ″ is the resource request table pointer 903.
6E, a pointer to the resource request table shown in FIG. 6E, a pointer to the timing map table shown in FIG. 7C as a timing map table pointer 904, and a node N1 as a definition node pointer 905.
A pointer to the node N4 is set as the reference node pointer 906, a pointer to the node N6 is set, and “2” is set as the remaining node number 907. Although not expressed in this embodiment, the result is output to the same register, but if the instruction schedule has a dependency on the order, the machine language that destroys the register is not expressed. Before the node corresponding to the instruction destroys the register, if the node corresponding to the machine language instruction referencing the register before the destruction refers to the above-described data dependence graph 3, the register is generated. The order to destroy is not scheduled first.

When the data dependence graph creating means 2 creates the data dependence graph 3 shown in FIG. 8, the schedule candidate instruction extracting means 4 can schedule a command which must be executed first. The node corresponding to the machine language instruction in the state is extracted from the data dependence graph 3, and the pointer to the extracted node is output as the schedule candidate instruction 5.

At this point in time, the two nodes N1 and N4 corresponding to the machine language instruction in the schedulable state are the schedule candidate instruction extracting means 4
The pointers to the nodes N1 and N4 are output as the schedule candidate instruction 5.

When the pointers to the nodes N1 and N4 are output as the schedule candidate instruction 5 from the schedule candidate instruction extracting means 4, the control means 6 starts the processing shown in the flowchart of FIG.

First, in step S1, the resource request exclusive control unit 71 and the timing control unit 81 clear the resource request blackboard 73 and the timing map blackboard 83 respectively to make them both blank and at the present time. Initialize a variable clock that holds the clock number of the machine clock for which the schedule is attempted to "0".

After that, the resource request exclusive control unit 71 outputs the schedule candidate instruction 5 from the schedule candidate instruction extracting means 4 and the remaining node number 907 is "0".
One of the pointers to the nodes N1 and N4 of
Set to de (step S3). Now, for example, it is assumed that the resource request exclusive control unit 71 sets the pointer to the node N1 among the pointers to the nodes N1 and N4 in the variable node.

When the pointer to the node N1 is set in the variable node, the resource request exclusive control unit 71 determines whether the content of the resource request table pointed to by the resource request table pointer 903 of the node N1 can be registered in the resource request blackboard 73. It is determined (step S6). At this point, the resource request blackboard 73 is in a blank state, so the resource request exclusive control unit 71 determines that it can be registered.

If the resource request exclusive control unit 71 determines that it can be registered, whether the timing control unit 81 can register the content of the timing map table pointed to by the timing map table pointer 904 of the node N1 in the timing map blackboard 83. It is determined (step S7). The timing map table pointer 904
Is NULL, that is, when the timing map table corresponding to the node N1 does not exist, the timing control unit 81 determines that it can be registered. In this case, the timing map table pointer 904 of the node N1 is NULL. Therefore, the determination result of step S7 is YES.

If the decision result in the step S7 is YES, the resource request exclusive control unit 71 sets the content of the resource request table pointed to by the resource request table pointer 903 of the node N1 to the variable cloc of the resource request blackboard 73.
The timing control unit 8 registers at the position indicated by k.
1 is the timing map table pointer 9 of the node N1
The contents of the timing map table pointed to by 04 are registered in the position indicated by the variable clock on the timing map blackboard 83, and the machine language instruction pointed by the instruction pointer 902 of the node N1 and the machine clock that schedules the machine language instruction Is registered in the schedule table 84 (step S
8). When the content of the timing map table pointer 904 is NULL, the timing control unit 81 determines that the timing map table can be registered in the timing map blackboard 83, but the actual registration operation is not performed. In this example, the node N1 corresponds to the first machine language instruction “LD% 0, A” in FIG.
Since the contents of the resource request table corresponding to D% 0, A "are as shown in FIG. 6A, as shown in FIG.
The contents of the resource request table shown in FIG. 6A are registered in clock = 0 of the resource request blackboard 73, but the node N1
Contents of the timing map table pointer 904 of
Since it is UL, the timing map table is not registered on the timing map blackboard 83.

Further, in step S8, the timing control section 81 decrements the remaining node number 907 of all the nodes pointed to by the reference node pointer 906 of the node N1 in the data dependence graph 3 by 1, and thereafter schedules The process of instructing the candidate instruction extracting means 4 to extract the schedule candidate instruction 5 is also performed.

Upon receipt of this instruction, the schedule candidate instruction extracting means 4 is in a machine language in which the machine language instruction, which must be executed first, has already been scheduled and is ready to be scheduled, based on the data dependence graph 3. The node corresponding to the instruction is extracted, and the pointer to the node is output as the schedule candidate instruction 5. in this case,
The pointers to the nodes N2 and N4 are output as the schedule candidate instruction 5.

When the pointers to the nodes N2 and N4 are output as the schedule candidate instruction 5, the resource request exclusive control unit 71 sets one of them in the variable node (step S3). Now, for example, it is assumed that the resource request exclusive control unit 71 sets a pointer to the node N4 in the variable node.

When the pointer to the node N4 is set in the variable node, the resource request exclusive control unit 71 determines whether the contents of the resource request table pointed to by the resource request table pointer 903 of the node N4 can be registered in the resource request blackboard 73. It is determined (step S6). In this case, the resource request table of the node N4 is as shown in FIG. 6D, and the content of the resource request table shown in FIG. 6A is registered at the position of clock = 0 on the resource request blackboard 73. And clock = 0, the resource inst-slo
Since t and m-bus overlap (conflict), it is determined that registration cannot be performed.

If it is determined in step S6 that registration is not possible, the resource request exclusive control unit 71 determines that one of the unprocessed nodes in the schedule candidate instruction 5 (node N in this case).
Similarly to 2), it is determined whether the resource request table of the node N2 can be registered in the resource request blackboard 73 (steps S3 and S6). In this case, the resource request table of the node N2 is as shown in FIG.
When lock = 0, the resources inst-slot and reg0 overlap each other, so it is determined that registration is not possible.

When it is determined in step S6 that the resource request table of the node N2 cannot be registered in the resource request blackboard 73,
The resource request exclusive control unit 71 determines that there is no unprocessed node in the schedule candidate instruction 5 (step S4).
Is NO), the variable clock is incremented by 1 (step S5), and the same processing as described above is performed again.

The variable clock is incremented by 1 to c
Even if lock = 1, the resource m-bus overlaps when the pointer to the node N4 is set in the variable node, and the resource reg0 overlaps when the pointer to the node N2 is set in the variable node. The request exclusive control unit 71 displays the nodes N4 and N2 on the resource request blackboard 73.
It is determined that the contents of the resource request table of 1 cannot be registered (step S6), and the variable clock is incremented by 1 (step S5).

The variable clock is incremented by 1 and c
When the pointer to the node N4 is set in the variable node after setting lock = 2, c of the resource request blackboard 73 is set.
Since the position of lock = 2 is blank and resource conflict does not occur, it is determined that the content of the resource request table of the node N4 can be registered (step S6).

When the resource request exclusive control unit 71 determines that the content of the resource request table of the node N4 can be registered in the resource request blackboard 73, the timing control unit 81 stores the content of the timing map table of the node N4 in the timing map blackboard 83. Determine if you can register (step S
7). In this case, since the timing map table corresponding to the node N4 does not exist, the timing control unit 81 determines that it can be registered.

When the timing control unit 81 determines that the resource request exclusion control unit 71 can register the contents of the resource request table of the node N4 shown in FIG. To register (step S
8). Further, in step S8, the timing control unit 81 decrements the remaining node number of all the nodes pointed to by the reference node pointer 906 of the node N3 in the data dependence graph 3, by one, and thereafter, the schedule candidate instruction extracting means. 4 is instructed to extract the schedule candidate instruction.

When this instruction is received, the schedule candidate instruction extracting means 4 makes the node corresponding to the machine language instruction, which has already been scheduled and must be executed, dependent on the node corresponding to the data. It is extracted from the graph 3 and the pointer to that node is output as the schedule candidate instruction 5. In this case, node N
2, pointers to N5 are output as the schedule candidate instruction 5.

When the pointers to the nodes N2 and N5 are output as the schedule candidate instruction 5 from the schedule candidate instruction extracting means 4, the resource request exclusive control unit 71 outputs one of them (for example, the pointer to the node N2). Variable no
It is set to de (step S3), and the same processing as described above is performed for the node N2.

Thereafter, the same processing as described above is performed, and FIG.
As shown in FIG. 1, the contents of the resource request table and the timing map table of the machine language instruction corresponding to the nodes N4, N2, N5 are sequentially registered in the resource request blackboard 73 and the timing map blackboard 83, and the nodes N4, N2, N5 The corresponding machine language instruction and the machine clock that schedules it are sequentially registered in the schedule table 84.

When the resource request table and the timing map program of the machine language instruction corresponding to the node N5 are registered in the resource request blackboard 73 and the timing map blackboard 83, the schedule candidate command extracting means 4 is data dependent as the schedule candidate command 5. The pointers to the nodes N3 and N6 in the graph 3 are output.

When the pointers to the nodes N3 and N6 are output as the schedule candidate instruction 5, the resource request exclusive control unit 71 sets one of them (the pointer to the node N3) in the variable node ( Step S3). At this time, the variable clock is “5”.

After that, the resource request exclusive control unit 71 determines whether or not the resource request table of the node N3 can be registered in the resource request blackboard 73 (step S6). In this case, the resource request table of the node N3 has the content shown in FIG. 6C, and the resource inst-slot overlaps at the position of clock = 5 on the resource request blackboard 73, so step S
The determination result of 6 is NO. As a result, the resource request exclusive control unit 71 sets the content of the remaining node N6 in the schedule candidate instruction 5 in the variable node (step S3),
The process of step S6 is performed.

In this case, the resource request table of the node N6 has the contents shown in FIG. 6 (F), and at the position of clock = 5 on the resource request blackboard 73, the resource inst-slot,
Since reg3 overlaps, the determination result of step S6 is NO.

Thereafter, the resource request exclusive control unit 71 increments the variable clock by 1 (step S5) since there is no unprocessed node in the schedule candidate instruction 5 (step S4 is NO), and then the above-mentioned processing is performed. Perform the same processing as.

The variable clock is incremented by 1 to c
When the content of the node N3 is set in the variable node after setting lock = 6, the cloc of the resource request blackboard 73
Since the position of k = 6 is blank, the resource request exclusive control unit 71 determines that the resource request table of the node N3 can be registered in the resource request blackboard 73 (step S6).

When the resource request exclusive control unit 71 determines that the resource request table of the node N3 can be registered, the timing control unit 81 can register the timing map table of the node N3 on the timing map blackboard 83. Is determined (step S7).

In this case, the timing map table of the node N3 has the contents shown in FIG. 7B. Since the timing add1 overlaps at the position of clock = 6 on the timing map blackboard 83, the timing control unit 81 Determines that the timing map table of the node N3 cannot be registered in the timing map blackboard 83.

When the timing controller 81 determines that the timing map table of the node N3 cannot be registered in the timing map blackboard 83 (NO in step S7),
The resource request exclusive control unit 71 sets the content of the remaining node N6 in the schedule candidate instruction 5 in the variable node (step S3), and performs the process of step S6.

In this case, since the content of the resource request table of the node N6 is as shown in FIG. 6F, it is determined that the resource request blackboard 73 can be registered at the position of clock = 6.

When the resource request exclusive control unit 71 determines that the resource request table of the node N6 can be registered, the timing control unit 81 can register the timing map table of the node N6 on the timing map blackboard 83. Is determined (step S7).

In this case, the timing map table of the node N6 has the contents shown in FIG. 7D, and the timing add1 overlaps at the position of clock = 6 on the timing map blackboard 83. Determines that the timing map table of the node N3 cannot be registered in the timing map blackboard 83.

Timing map Blackboard 83, node N6
Timing map table of timing map blackboard 8
If it is determined that the schedule request instruction 5 has no unprocessed nodes (NO in step S4), the resource request exclusive control unit 71 sets the variable clock to 1
It is incremented (step S5), and then the same processing as described above is performed.

The variable clock is incremented by 1 and c
When the pointer to the node N3 is set to the variable node after setting lock = 7 (step S3), the position of clock = 7 on the resource request blackboard 73 is blank, so the resource request exclusive control unit 71 It is determined that the resource request table of the node N3 can be registered in the resource request blackboard 73 (step S6).

When the resource request exclusive control unit 71 determines that the resource request table of the node N3 can be registered, the timing control unit 81 can register the timing map table of the node N3 on the timing map blackboard 83. Is determined (step S7).

In this case, since the position of clock7 in the timing map table of the node N3 is blank, the timing controller 81 judges that the contents of the timing map table of the node N3 can be registered in the timing map blackboard 83. become. Thereafter, the same processing as that described above is performed, and the contents of the resource request table and the timing map table of the machine language instruction corresponding to the nodes N3 and N6 are sequentially registered in the resource request blackboard 73 and the timing map blackboard 83, and at the same time, the node N3. The machine language instruction corresponding to N6 and the machine clock that schedules it are sequentially registered in the schedule table 84. Then, when the above-described processing is performed for all the nodes, the control means 6 ends the processing.

As described above, in this embodiment, the machine language instructions are not only scheduled based on the resource competition, but the machine language instructions are scheduled in consideration of the constraint of the instruction issue timing between the machine language instructions. Therefore, as shown in clock = 5, 6, 7 in FIG. 11, the machine language instruction “ST% 1, X” is the machine language instruction “ADD% 3.
It will be scheduled two machine clocks after the issuance timing of "% 0,% 2". Therefore, if cl
The machine language instruction "ADD% 3,% 0,%" that is scheduled to clock = 5 even if it is scheduled to ock6
2 ”and the machine language instruction“ ST% 1, X ”does not cause resource competition, and if there is a machine language instruction satisfying the constraint of the instruction issue timing, the machine language instruction is clock = 6.
Therefore, it is possible to improve the execution efficiency of the program as compared with the case where the machine language instruction is scheduled only based on the resource competition.

[0083]

The present invention described above, according to the present invention, since there <br/> includes issuing timing control means for scheduling the machine language instructions in consideration of the constraints of the instruction issue timing between the machine language instructions, hard It is possible to generate a machine language instruction that can reduce interlock in the hardware as compared with the conventional technique that only schedules the machine language instruction only on the basis of the contention of the hardware resource. The effect is that the execution efficiency of the target program can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration example of a timing map table.

FIG. 3 is a flowchart showing a processing example of a control unit 6.

FIG. 4 is a diagram showing an example of a machine language instruction sequence.

FIG. 5 is a diagram showing an example of a source program.

FIG. 6 is a diagram showing an example of contents of a resource request table.

FIG. 7 is a diagram showing an example of contents of a timing map table.

FIG. 8 is a diagram showing an example of a data dependence graph 3.

9 is a diagram showing an example of the contents of nodes in the data dependence graph 3. FIG.

FIG. 10 is a diagram showing an example of contents of a node N5.

FIG. 11: Resource request blackboard 73, timing map blackboard 8
It is the figure which showed the example of contents of 3.

FIG. 12 is a diagram showing an example of contents of a resource request table.

[Explanation of symbols]

1 ... Instruction scheduler 2 ... Data dependence graph creation means 3 ... Data dependence graph 4. Schedule candidate instruction extracting means 5 ... Schedule candidate instruction 6 ... Control means 7 ... Resource request exclusive control means 71 ... Resource request exclusive control unit 72-1 to 72-m ... Resource request table 73 ... Resource request blackboard 8 ... Issuance timing control means 81 ... Timing control unit 82-1 to 82-n ... Timing map table 83 ... Timing map blackboard 84 ... Schedule table

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-6-131197 (JP, A) International Publication 94/22079 (WO, A1) M.M. JOHNSON, Translated by Murakami "Superscalar Processor" (1994-8) Nikkei BP, p. 175〜198 (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 9/45

Claims (2)

(57) [Claims] 1. A machine language instruction scheduling device of a compiling device for scheduling a sequence of machine language instruction sequences generated based on a source program so that the execution efficiency of the program is improved, in the machine language instruction sequence. From the schedule candidate instruction extracting means for extracting all machine language instructions in a schedulable state, and a resource request table in which the resources necessary for executing the machine language instruction are described in machine clock units for each machine language instruction. And a timing map table in which constraint information indicating a constraint of instruction issue timing between machine language instructions is described for each machine language instruction, and a machine language instruction extracted by the schedule candidate instruction extracting means.
Trying the current schedule for any of the orders
Scheduled Machine at Machine Clock
Determine whether or not there is a conflict between the word command and the resource, and compete for the resource.
If it is determined that no match occurs, the machine language instruction and schedule
The machine language instruction that has been completed is the timing map
Instruction issuer between machine language instructions indicated by constraint information in the table
Judge whether or not the imming constraint is satisfied and satisfy the constraint.
When it is determined that they are added, the machine language instruction is
Schedule to schedule next to a machined instruction
And control means for performing Yuru processing, said control means, whether or not competition of the resource does not occur or determine
If it is determined that competition for resources will occur,
A candidate for extracting the schedule candidate instruction other than the machine language instruction
Judge whether there is a machine language instruction extracted by Dan, and if there is,
For any of them,
If not, advance the machine clock by one and restart.
The machine extracted by the schedule candidate instruction extracting means
The schedule process for any of the word commands
To determine whether or not the above constraints are satisfied.
When it is determined that the constraints are not satisfied,
The schedule candidate instruction extraction means other than the machine language instruction is extracted.
Judge whether there is a machine language instruction issued, and if so,
For any of the above, perform the schedule process,
If not, advance the machine clock by one and then again.
Machine language instruction extracted by the schedule candidate instruction extraction means
Perform the schedule process for any of the
A machine language instruction scheduling apparatus characterized by the following features. 2. A schedule dependence instruction extraction means, comprising data dependence graph creation means for creating a data dependence graph representing a data dependence relationship between machine language instructions of a machine language instruction sequence generated based on the source program. The machine language instruction scheduling device according to claim 1, wherein the machine language instruction scheduling apparatus extracts a machine language instruction that is in a schedulable state based on the data dependence graph.