JP2831742B2 - Architecture synthesis system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a hardware architectural synthesis system, and more particularly, to enabling a designer to control a hardware resource allocation process. It was done.

(Prior Art) With the enlargement of digital systems, various CAD systems have been developed for the purpose of improving design efficiency.
In particular, recently, as a system that provides support from a higher stage than functional design, an architecture synthesis system that receives a specification represented by a software algorithm and generates a hardware configuration that realizes the algorithm has been realized.

Usually, in this architecture synthesis system,
The designer pays attention only to the processing algorithm to be realized without paying attention to the specific hardware configuration, and describes the hardware specifications using a syntax similar to a general-purpose programming language. Then, the system inputs such a specification description, extracts the order and parallelism of the operations included in the specification description, and determines (scheduling) the execution order of the operations. Then, hardware resources necessary for performing the operation in accordance with the execution order, that is, resource allocation (data path allocation) of a computing unit, a register, and a transfer path are performed. These series of processes are automatically performed according to a certain corrugation without the intervention of a designer.

For the scheduling, the ASAP scheduling method described in the following document [1] is used so that the process described in the specification can be executed in as few steps as possible. For the data path allocation, the following method is used to reduce the number of resources as much as possible. The clique splitting technique described in Reference [2] is often used.

[References] [1] MCMcFarland, ACPaker, R. Camposano, “Tuto
rial on High-Level Synthesis ", 25th ACM / IEEE Desig
n Automation Conference, 1988, pp330-336. [2] CJTseng, DPSiewiorek, “Automated Synthe
sis of Data Paths in Digital Systems ", IEEE Transac
tions on Computer-Aided Design, Vol.CAD-5, NO3, JUL
Y 1986, pp379-395. Here, the fact that the fastest scheduling method is automatically determined by the system is advantageous for designers in the sense that the speed cannot be further increased. The fact that the system completely automatically determines the determined data path allocation processing according to a certain algorithm has a problem in that the idea of the designer cannot be reflected.

For example, the designer says, "It is better to use the same register for variables x and y.", "I want to implement operations p and q with the same ALU.", "I want to implement variables x and y with the same register. The data path configuration cannot be generated in accordance with the determination or intention such as "

In addition, regarding the assignment of arithmetic units, in order to allocate resources based on only formal information such as the similarity of operands of arithmetic operations, for example, assignment of addition and division to the same arithmetic unit is not possible. The problem of generation often arises.

Furthermore, regarding the storage element allocation, the period during which the variable is valid is determined without considering the influence on the transfer path such as the increase in the number of multiplexers and the increase in the number of fan-outs of the storage element required as a result of sharing the storage element. In order to share as much as possible the non-overlapping lifetimes as much as possible, the variables selected at the beginning of the process are shared a lot, and the transfer paths of the storage elements corresponding to the variables are changed. On the other hand, there is a problem that variables selected later in the processing are not shared so much, resulting in an unbalanced data path configuration.

(Problems to be Solved by the Invention) As described above, in the conventional architectural synthesis system, the problem of hardware resource allocation can be solved by a short combination optimization problem without considering a configuration usually considered by a designer. As a result, the data path intended by the designer is not generated. Also,
Since a designer cannot take a design method of constructing a data path, there is a problem that it is not possible to reflect a designer's idea and to carry out a design suitable for an actual system.

Therefore, an object of the present invention is to provide an architecture synthesis system capable of generating a data path structure intended by a designer by reflecting the idea of the designer in a process of allocating hardware resources.

[Means for Solving the Problems] According to the present invention for solving the above problems, a hardware specification description is input, the order and parallelism of operations included in the description are extracted, and scheduling and data paths are performed. In an architecture synthesizing system for performing allocation, a scheduling result storage unit for storing an execution schedule of an operation, a hardware resource storage unit for storing required hardware resources, an allocation execution unit for allocating hardware resources, Execution history storage means for storing a history, execution control means for controlling the resource allocation process, interrupting the execution of resource allocation processing by the allocation execution means in response to an instruction from the operator, and then changing the idea of the operator. An instruction unit for executing a process according to the reflected instruction is provided.

(Operation) In the architecture synthesis system of the present invention, a hardware specification description is input, the order and parallelism of the operations included in the description are extracted, and scheduling and data path allocation are automatically performed. , And the process is executed in accordance with an instruction reflecting the thought of the operator.

(Example) Hereinafter, an example of the present invention will be described.

FIG. 1 is a block diagram showing, in particular, a storage element allocation function in an architecture synthesis system according to an embodiment of the present invention.

As shown in the figure, the architecture synthesis system of this example includes a scheduling result storage unit 1 that stores an execution schedule of an operation, a hardware resource storage unit 2 that stores necessary hardware resources, and an assignment of hardware resources. A resource allocation execution unit 3 to perform, an execution history storage unit 4 for storing a history of the allocation process of the means 3, an execution control unit 5 for controlling a resource allocation process, and the execution of the allocation in accordance with an instruction from the operator side A support unit 6 is provided for interrupting the execution of the resource allocation process by the unit 3 and thereafter executing the process according to an instruction reflecting the thought of the operator. Further, a data path display section 7 for displaying the generated data path and an execution history display section 8 for displaying the execution history are provided.

The scheduling result storage unit 1 stores the operations executed in each step in a directed graph as shown in FIG.

In FIG. 2, nodes represent operations and edges represent data flows. As shown in the legend in FIG. 3, the node has, as attributes, a type of operation, a step for executing the operation, an operation unit id for executing the operation, a variable name for storing the operation result, and its bit width. The operation type I node represents an input variable, and the operation type O node represents an output variable.

The hardware resource storage unit 2 stores information on the assigned computing units and storage elements as shown in FIG. FIG. 5 shows the legend. R is a register, and the attribute of R is a register name and a corresponding node list in the scheduling storage unit 1.

FIG. 4 stores the result of assigning a storage element having the same name as the variable name to each variable alive in a plurality of steps as an initial value.

The data path display unit 7 displays, on the display 7D, a data path for executing the operation of the scheduling result storage unit 1 using the resources of the hardware resource storage unit 2. FIG. 6 shows an example in which the information shown in FIGS. 2 and 4 is displayed by the data path display unit 7. The suffix D of the reference sign indicates that it is a screen.

The instructing unit 6 is constituted by a keyboard or the like, and instructs a storage element sharing process performed by the resource allocation executing unit 3 by using the following commands stop, cont, return, and alt.

stop: Suspend the execution of resource allocation and display the resulting data path.

cont: Release the suspension of execution and continue processing.

return ... Return the state of resource allocation to the previous state.

alt-Executes a different resource allocation method than previously performed.

The resource allocation execution unit 3 sequentially obtains and shares other storage elements having the minimum ids whose lifetimes do not overlap with each other in order from the storage element with the smallest id stored in the hardware resource storage 2.

The execution history storage unit 4 stores a history of sharing by the resource allocation execution unit 3 and an instruction input to the execution control unit 5. The execution history display unit 8 displays the contents of the execution history storage unit 4 on a display.

In the above configuration, it is assumed that the information shown in FIGS. 2 and 4 is stored in the scheduling result storage unit 1 and the hardware resource storage unit 2, respectively. The results obtained are shown in FIG. The horizontal direction in FIG. 7 represents a variable or an assigned storage element, and the vertical direction represents an operation execution step. The symbol L in the figure represents a period during which the variable is valid, and the symbol D represents a period during which the variable is not valid.

FIG. 8 shows the result of detecting a sharable variable from the lifetime table LTT of FIG. In FIG.
Nodes in the graph represent registers (variables), and edges represent that registers at both ends can be shared. Here, in the lifetime table LTT of FIG. 7, it is determined that the registers (variables) x and y can be shared when one of the following [Rule 1] and [Rule 2] is satisfied.

[Rule 1] In the columns of two variables x and y, the periods having the symbol L do not overlap.

[Rule 2] In a column of two variables x and y, both symbols L
And for all these steps x ends L at this step and y starts L at this step.

Therefore, it is assumed that the designer has entered the following command in the execution control unit 5 while looking at the display of the data path in FIG. 6 and intending to intervene in sharing the variables x2 and x7.

> Stop x2, x7;> indicates a prompt. This command uses the variables x2 and
Indicates that processing is interrupted when sharing is executed for x7 and the data path at that time is displayed.

The resource allocation execution unit 3 executes sharing in the hardware resource storage unit 2 in order from a register having a smaller id. That is, from the graph of FIG.
Since x1 and x4 are shared and x6 can share x1 and x4, x1 and x6 are shared next. here,
id of register created by sharing registers with id w1 and w2
Is set to min (w1, w2), and the execution history storage unit 8 stores w1, w2, min
The three sets of {w1, w2} are stored. Therefore, a triple (4,7,4) and (4,9,4) are stored by the above two sharing.

Next, the resource allocation execution unit 3 shares the variables x2 and x5. The storage contents of the scheduling information storage unit 1, the hardware resource storage unit 2, and the execution history storage unit 4 at this time are shown in FIGS. 9 to 11, respectively.

Here, the execution control unit 5 interrupts the processing of the resource allocation execution unit 3 by the command "stop", and causes the data path display unit 7 to display the data path as shown in FIG.

Now, the designer looks at the display of the data path in FIG. 12, judges that the transfer path for input / output of the variable x2 is not desirable, and uses the execution history display unit 8 to check the information in FIG. Is displayed on the display 8D. Using this information and the information shown in FIG. 6 displayed in another window using, for example, a multi-window,
Since the id is described, it is understood that the variables x2 and x5 have been shared.

Next, when the designer determines from the above information that it is better not to share the variables x2 and x5,
For example, assume that the following command is input.

> Return 1; This return command represents an instruction to cancel the processing up to the time point n stored in the execution history storage unit 4 and display the resulting data path when the operand is n (> 0). . FIG. 13 shows the processing procedure for n = 1.

In FIG. 13, in step S1, the latest history (w1, w2, w3) is obtained from the execution history storage unit, and in step S2, a list L of the hardware resource storage unit 2 having w3 as id is obtained, and step S3 is performed.
Then, w = max (w1, w2) is obtained, and the last element Z of the node list in the list L is obtained in step S4.

Next, in step S5, a variable name S of an attribute of the node r of the scheduling information storage unit 1 having Z as id is obtained,
In step S6, (w, R (S, (Z)) is added to the hardware resource storage unit, Z is removed from the attribute of list L, and
In step S7, the storage element name of the node r is set to S, and in step S8, the resulting data path is displayed.

Specifically, in step S1, (w1, w
(2, w3) = (5,8,5), and the list L = (5, R, (x2, (7,10))) is obtained from FIG. 4 in step S2. Therefore, in steps S3 and S4, w = 8 and z = 10.

Therefore, S becomes x5 from FIG. 2, and after execution of steps S6 and S7, the contents of the scheduling result storage unit 1 and the hardware resource storage unit 2 are as shown in FIGS. 14 and 15, respectively, and the execution history storage A history of cancellation is stored in the unit 4 as shown in FIG. 16, and a data path as shown in FIG. 17 is displayed on the display 7D.

In the case of n ≠ 2, the processing procedure excluding step S8 of return 1; may be sequentially performed for the latest n histories in the execution history storage unit 4. However, if the target of the return command having n histories, that is, the history of only a part of the m histories corresponding to return m; is included, for example, the state after execution of the return command is returned. When all of the objects are included, that part may be skipped and the processing in FIG. 13 may be executed.

Next, it is assumed that the designer looks at the data path in FIG. 17 and inputs the following command.

>Alt; This command indicates that sharing other than that stored in the execution history storage unit 5 is performed. That is, the command can control the process of the resource allocation execution unit 3 so as not to execute the process canceled as described above again. Specifically, the resource allocation execution unit 3 restarts the sharing process, and first tries to share x2 and x5.
By the alt command, the execution control unit 5 detects that (5,8,5) exists in the execution history storage unit 4, and causes the resource allocation execution unit 3 to prohibit the execution of the same content allocation. As a result, the resource allocation execution unit 3 attempts another sharing, and the variable x6 becomes x1.
Since x2 and x7 are already shared, x2 and x7 are shared.

Here, the execution of sharing can be interrupted again by the previously input stop command, and the data path after reconsideration as shown in FIG. 18 can be displayed on the display 7D. When the designer determines that appropriate sharing has been performed by looking at the data path,
The following command can instruct the resource allocation execution unit 3 to continue the processing.

>Cont; In this case, the resource allocation execution unit 3 shares the variables x3 and x5 and ends the processing. The contents of the scheduling result storage unit 1, hardware resource storage unit 2, and execution history storage unit 4 are shown in FIGS. 19 to 21, respectively. FIG. 22 shows a display result by the data path display unit 7 at this time.

As described above, in the present example, the processing is interrupted at the point in time when the sharing of the variable focused by the designer is performed by the command “stop”, the processing is returned to the desired point in time by the command “return”, and the same is executed by the command “alt”. The assignment process can be prohibited, and another assignment process can be executed by the command “cont”.

Therefore, the operator can change the unintended assignment contents by setting the conditions to be interrupted in advance, and can perform the intended resource assignment in consideration of the actual hardware convenience. .

In the above-described embodiment, the execution control unit 5 allows the designer to interrupt when the sharing of the variable of interest is performed, but the processing of the resource allocation execution unit 13 is performed immediately before the sharing is performed. Suspend, display the data path at that stage, specify the resource that is about to be shared by, for example, blinking on the display, etc., and ask the designer to enter whether or not to allow the sharing You may do so.

Further, in the above embodiment, the resource allocation execution unit 3 can be interrupted by focusing on a specific resource.
For example, considering a cost function f for evaluating the amount of hardware resources, it is also possible to suspend when f ≦ M (M is a constant). The execution control unit 5 interrupts each time a resource is shared by the resource allocation execution unit 3, displays the data path at that time, and allows the designer to input whether to cancel the sharing. Is also good. The execution control unit 5 may be configured to be able to appropriately cancel the once set interruption condition. Further, only the history at the past K time points may be stored in the execution history storage unit 4. K is a preset constant, and may be set and changed when the execution control unit 5 can input a command. Thereby, for example, the processing of the alt command in the above-described embodiment can be set to “apply a strategy that has not been performed at the past K time points (order of combinations for performing sharing)”.

Furthermore, the scheduling information storage unit 1 and the hardware resource storage unit 2 may be configured to store n (≧ 2) data, and the execution control unit 5 may be able to store the data at the time of interruption. it can. Also, the function of the alt command described in the above embodiment enables a method of obtaining a design result by various strategies, displaying the data on the data path display unit, comparing the data, and selecting an optimum one. .

Further, in the above embodiment, the assignment of the storage element has been described, but other resource assignments, for example, assignment of a computing unit, assignment of a shared bus for a transfer path) may be used.

In addition, the present invention can be appropriately modified and implemented without departing from the gist thereof.

[Effects of the Invention] As described above in detail, according to the present invention, the designer interrupts the resource allocation process performed by the resource allocation execution means at an arbitrary condition and at an arbitrary time, and After grasping the allocation process, it is possible to appropriately cancel the previously executed allocation process and perform a new resource allocation using a different strategy from the previous one, etc., and to shorten the data path intended by the designer in a short time. Can be generated.

[Brief description of the drawings]

FIG. 1 is a block diagram of an architecture synthesizing system according to an embodiment of the present invention, FIG. 2 is an explanatory diagram showing contents stored in a scheduling result storage unit, FIG. 3 is an explanatory diagram showing a legend, and FIG. FIG. 5 is an explanatory diagram showing a legend, FIG. 6 is an explanatory diagram showing a display example of a data path display unit, and FIG. 7 is an explanatory diagram of a lifetime table. , FIG. 8 is an explanatory view of a graph showing sharability between variables obtained by processing a lifetime table, and FIGS. 9 and 10 are other storage contents of a scheduling information storage unit and a hardware resource storage unit. FIG. 11 is an explanatory diagram showing a display example of an execution history display unit, FIG. 12 is an explanatory diagram showing a display example of a data path display unit corresponding to FIG. 9 and FIG. The figure shows the processing procedure of the return command. FIGS. 14, 15 and 16 are explanatory diagrams showing the contents of a scheduling result storage unit, a hardware resource storage unit, and an execution history storage unit after execution of a return command, respectively.
FIG. 17 is an explanatory diagram of the display contents of the data path display unit at that time, FIG. 18 is an explanatory diagram of a data path display example after the sharing process, and FIG. 19 is an explanation of the storage contents of the final result scheduling result storage unit FIG. 20, FIG. 20 is an explanatory diagram of the storage contents of the hardware resource storage unit of the final result, FIG. 21 is an explanatory diagram of the storage contents of the execution storage unit of the final result, and FIG. 22 is a data path display example of the final result. FIG. 1 scheduling result storage unit 2 hardware resource storage unit 3 resource allocation execution unit 4 execution history storage unit 5 execution control unit 6 display unit 7 data path display unit 8 Execution history display section

Claims (3)

(57) [Claims] A scheduling result storage for storing an operation execution schedule in an architecture synthesis system that inputs a hardware specification description, extracts the order and parallelism of operations included in the description, and performs scheduling and data path allocation. Means, hardware resource storage means for storing necessary hardware resources, allocation execution means for allocating hardware resources, execution history storage means for storing a history of the allocation process, execution for controlling the resource allocation process Control means, instruction means for interrupting execution of resource allocation processing by the allocation execution means in accordance with an instruction from the operator side, and thereafter executing processing in accordance with an instruction reflecting the idea of the operator. A featured architectural synthesis system. 2. The architecture synthesizing system according to claim 1, wherein, after the interruption according to the instruction of said instruction means, said execution control means stores the contents stored in said schedule result storage means and said hardware resource storage means. The history number n in the history stored by the execution history storage means
(≧ 1) An architecture synthesizing system characterized by returning to a state before the time point. 3. The architecture synthesizing system according to claim 1, wherein, after the interruption according to the instruction of said instruction means, said execution control means sets a time point of a history number n (≧ 1) stored in said execution history storage means. An architecture synthesizing system characterized by executing a resource allocation process different from the hardware resource allocation process that appears in the history up to the previous time.