JP2830660B2 - Memory dump display method of microcomputer controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory dump display system for a microcomputer controller.

[0002]

2. Description of the Related Art In a conventional memory dump display method of a microcomputer control device, a method of outputting an operation state and input / output information to an external device is to directly output the contents of a specified memory at a specified time to a printer. Printing,
There are a method of displaying the data on a light emitting diode (LED) array or various display devices, and a method of reading out the contents of a specified memory at a fixed period and displaying the contents on an LED array or various display devices in real time. Also, after storing the time series change of the specified memory in a specific continuous memory (memory trace), it is printed or displayed on a printer or various display devices so that the operation status of the microcomputer control device and the input / output information can be obtained. It had a means for outputting a series change.

[0003]

In the conventional microcomputer controller memory dump display method, when it is desired to know a time series change of the operation state of the microcomputer controller or input / output information, the contents of the memory are read in real time. In the display method, if the time-series change is too fast, the display may be overlooked or unrecognizable even if you look at the display.In addition, in the method using the memory trace, a display device that can output multiple memories is required because multiple memories are displayed. There is a problem that it is expensive and takes up space, and there is a problem that an interface function of a display device is required for a microcomputer control device, and control becomes complicated.

Further, a method of displaying a plurality of traced memories by a real-time display method while designating a memory address from the outside at any time has been performed, but there has been a problem that the operation of designating the memory address is troublesome.

[0005]

According to the present invention, there is provided a memory dump display system for a microcomputer control device having a function of displaying the contents of a memory unit on a display unit at a predetermined cycle. An input means for inputting a selection signal for selecting a display mode, and comparing the contents of the memory unit with the contents of the memory unit one cycle before in the cycle. There are storage means for storing the data in the memory and display means for reading out the contents from the first-in first-out memory at a cycle longer than the cycle and displaying the contents on the display unit.

[0006]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a communication control apparatus according to one embodiment of the present invention.

In FIG. 1, a terminal interface unit 1 for interfacing with a terminal connected to a communication control device according to the present embodiment and an interrupt control circuit (INTC) 2 for controlling an interrupt to a microprocessor (MPU).
And a timer circuit (TIMER) 3 for supplying a basic clock to the MPU 4 and the INTC 2, and a microprocessor (CP) for controlling the communication control device as a whole via a bus, such as control of a communication operation and control of a display operation described later.
U) 4, a parallel input / output interface circuit (PIO) 5 using parallel / serial conversion, a dip switch (DSW) 10 connected to the PIO 5, a light emitting diode (LED) 11 for one word, and a program realized by the MPU 4. , A working memory, a line buffer, etc., and a first-in-first memory (F) configured by the memory control described in detail with reference to FIGS.
It comprises a memory section 6 including an IFO memory 12, a direct memory access transfer control circuit (DMAC) 7, a communication control circuit 8, and a line interface section 9. The DSW 10 includes a 12-bit switch for specifying an address (dump address) of a memory to be displayed and a 1-bit switch for specifying a display mode.

Next, the operation of this embodiment will be described.

The DMAC 7 transfers the information input from the terminal interface unit 1 to the communication control circuit 8 via the line buffer of the memory unit 6 and transmits the information from the line interface unit 9. This is performed by outputting received information to the interface unit 1.

The internal display function of the memory unit 6 is performed as follows.

The MPU 4 counts an interrupt signal from the INTC 2 with a period of 10 ms, and outputs a PIO every 100 ms.
Then, if the display mode is the real-time display mode, the data of the memory unit 6 specified by the dump address is read and the PIO 5 is tried. PIO5 sends the written data to LED1
1 is latched and output.

If the display mode is the slow display mode, the data specified by the dump address is read. If the data is different from the data previously input to the FIFO memory 12, the data is input to the FIFO memory 12; Data is output from the FIFO memory 12 every 500 ms, and output to the LED 11 via the PIO 5.

When the FIFO memory 12 is empty, the output operation from the FIFO memory 12 is not performed, but the previously output data is latched by the PIO 5 and the LED 1
1 is output. When the FIFO memory 12 becomes full, input to the FIFO memory 12 is stopped thereafter, output is performed every 500 ms until the FIFO memory 12 becomes empty, and when it becomes empty, "FF" is output in hexadecimal notation as a halt code. This state is released when the DSW 10 designates the real-time display mode.

In addition to this, there is a method of emptying the FIFO memory 12 when it becomes full, a method of overwriting, a method of restricting the input, and a method of inputting when the full state is released. Since the continuity of the time series change of the memory thus obtained cannot be guaranteed, the halt code is displayed.

FIG. 2 shows the F in the memory unit 6 in the present embodiment.
FIG. 2 is a diagram showing a configuration of an IFO memory 12.

In FIG. 2, a memory unit 6 stores an address FS.
A 64-byte continuous memory area (M) 13 from TA to FEND, an input pointer (INP) 14, an output pointer (OUTP) 15, and a flag (FULL FLA) indicating that the FIFO memory 12 is full.
G) 16 and a flag (EMPTY FLAG) 17 indicating that the FIFO memory 12 has become empty.

The input to the FIFO memory 12 is INP 14
This is performed by performing a write operation to the memory (M (INP)) and an update operation of the INP 14. The initial value of both INP14 and OUTP15 is FSTA, and the update is performed by adding 1 to the value and resetting it to FSTA when the value exceeds FEND.
The full state of the FIFO memory 12 is detected when the value of INP14 becomes equal to the value of OUTP15 after input to the FIFO memory 12. The detection of the empty state is F
After the output operation from the IFO memory 12 is detected, the value of OUTP15 becomes equal to the value of INP14.

FIG. 3 is a flowchart showing a display process executed by the MPU 4 in this embodiment.

Next, the operation of the display processing of this embodiment will be described with reference to FIGS.

In step S18, processing is started. ZD in S19
The designation of the display mode designation dump address is input from the SW 10. According to the determination of the display mode in S20, S21 is executed in the case of the real time display mode, and S24 is executed in the case of the slow display mode. In step S21, initialization of pointers and flags used in the slow display mode
NP14, OUTP15, FULL FLAG16 and EMPTY FLAG17 are initialized. In step S22, the contents of the memory unit 6 specified by the dump address are
To output to the LED 11 via the. S at S23
The display process starting with 18 ends.

At S24, if the contents of the memory section 6 specified by the dump address and the data previously input to the FIFO memory 12 match, S30 is executed, and if not, S25 is executed. The previously entered data is S
At the time of input to the FIFO memory 12 at 26, the data is saved in another one-word area or the input pointer INP14 is set to 1
It is obtained by reading back and reading M (INP14). In this embodiment, the latter method is used.

At step S25, FULL FLAG 16 is set to "1".
Is determined, and if "1", S30 is executed, and if "0", S26 is executed. FI at S26
The input operation to the FO memory 12 is performed. EMPT at S27
A reset operation for setting Y FLAG 17 to “0” is performed.
At S28, an operation of detecting the full state of the FIFO memory 12 is performed. If it is full, execute S29. If it is not full, execute S30.
Execute S29 sets FULL FLAG16 to "1".
Perform a set operation.

At S30, a 500 ms period is detected, and 5
If the cycle is 00 ms, S31 is executed; otherwise, the process ends in S23. FULL FLAG in S31
It is determined whether 16 is “1” or “0”. If “1”, S33 is executed, and if “0”, S32 is executed. In S32, it is determined whether the EMPTY FLAG 17 is "1" or "0". If "1", the process ends in S23, and if "0", S34 is executed. S33
Then, it is determined whether the EMPTY FLAG 17 is “1” or “0”. If “1”, S37 is executed, and if “0”, S34 is executed. The output operation from the S34 FIFO memory 12 is performed.

At S35, an operation of detecting the empty state of the FIFO memory 12 is performed. S36 if empty
Is executed, otherwise, the process ends in S23. S
At 36, an operation of setting the EMPTY FLAG 17 to "1" is performed. Every 100 ms, the display process is started in S18, the DSW 10 is read in S19, and in the case of the real time display mode in S20, the slow display mode is initialized in S21, the memory data of the dump address is output in S22, and the process proceeds to S23. The process ends.

In the case of the slow display mode in S20, the following (1) to (10) are executed.

(1) If data is the same as last time, FIFO
No input is made to the memory 12 (S24).

(2) No input is made once the FIFO memory 12 is full (S25).

(3) After the input to the FIFO memory 12, the empty state is released (S26, S27).

(4) When the full state is detected, FULL F
The LAG 16 is set (S28, S29).

(5) No output is made unless the period reaches 500 ms (S30).

(6) When the full state is not detected and the empty state is not detected, the FIFO memory 12 outputs the data to the LED 11 (S31, S32, S34).

(7) No force is applied before the detection of the full state and the empty state (S31, S32).

(8) After detecting the full state and not in the empty state, the FIFO memory 12 outputs to the LED 11 (S31, S33, S34).

(9) After detecting the full state and the empty state, a halt code is output to the LED 11 (S3).
1, S33, S37).

(10) If an empty state is detected after outputting data from the FIFO memory 12, an empty flag is set (S35, S36).

[0037]

As described above, according to the present invention, in the memory dump display system of the microcomputer control device having the function of displaying the contents of the memory unit on the display unit at a predetermined cycle, the display mode is selected. Input means for inputting a signal; comparing the contents of the memory unit with the contents of the memory unit one cycle before in the cycle;
Storage means for storing the contents in the FIFO memory; and display means for reading the contents from the FIFO memory at a cycle longer than the cycle and displaying the contents on the display unit, wherein the contents of the memory unit are periodically displayed by a selection signal from the input means. , Or display by the storage means and the display means, so that even if the time series change of the contents of the memory portion is fast, the contents can be displayed without overlooking the contents. This has the effect of eliminating the need for a plurality of display devices for displaying the contents of the plurality of memory units and an interface for the plurality of display devices.

Furthermore, since the data is not input to the FIFO memory if it matches the contents of the memory unit one cycle before, the overflow of the FIFO memory caused by the difference between the input cycle and the output cycle can be prevented. I have.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a communication control device according to an embodiment of the present invention.

FIG. 2 is a diagram showing an F in a memory unit according to the embodiment shown in FIG. 1;
FIG. 2 is a diagram illustrating a configuration of an IFO memory.

FIG. 3 is a flowchart showing a display process executed by an MPU in the embodiment shown in FIG. 1;

[Explanation of symbols]

Reference Signs List 1 terminal interface unit 2 interrupt control circuit (INTC) 3 timer circuit (TIMER) 4 microprocessor (MPU) 5 parallel input / output interface circuit (PIO) 6 memory unit 7 direct memory access transfer control circuit (DMA)
C) 8 Communication control circuit 9 Line interface unit 10 Dip switch (DSW) 11 Light emitting diode (LED) 12 First effect out memory (FIF
O memory)

Claims (1)

(57) [Claims] An input means for inputting a selection signal for selecting a display mode in a memory dump display method of a microcomputer control device having a function of displaying the contents of a memory unit on a display unit at a predetermined cycle. A storage unit for comparing the contents of the memory unit with the contents of the memory unit one cycle before in a cycle, and storing the contents in a first-in first-out memory if they do not match; Display means for reading contents from a first-out memory and displaying the contents on the display unit, and periodically displaying the contents of the memory unit on the display unit according to the selection signal by the input means, or the storage means and Memory for a microcomputer control device, wherein the display is performed by either the display means or the display means. Dump display method.