JP2722028B2 - LCD control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LCD control system for controlling display of an LCD capable of displaying characters and graphics.

[0002]

2. Description of the Related Art FIG. 4 shows a conventional LCD control device of this kind. In the figure, 1 is a CPU, 2 is a data bus contention control circuit, 3 is a display SRAM, 4 is an LCD controller, 5 is an LCD unit, AD is an address bus, DB is a data bus, A is an address signal, and D and DD. Is a data signal, INH is a display data transfer inhibition signal, TINH is a display data transfer inhibition request signal, CP1 is a clock signal, LP
Is a line transfer pulse signal, and FP is a frame pulse signal. In the above-described apparatus, when various kinds of display are performed on the LCD unit 5, first, the CPU 1 controls the display SR.
When a predetermined address of the AM 3 is selected via the address bus AD and subsequently display data is output via the data bus DB, the display data is written to the predetermined address of the display SRAM 3. On the other hand, the LCD controller 4
Read the contents of the display SRAM 3 in a predetermined cycle and transfer it to the LCD unit 5. Therefore, when the display data is written to the display SRAM 3, the written display data is immediately stored on the LCD unit 5. Will be displayed.

[0005] FIG. 5 is a timing chart of the LCD controller 4. The display address signal A to the display SRAM 3 is updated in synchronization with the falling of a clock signal CP 2 (not shown) generated internally, and the clock signal is generated. The 8-bit display data D from the display SRAM 3 is input in synchronization with the rise of the signal CP2, and the 8-bit data D is similarly decomposed into 4-bit data DD in synchronization with the internally generated clock signal CP1. The data is output to the LCD unit 5. In this case, the LCD unit 5
In the case it has been used is large LCD of 320 × 240 dots as displayed in 77H _Z, the total data transfer time corresponding to one line and the data write time is about 54μs . In such a case, LC
The D controller 3, as shown in FIG.
After transferring data corresponding to one line of the unit 5 (the transfer time is about 45 μs in this example), the data transfer is stopped for a certain period of time (about 9 μs in this example). During this time, the busy signal BUSY is set to “ H "
Notify U1. Therefore, the CPU 1 outputs the busy signal B
Only when USY is at the “H” level, display data is written to the display SRAM 3.

[0004]

Conventionally, a display SRAM has been proposed.
When writing the display data to No. 3, writing can be performed only while the busy signal BUSY is at "H". This time is L
Since the time is very short compared to the data transfer time to the CD unit 5, for example, when the screen displayed on the LCD unit 3 is rewritten all at once, the display data to be rewritten is transferred to the display SRAM 3. It has a drawback that it cannot be transmitted quickly and is not suitable for a device using a large-screen display. It is also possible to prioritize data writing to the display SRAM 3 over data transfer from the display SRAM 3, but in this case, writing a large amount of data to the display SRAM 3 causes a drawback such as flickering of the display. there were.

[0005]

In order to solve such a problem, the present invention comprises an LCD and a display memory,
Writes the display data displayed on the LCD to the display memory
On the other hand, the written display data is transferred via the FIFO unit.
The LCD controller to be transferred to the LCD, those with Viewing detection result access conflict detector for rewriting the display data stored in the FIFO unit to a predetermined value the write request of the display data to the display memory while transferring data It is.

[0006]

With the provision of the FIFO section, the transfer of display data is performed in a burst manner, and the transfer time is shortened. As a result, it is possible to give a margin to the time for allocating the display data to the display memory. Also,
If there is a display data write request during display data transfer, the display data stored in the FIFO unit is rewritten to a predetermined value, and writing of the display data to the display memory is allowed.

[0007]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of an apparatus to which an LCD control system according to the present invention is applied. In the figure,
4 are denoted by the same reference numerals and the description thereof will be omitted. In FIG. 1, reference numeral 10 denotes a register selection / setting unit for selecting each register unit to be described later and inputting various setting values to the selected register unit;
A display start address portion for setting a start address of display data to be displayed on the D unit 5, a duty number register portion 12 for setting a duty number (the number of lines; the number of vertical lines), and a reference numeral 13 for a horizontal character number (the number of characters per line) ) Is set, a horizontal character number register section 14 is a duty number counter,
Reference numeral 15 denotes a horizontal character number counter, 16 denotes a comparison unit that compares the set value of the duty number register unit 12 with the value of the duty number counter 14, and 17 compares the set value of the horizontal character number register unit 13 with the value of the horizontal character number counter 15. This is a comparison unit. Reference numeral 18 denotes an address multiplex unit for switching addresses; 19, a display address counter for generating a display address; 20, a timing generation unit for generating various timings; 21, a display data input circuit;
Reference numeral 22 denotes a FIFO unit provided in the display data input circuit 21 for fetching one line of display data to the LCD unit 5 and performing first-in first-out of the fetched data.
Is a display data output circuit.

That is, the CPU 1 has the LCD unit 5
Prior to the upward display, first, the display start address is set via the register selection setting unit 10 to the display start address unit 1.
It is set to 1 and stored in the display address counter 19 and sent to the address multiplex unit 18. Further, the number of lines (the number of lines) to be displayed is set in the duty number register section 12, and the number of characters corresponding to one line (the number of lines) is set in the horizontal character number register section 13. After performing these various settings, the CPU 1 sets the display SRAM 3
Starts writing display data to. That is, the display S
An address bus AD for selecting an address of the RAM 3
Is transmitted to the address multiplexing unit 18, where the address is switched to select the address of the display SRAM 3, and when the display data D is subsequently transmitted via the data bus DB,
The data is written to the above address of the display SRAM 3 via a path (not shown).

In this manner, the display data is sequentially displayed on the display SRA.
M4, and when this reaches one line, the value of the horizontal character number counter 15 becomes the same as the value set in the horizontal character number register unit 13, so that the comparison unit 17 outputs a coincidence signal a. Timing generator 20
A busy signal BUSY is output from the
The display data writing operation of No. 1 is stopped.

Simultaneously with the output of the busy signal BUSY, the display data input circuit 21 captures one line of 8-bit display data from the display SRAM 3 into a FIFO unit 22 provided therein, and outputs the captured data to a display data output. The LCD 23 outputs the busy signal BUSY to the display SRAM 3 when the data is transmitted to the LCD unit 5 as 4-bit data. If there is write data, the CPU 1 writes the corresponding one-line data into the display SRAM 3.

Thus, the display data input circuit 21
The display data in the display SRAM 3 is sequentially transferred one line at a time to the LCD unit 5 for display. When the transfer of the display data for a predetermined number of lines is completed, the data of the first one line is displayed. To transfer from.

FIG. 2 is a diagram showing timings of writing and transferring display data. That is, CPU1
When there is display data to be written to the display SRAM 3, the data is written one line at a time while the busy signal BUSY is not output (while the busy signal BUSY is at the "H" level). When the data for one line is written and the busy signal BUSY goes to the "L" level as shown in FIG.
This is a waiting state even if an attempt is made to write data into the memory, and as a result, the writing is prohibited.

When the writing operation of the CPU 1 into the display SRAM 3 is prohibited, the address of the display SRAM 3 is selected at the rising edge of the high-speed clock signal CP3 [FIG. 2D], the data D from the SRAM 3 is taken into the FIFO unit 22 in the display data input circuit 21 at the fall of the clock signal CP3 [FIG. 2E]. Then, at the next rising of the clock signal CP3, the display S
The next address of the RAM 3 is selected and the FI
The data taken into the FO unit 22 is transferred to the LCD unit 5 by the display output circuit 23 [FIG. 2 (f)].
In this way, the display data is transferred one by one to the LCD unit 5, and when one line of data is transferred, the busy signal BUSY is set to the "H" level, and the display SR
Permit access to AM3.

The speed of the clock signal CP3 in this embodiment is a high-speed clock of about 150 ns, and data is transferred using this clock. In contrast, in the prior art, a low-speed clock signal CP1 of about 560 ns is used. Since the data transfer is performed for a time corresponding to two clocks of the low-speed clock signal CP1, the data transfer time is about ８ of the conventional data transfer time. As a result, 320 × 240
A large LCD dot (if the sum of the data transfer time for one line and the data writing time is about 54Myuesu) if that displays at 77H _Z, as shown in FIG. 2 (g), of one line The transfer time of the display data is reduced to about 8 μs, and the remaining time is reduced to about 48 μs for the SRAM 3 of the CPU 1.
Can be allocated to the data write time for one line, and sufficient data can be written during this time.

As described above, the FIFO unit 22 capable of storing one line of display data is provided in the display data input circuit 21 so that one line of data transferred from the display SRAM 3 to the LCD unit 5 can be burst-processed. In this case, there is a margin in the access time of the CPU 1 to the display SRAM 3, and as a result, the present invention is sufficiently applicable to a case where a large amount of display data is rewritten at a time in a large LCD.

FIG. 3 is a block diagram showing another embodiment of the present invention. In the figure, an access conflict detection unit 24 is provided in the block diagram of FIG. 1 so that the display SRA of the CPU 1 can be used during data transfer from the display SRAM 4 to the LCD unit 5.
This enables writing to M3.

That is, the display data input circuit 21 is connected to the display S
One line of data in the RAM 3 is stored in the internal FIFO unit 2
2, the busy signal BUSY is at "L" level. When the CPU 1 writes display data to the display SRAM 3 in spite of such a state, the CPU 1 sends a write request signal b to the access conflict detection unit 24 and then writes the display data to the display SRAM 3. On the other hand, in the access contention detection unit 24 to which the write request signal b is input, the reset signal c or the set signal c is obtained from the write request signal b and the busy signal BUSY.
To the display data input circuit 21 to cause the display data transferred from the display SRAM 3 to the FIFO unit 22 to be rewritten to “00” or “FF” while the CPU 1 is writing the display data to the display SRAM 3. .

As a result, "00" or "F" partially set due to contention in the display data for one line.
The "F" data is transferred to the LCD unit 5, and that portion is momentarily displayed as a "blank" or "black line". However, since the normal display data can be transferred in the next cycle, it can be recovered immediately. it can. During the conflict, the display data from the CPU 1 to the display SRAM 3 is of course normally written. As described above, since the data set due to the access conflict in the display data for one line is very small, the C data is not transferred during the transfer of the display data.
Even when the PU 1 writes the display data, the display screen does not flicker.

[0019]

As described above, the present invention relates to a FIFO which stores display data for the unit number of lines stored in the display memory when the display data is transferred from the display memory to the LCD.
Since the O portion is provided, the transfer of the display data is performed in a burst manner, and the transfer time is shortened. As a result, the time for allocating data to the display memory of the CPU increases, so that a large amount of display data can be written at once, and the present invention can be sufficiently applied to an apparatus using a large-screen display. Also,
If there is a display data write request during the transfer of display data, the display data stored in the FIFO unit is rewritten to a predetermined value, and the writing of the display data to the display memory is permitted. The display data can be rewritten without causing flicker.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an apparatus to which an LCD control system according to the present invention is applied.

FIG. 2 is a timing chart of the above device.

FIG. 3 is a block diagram showing another embodiment of the present invention.

FIG. 4 is a block diagram of a conventional LCD control device.

FIG. 5 is a timing chart of a conventional LCD control device.

[Explanation of symbols]

 Reference Signs List 1 CPU 3 Display SRAM 5 LCD unit 20 Timing generation unit 21 Display data input circuit 22 FIFO unit 23 Display output circuit 24 Access conflict detection unit a Match signal b Write request signal c Reset signal D, DD data signal BUSY busy signal CP1 CP3 clock signal LP line transfer pulse signal FP frame pulse signal

Claims (1)

(57) [Claims] An LCD and a display memory;
The display data to be displayed on the CD is written into the display memory, and the written display data is written through the FIFO unit.
In LCD controller to be transferred to the LCD Te, displayed for the display memory in the display data transfer
When a data write request is detected, the data is stored in the FIFO unit.
Access competition to rewrite stored display data to a predetermined value
And a display unit for writing display data to the display memory.
LCD control method being characterized in that to enable write.