JP2827430B2 - Manufacturing method of multilayer printed wiring board - Google Patents

Manufacturing method of multilayer printed wiring board

Info

Publication number
JP2827430B2
JP2827430B2 JP2087933A JP8793390A JP2827430B2 JP 2827430 B2 JP2827430 B2 JP 2827430B2 JP 2087933 A JP2087933 A JP 2087933A JP 8793390 A JP8793390 A JP 8793390A JP 2827430 B2 JP2827430 B2 JP 2827430B2
Authority
JP
Japan
Prior art keywords
wiring pattern
printed wiring
multilayer printed
wiring board
bumps
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2087933A
Other languages
Japanese (ja)
Other versions
JPH03285388A (en
Inventor
徹 山本
勝秀 塚本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2087933A priority Critical patent/JP2827430B2/en
Publication of JPH03285388A publication Critical patent/JPH03285388A/en
Application granted granted Critical
Publication of JP2827430B2 publication Critical patent/JP2827430B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Description

【発明の詳細な説明】 産業上の利用分野 本発明はポータブルテープレコーダやビデオカメラ等
の小型電子機器の多層プリント配線板の製造方法に関す
るものである。
Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer printed wiring board of a small electronic device such as a portable tape recorder and a video camera.

従来の技術 近年、電子機器の小型化、高密度実績化に伴いプリン
ト配線板の薄膜化、高密度化が要請され、回路基板を何
枚も積層した多層プリント配線板が実用化されている。
2. Description of the Related Art In recent years, as electronic devices have been downsized and have achieved high densities, thinning and high densification of printed wiring boards have been demanded, and multilayer printed wiring boards in which a number of circuit boards are stacked have been put to practical use.

従来、これらの多層プリント配線板は銅張基板にエッ
チング等の方法で配線パターンを形成した複数枚の回路
基板を適当な厚さの絶縁材料(プリプレグ)を介して上
下の位置合わせを行いながら加熱、加圧して接着、積層
してまず多層板を作製し、次に各層の電気的接続は上か
ら下まで貫通したスルーホールを開け、この内壁にメッ
キ等で導電体層を形成し上下層の短絡を行っていた。
Conventionally, these multilayer printed wiring boards have been heated while performing vertical alignment of a plurality of circuit boards, each having a wiring pattern formed on a copper-clad board by an etching method or the like, through an insulating material (prepreg) having an appropriate thickness. First, a multilayer board is manufactured by pressing and bonding and laminating, then the electrical connection of each layer is made by opening through holes penetrating from top to bottom, forming a conductor layer on this inner wall by plating etc. Short circuit was occurring.

これ以外に各層間での任意の位置での短絡法として
は、ガラス・エポキシ等の樹脂基板の場合は一部で第8
図に示す構造のものが使用されている。第1層として基
板81に配線パターン82を形成した後、第2層として必要
箇所に穴83をあけた基板84(もしくは穴開けしたプリプ
レグ)を第1層と位置合わせした後接合し、次に全体を
メッキして第2層表面、穴の底面(第1層の導体層上)
および穴の側面に導体層85を形成する。この後、第2層
のメッキ部をエッチング技術で必要部分のみ残し配線パ
ターンを形成する。以下同様にして多層化を行い、多層
プリント配線板を作製する。
In addition to this, as a short-circuiting method at an arbitrary position between the respective layers, in the case of a resin substrate such as
The structure shown in the figure is used. After forming a wiring pattern 82 on a substrate 81 as a first layer, a substrate 84 (or a prepreg with a hole) having a hole 83 formed at a required position as a second layer is aligned with the first layer and then joined, and then bonded. Plating the whole surface of the second layer, the bottom of the hole (on the first conductive layer)
Then, a conductor layer 85 is formed on the side surface of the hole. Thereafter, a wiring pattern is formed by leaving only a necessary portion of the plated portion of the second layer by an etching technique. Hereinafter, multilayering is performed in the same manner to produce a multilayer printed wiring board.

一方、基板としてアルミナ等のセラミックを用いたも
のの場合は、第9図に示すようにセラミックのグリーン
シート91上に銅酸化物等のレジネートで配線パターン92
を形成する。この上に第2層として第1層との短絡箇所
にベアホールを有し、このベアホール中に吸引しながら
スクリーン印刷を行い、レジネートを埋め込み、さらに
もう一度通常のスクリーン印刷を行い、配線パターン93
を形成したグリーンシート94を積層する。この様にベア
ホールにレジネートが充填されたグリーンシートを必要
枚数だけ正確に位置合わせを行い、積層する。最後にこ
の積層シートを加圧しながら焼成し、レジネートを還元
して金属導体化する。例えば、日経ニューマティリアル
1989年11月20日号p85記事参照。
On the other hand, in the case of using a ceramic such as alumina as a substrate, as shown in FIG. 9, a wiring pattern 92 is formed on a ceramic green sheet 91 by resinate such as copper oxide.
To form On top of this, a bare hole is formed as a second layer at a short-circuit point with the first layer, screen printing is performed while sucking into the bare hole, a resinate is embedded, and normal screen printing is performed again to obtain a wiring pattern 93.
The green sheet 94 formed with is formed. In this way, the required number of green sheets, in which bare holes are filled with resinate, are accurately positioned and stacked. Finally, the laminated sheet is baked while applying pressure to reduce the resinate to form a metal conductor. For example, Nikkei New Material
See p85 article, November 20, 1989.

発明が解決しようとする課題 しかしながら、第1の従来法では各層のプリント配線
板を積層するには、ガラス布にエポキシ樹脂等を半硬化
状態で含浸させたプリプレグを各層間に介在させるた
め、基板の厚みがどうしても厚くなり、プリント配線板
の薄膜化を阻害していた。
SUMMARY OF THE INVENTION However, in the first conventional method, in order to laminate printed wiring boards of respective layers, a prepreg obtained by impregnating glass cloth with an epoxy resin or the like in a semi-cured state is interposed between the respective layers. Was inevitably thick, which hindered the thinning of the printed wiring board.

さらに上下の層を任意の位置で短絡させるスルホール
(ベアホール)の作製が不可能であり、このため回路設
計が複雑となり、積層数も増加し、コスト高となる欠点
を有していた。
Furthermore, it is impossible to form a through hole (bare hole) for short-circuiting the upper and lower layers at arbitrary positions, which complicates the circuit design, increases the number of stacked layers, and has the disadvantage of increasing the cost.

第2の従来法では、任意の位置でのベアホールの作製
は可能であるが、その工程が非常に複雑でコスト高とな
る。さらにベアホールの周辺(内壁)のみにメッキがさ
れ、断線の危険性も高い。
According to the second conventional method, a bare hole can be formed at an arbitrary position, but the process is very complicated and costly. Furthermore, plating is performed only on the periphery (inner wall) of the bare hole, and there is a high risk of disconnection.

セラミックグリーンシートを用いた第3の従来法で
は、工程もかなり簡素化されベアホール部での接続状態
も良いが、材料費が高価であり、基板の重量も重くなる
欠点を持つ。
In the third conventional method using ceramic green sheets, the process is considerably simplified and the connection state at the bare hole is good, but it has the disadvantage that the material cost is high and the weight of the substrate is heavy.

本発明は上記課題に鑑み、工程が簡単でコストが安く
任意の位置にベアホールを形成でき、電気的接合性にも
優れた軽量の多層プリント配線板の製造方法を提供する
ものである。
The present invention has been made in view of the above problems, and provides a method for manufacturing a lightweight multi-layer printed wiring board that has a simple process, is inexpensive, can form a bare hole at an arbitrary position, and has excellent electrical bonding properties.

課題を解決するための手段 本発明は、ベアホールによる上下層の電気的接合法と
は異なり、直接ワイヤ線で上下層を接続するもので、ワ
イヤ線の形成方法として第1層(下層)上にワイヤーボ
ンドによりバンプを上下層の接続必要箇所に作製する。
Means for Solving the Problems The present invention is different from the electrical bonding method of the upper and lower layers by a bare hole, in which the upper and lower layers are directly connected by a wire, and the wire is formed on the first layer (lower layer). Bumps are formed by wire bonding in the upper and lower layers where connection is required.

次に、この上にポリイミド等の熱硬化性樹脂をロール
コーティング法や噴霧法や浸漬法でバンプの高さより薄
く塗布、硬化させて絶縁層を形成する。この熱硬化性樹
脂が光硬化性であれば硬化が短時間ですみより効率的で
ある。
Next, a thermosetting resin such as polyimide is applied thereon and thinned by a roll coating method, a spraying method, or a dipping method to a thickness smaller than the height of the bump to form an insulating layer. If the thermosetting resin is photo-curable, curing can be performed in a short time, and the process is more efficient.

次に、絶縁層上に突出したバンプの頭部をカッター等
で切断し、金属面を露出させる。この上に第2層の配線
パターンを形成して上下層の電気的接続を行う。以下同
様にして多層化を行なう多層プリント配線板の製造方法
を提供するものである。
Next, the head of the bump protruding on the insulating layer is cut with a cutter or the like to expose the metal surface. A second-layer wiring pattern is formed thereon, and the upper and lower layers are electrically connected. Hereinafter, the present invention provides a method of manufacturing a multilayer printed wiring board for performing multilayering in the same manner.

作用 絶縁層がキャスティング法によって形成されるため膜
厚が薄くでき多層プリント配線板自体の厚さも薄くする
ことができる。また、工程も容易で材料費も安く製造コ
ストを大幅に低下できる利点もある。さらに上下層間の
電気的接続も従来のスルホールタイプのものと比べ導通
断面積が大きく安定している。
Since the insulating layer is formed by the casting method, the thickness can be reduced, and the thickness of the multilayer printed wiring board itself can be reduced. In addition, there is an advantage that the process is easy, the material cost is low, and the manufacturing cost can be greatly reduced. Further, the electrical connection between the upper and lower layers is large and stable as compared with the conventional through-hole type.

実施例 以下に本発明の第1の一実施例について、図面を参照
しながら説明する。第1図は本発明の第1の実施例にお
ける配線パターン形成後の概観図、第2図はバンプ形成
工程の概観図、第3図は熱硬化性樹脂の塗布工程の概観
図、第4図はバンプの突出部の切断工程の概観図、第5
図は完成した多層プリント配線板の断面図である。ここ
で11はポリイミドフィルム、12は金ペースト、21はワイ
ヤーボンディング装置、22は金線、23はバンプ、31は光
硬化性ポリイミド樹脂、32は噴霧器、33は紫外線ラン
プ、41はバンプ、42はポリイミド絶縁層、43はカッタ
ー、51はポリイミド絶縁層、52は配線パターン、53はバ
ンプ、54はチップ部品である。
Embodiment A first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic diagram of a first embodiment of the present invention after a wiring pattern is formed, FIG. 2 is a schematic diagram of a bump forming process, FIG. 3 is a schematic diagram of a thermosetting resin coating process, and FIG. Is a schematic view of a process of cutting the protruding portion of the bump, and FIG.
The figure is a sectional view of the completed multilayer printed wiring board. Here, 11 is a polyimide film, 12 is a gold paste, 21 is a wire bonding device, 22 is a gold wire, 23 is a bump, 31 is a photocurable polyimide resin, 32 is a sprayer, 33 is an ultraviolet lamp, 41 is a bump, 42 is A polyimide insulating layer, 43 is a cutter, 51 is a polyimide insulating layer, 52 is a wiring pattern, 53 is a bump, and 54 is a chip component.

ポリイミドフィルム11(東レ・デュポン社製カプト
ン、膜厚25μm)上に金ペースト12をスクリーン印刷法
で塗布し、配線パターンを形成した。
A gold paste 12 was applied on a polyimide film 11 (Kapton, manufactured by Du Pont-Toray Co., Ltd., film thickness: 25 μm) by a screen printing method to form a wiring pattern.

次に、この形成された配線パターン上において上層
(第2層)との接合(短絡)部にワイヤ・ボンディング
装置21を用い、線径20μmの金線22を先端部に電気放電
によって金ボールを形成させ、これを超音波で第1層配
線パターンの必要箇所に接合し、その後ワイヤ部を直ち
にヘアピン状に湾曲させて切断し、頭部(スタッド)に
尻尾の付いた形状のバンプ23を形成した。このバンプ径
の大きさは約60μm、高さは約50μmであった。バンプ
形状としては、このようなスタッドバンプ形状に限定さ
れないがスタッドがある方が下地との接着性に優れ、接
触抵抗も小さくなる利点がある。
Next, a gold ball 22 having a wire diameter of 20 μm was applied to the tip of the gold ball by electric discharge using a wire bonding apparatus 21 at the junction (short circuit) with the upper layer (second layer) on the formed wiring pattern. This is joined to the required portion of the first layer wiring pattern by ultrasonic waves, and then the wire portion is immediately bent into a hairpin shape and cut to form a bump 23 having a tail on a head (stud). did. The size of the bump diameter was about 60 μm, and the height was about 50 μm. The bump shape is not limited to such a stud bump shape, but the presence of a stud has advantages that the adhesion to the base is excellent and the contact resistance is small.

次に、この上に光硬化性ポリイミド樹脂31を噴霧器32
からイエロールーム内で噴霧、配線パターンを全面的に
バンプの高さより薄くコーティングする。この後、紫外
線ランプ33によって、樹脂上に紫外線を照射しポリイミ
ド樹脂を完全硬化させ、絶縁層(膜厚約35μm)を形成
する。しかし、この状態ではポリイミド樹脂上に突出し
たバンプの上にも樹脂が存在し、絶縁状態である そこでカッター43によってポリイミド絶縁層42から突
出しているバンプ41を切断し、バンプの金を露出させ
る。
Next, a photocurable polyimide resin 31 was sprayed on the
Spray in the yellow room, and coat the entire wiring pattern thinner than the bump height. Thereafter, ultraviolet rays are irradiated onto the resin by an ultraviolet lamp 33 to completely cure the polyimide resin, thereby forming an insulating layer (thickness: about 35 μm). However, in this state, the resin also exists on the bumps protruding on the polyimide resin, and the resin is in an insulating state. Therefore, the bumps 41 protruding from the polyimide insulating layer 42 are cut by the cutter 43 to expose the gold of the bumps.

次に、このポリイミド絶縁層51および切断されたバン
プ53の上に再び金ペーストをスクリーン印刷することで
配線パターンを形成した。以下同様の工程を繰り返して
多層化を行い、最後の表面部分に抵抗、コイル、コンデ
ンサおよび半導体等のチップ部品54、54′、54″を実装
して多層プリント配線板を完成した。
Next, a wiring pattern was formed on the polyimide insulating layer 51 and the cut bumps 53 by screen printing a gold paste again. Thereafter, the same steps were repeated to form a multilayer, and chip components such as a resistor, a coil, a capacitor, and a semiconductor were mounted on the last surface portion to complete a multilayer printed wiring board.

配線材料として金ペーストが使用できるのは今のとこ
ろ比抵抗の大きさからデジタル回路に限定されるが、作
製工程が容易で製造コストが大幅に下げることができ
る。
At present, the use of gold paste as a wiring material is limited to digital circuits because of its high specific resistance, but the manufacturing process is easy and the manufacturing cost can be significantly reduced.

以上のようにして作製した多層プリント配線板は、絶
縁層の厚みが約35μmで金ペーストからなる配線パター
ンの段差(約15μm)を抑えることができ、より複数の
多層化が可能となった。さらに基板がポリイミドフィル
ムであるため可とう性があり、湾曲したところへの基板
の配置も可能である。また、多層プリント配線板の製造
コストも大幅に低下した。
In the multilayer printed wiring board manufactured as described above, the thickness of the insulating layer was about 35 μm, the level difference (about 15 μm) of the wiring pattern made of gold paste could be suppressed, and a plurality of multilayers became possible. Furthermore, since the substrate is a polyimide film, the substrate has flexibility, and the substrate can be arranged at a curved place. Also, the manufacturing cost of the multilayer printed wiring board has been significantly reduced.

以下に本発明の第2の実施例について図面を参照しな
がら説明する。第6図は熱硬化性樹脂の塗布工程の概観
図である。61はポリイミドフィルム、62はニッケル配線
パターン、63はロール、64はベルトコンベア、65は光硬
化性エポキシアクリレート樹脂、66は紫外線ランプ、67
はバンプである。
Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. FIG. 6 is a schematic view of a step of applying a thermosetting resin. 61 is a polyimide film, 62 is a nickel wiring pattern, 63 is a roll, 64 is a belt conveyor, 65 is a photocurable epoxy acrylate resin, 66 is an ultraviolet lamp, 67
Is a bump.

ポリイミドフィルム61の上を塩化第一錫溶液で処理し
て感度付与を行った後、塩化パラジウム溶液を塗布し、
これをよく水洗いしてから硫酸ニッケルとホウ酸からな
るカセイアルカリ性溶液に浸した。90℃1時間で約15μ
mの膜厚となった。次にこの上に配線パターンをレジス
トインクで印刷し、エッチング液中に浸漬して不要部分
を溶かし、配線パターンを形成する。その後、配線パタ
ーン上のレジストインクを除去し、パターン上の必要箇
所に第1の実施例と同様の方法でバンプを形成した。
After treating the top of the polyimide film 61 with a stannous chloride solution to give sensitivity, a palladium chloride solution is applied,
This was thoroughly washed with water and then immersed in a caustic alkaline solution consisting of nickel sulfate and boric acid. About 15μ at 90 ° C for 1 hour
m. Next, a wiring pattern is printed thereon with resist ink, and immersed in an etching solution to dissolve unnecessary portions, thereby forming a wiring pattern. After that, the resist ink on the wiring pattern was removed, and bumps were formed at necessary positions on the pattern in the same manner as in the first embodiment.

次に、第6図に示すようにポリイミドフィルム61上に
ニッケル配線パターン62およびバンプ67が形成された基
板をベルトコンベア64の上に乗せ、少し柔らかいゴム等
からなるロール63の下を通し、光硬化性エポキシアクリ
レート樹脂65を基板全面に塗布し、その後紫外線ランプ
66の元を通し樹脂を硬化させた。その後、カッターで突
出したバンプの先端部を切断し、再びメッキ、配線パタ
ーン印刷、エッチング、レジスト除去の各工程を経て第
2層目の配線パターンを形成する。以下、同様の工程で
多層化を行った。
Next, as shown in FIG. 6, a substrate having a nickel wiring pattern 62 and bumps 67 formed on a polyimide film 61 is placed on a belt conveyor 64 and passed under a roll 63 made of slightly soft rubber or the like. Apply curable epoxy acrylate resin 65 over the entire surface of the substrate, and then use an ultraviolet lamp
The resin was hardened through the base of 66. After that, the tip of the protruding bump is cut by a cutter, and the second layer wiring pattern is formed through the steps of plating, wiring pattern printing, etching, and resist removal again. Hereinafter, multilayering was performed in the same process.

光硬化性エポキシアクリレートをロールコーティング
することによって塗布材料の使用量が最小限に抑えられ
る利点がある。但し、表面性は噴霧法に比べかなり劣
る。一方、配線材料をメッキ法で作製することによって
配線パターンの製造コストは上がるが、配線抵抗を大き
く下げれるメリットがある。
Roll coating of the photocurable epoxy acrylate has the advantage of minimizing the amount of coating material used. However, the surface properties are considerably inferior to the spray method. On the other hand, by manufacturing the wiring material by plating, the manufacturing cost of the wiring pattern increases, but there is an advantage that the wiring resistance can be greatly reduced.

以下に本発明の第3の実施例について図面を参照しな
がら説明する。第7図は熱硬化性樹脂の塗布工程の概観
図である。71はアルミナ基板、72はニッケル配線パター
ン、73はバンプ、74は保護フィルム、75は熱硬化性フェ
ノール樹脂、76は熱風炉である。
Hereinafter, a third embodiment of the present invention will be described with reference to the drawings. FIG. 7 is a schematic view of a step of applying a thermosetting resin. 71 is an alumina substrate, 72 is a nickel wiring pattern, 73 is a bump, 74 is a protective film, 75 is a thermosetting phenol resin, and 76 is a hot blast stove.

アルミナ基板71上に第2の実施例と同様にメッキ法で
配線パターン72を形成した。この際基板の裏側に保護フ
ィルム74を張っておく。次に第1の実施例と同様の方法
で必要箇所にバンプ73を形成した後、基板全体を熱硬化
性フェノール樹脂75に浸漬し、熱風炉76で樹脂を硬化さ
せた。バンプの先端切断工程以下は第1の実施例と同様
に行い、多層プリント配線板を作製し、最後に保護フィ
ルムを除去して完成した。
A wiring pattern 72 was formed on an alumina substrate 71 by plating in the same manner as in the second embodiment. At this time, a protective film 74 is provided on the back side of the substrate. Next, after forming bumps 73 at necessary places in the same manner as in the first embodiment, the entire substrate was immersed in a thermosetting phenol resin 75, and the resin was cured in a hot air oven 76. The steps following the step of cutting the tip of the bump were performed in the same manner as in the first embodiment, a multilayer printed wiring board was manufactured, and finally the protective film was removed to complete the process.

浸漬法による保護膜形成は基板の裏面にも樹脂がつく
ため若干のコスト高となる反面、表面性に優れた緻密な
保護膜が得られる利点を有する。
Forming the protective film by the immersion method slightly increases the cost because the resin is also attached to the back surface of the substrate, but has the advantage that a dense protective film having excellent surface properties can be obtained.

上記3つの実施例の多層プリント配線板と従来のガラ
ス・エポキシ基板にベアホールを形成したタイプの多層
プリント配線板を85℃85%RHの条件で加速し、抵抗値の
変化を調べたところ、本実施例においては2000時間後に
おいても抵抗の変化はほとんど認められかなったが、従
来品では1.6倍程度抵抗が増加した。
When the multilayer printed wiring board of the above three embodiments and the conventional multilayer printed wiring board in which bare holes were formed in a glass / epoxy board were accelerated under the conditions of 85 ° C. and 85% RH, the change in resistance value was examined. In the example, almost no change in the resistance was observed even after 2000 hours, but the resistance was increased by about 1.6 times in the conventional product.

以上のように本実施例によれば上下層の電気的接続を
バンプによって行なうため、工数を大幅に削減できコス
トダウンがはかれる。また、接続抵抗も少なく信頼性の
面でも優れている。さらにポリイミド等の熱硬化性樹脂
をキャスティングで絶縁層を形成するため、絶縁層が薄
くでき、軽量で柔軟性を有する多層プリント配線板が可
能となる。
As described above, according to the present embodiment, since the upper and lower layers are electrically connected by the bumps, the number of steps can be significantly reduced and the cost can be reduced. Also, the connection resistance is small and the reliability is excellent. Further, since the insulating layer is formed by casting a thermosetting resin such as polyimide, the insulating layer can be made thin, and a lightweight and flexible multilayer printed wiring board can be obtained.

発明の効果 以上のように本発明は、上下層の電気的接触をベアホ
ールによって行なうのではなくワイヤーボンディングに
よりバンプを形成して行なうため、工数を大幅に削減で
きコストダウンがはかれる。また、接続抵抗もベアホー
ルの場合のように内壁部のみで接合しているのではな
く、バンプ全体に電流が流れるため少なくなる。寿命等
の信頼性の面でも優れている。さらにポリイミド等の熱
硬化性樹脂のキャスティングで絶縁層を形成するため、
絶縁層が薄くでき、セラミック多層基板に比べ軽量で柔
軟性を有する多層プリント配線板が可能となる。
Effect of the Invention As described above, in the present invention, the electrical contact between the upper and lower layers is performed by forming bumps by wire bonding instead of using bare holes, so that the number of steps can be greatly reduced and cost can be reduced. Also, the connection resistance is reduced because the current flows through the entire bumps instead of being joined only by the inner wall portions as in the case of the bare hole. Excellent in reliability such as life. Furthermore, in order to form an insulating layer by casting of a thermosetting resin such as polyimide,
An insulating layer can be made thin, and a multilayer printed wiring board which is lighter and more flexible than a ceramic multilayer substrate can be obtained.

以上のように本発明は製造工程が少なく低コストで作
製可能な、かつ接続抵抗が小さく信頼性にも優れた軽量
で薄型の多層プリント配線板の製造方法を提供するもの
である。
As described above, the present invention provides a method of manufacturing a lightweight and thin multilayer printed wiring board which can be manufactured at low cost with a small number of manufacturing steps, has low connection resistance, and is excellent in reliability.

【図面の簡単な説明】[Brief description of the drawings]

第1図は本実施例における配線パターン形成後の概観
図、第2図は本実施例におけるバンプ形成工程の概観
図、第3図は熱硬化性樹脂の塗布工程の概観図、第4図
はバンプの突出部の切断工程の概観図、第5図は完成し
た多層プリント配線板の断面図、第6図は熱硬化性樹脂
の塗布工程の概観図、第7図は熱硬化性樹脂の塗布工程
の概観図、第8図は従来のガラス・エポキシ等の多層樹
脂基板の概観図、第9図は従来のセラミック多層基板の
概観図である。 11……ポリイミドフィルム、12……金ペースト、21……
ワイヤーボンディング装置、22……金線、23……バン
プ、31,31′……光硬化性ポリイミド樹脂、32……噴霧
器、33……紫外線ランプ、41……バンプ、42……ポリイ
ミド絶縁層、43……カッター、51……ポリイミド絶縁
層、52……配線パターン、53……バンプ、54,54′,54″
……チップ部品、61……ポリイミドフィルム、62……ニ
ッケル配線パターン、63……ロール、64……ベルトコン
ベア、65……光硬化性エポキシアクリレート樹脂、66…
…紫外線ランプ、67……バンプ、71……アルミナ基板、
72……ニッケル配線パターン、73……バンプ、74……保
護フィルム、75……熱硬化フェノール樹脂、76……熱風
炉。
FIG. 1 is a schematic view after forming a wiring pattern in this embodiment, FIG. 2 is a schematic view of a bump forming step in this embodiment, FIG. 3 is a schematic view of a thermosetting resin application step, and FIG. FIG. 5 is a cross-sectional view of a completed multilayer printed wiring board, FIG. 6 is a schematic view of a thermosetting resin coating process, and FIG. 7 is a thermosetting resin coating process. FIG. 8 is a schematic view of a conventional multilayer resin substrate made of glass, epoxy or the like, and FIG. 9 is a schematic view of a conventional ceramic multilayer substrate. 11: Polyimide film, 12: Gold paste, 21:
Wire bonding equipment, 22: Gold wire, 23: Bump, 31, 31 '... Photo-curable polyimide resin, 32: Sprayer, 33: UV lamp, 41: Bump, 42: Polyimide insulating layer, 43 ... cutter, 51 ... polyimide insulating layer, 52 ... wiring pattern, 53 ... bump, 54, 54 ', 54 "
…… Chip parts, 61 …… Polyimide film, 62 …… Nickel wiring pattern, 63 …… Roll, 64 …… Belt conveyor, 65 …… Photocurable epoxy acrylate resin, 66…
… UV lamp, 67… Bump, 71… Alumina substrate,
72: Nickel wiring pattern, 73: Bump, 74: Protective film, 75: Thermosetting phenol resin, 76: Hot air stove.

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】樹脂製フィルムもしくはセラミック板に配
線パターンを形成した後、上部配線パターンとの短絡部
にワイヤーボンドによりバンプを形成する工程と、 熱硬化性樹脂層を前記配線パターン上にロールコーティ
ングで前記バンプより薄い厚さで形成し、十分硬化させ
た後、突出しているバンプの先端部を切断して前記先端
部を露出させる工程と、 硬化した熱硬化性樹脂および露出したバンプの先端部の
上に、2層目の配線パターンを形成する工程と、 前記した同様の工程を繰り返して多層化を行なうことを
特徴とする多層プリント配線板の製造方法。
1. A step of forming a wiring pattern on a resin film or a ceramic plate and then forming a bump by wire bonding at a short-circuit portion with the upper wiring pattern, and roll coating a thermosetting resin layer on the wiring pattern. Forming a thinner than the bumps and curing the bumps sufficiently, and then cutting off the tips of the protruding bumps to expose the tips; and the cured thermosetting resin and the tips of the exposed bumps. Forming a second-layer wiring pattern thereon, and repeating the same steps as described above to perform multi-layering.
【請求項2】熱硬化性樹脂層をロールコーティングに代
えて噴霧法によって形成することを特徴とする請求項1
記載の多層プリント配線板の製造方法。
2. The method according to claim 1, wherein the thermosetting resin layer is formed by spraying instead of roll coating.
A method for producing the multilayer printed wiring board according to the above.
【請求項3】熱硬化性樹脂層をロールコーティングに代
えて浸漬法によって形成することを特徴とする請求項1
記載の多層プリント配線板の製造方法。
3. The method according to claim 1, wherein the thermosetting resin layer is formed by a dipping method instead of roll coating.
A method for producing the multilayer printed wiring board according to the above.
JP2087933A 1990-04-02 1990-04-02 Manufacturing method of multilayer printed wiring board Expired - Fee Related JP2827430B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2087933A JP2827430B2 (en) 1990-04-02 1990-04-02 Manufacturing method of multilayer printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2087933A JP2827430B2 (en) 1990-04-02 1990-04-02 Manufacturing method of multilayer printed wiring board

Publications (2)

Publication Number Publication Date
JPH03285388A JPH03285388A (en) 1991-12-16
JP2827430B2 true JP2827430B2 (en) 1998-11-25

Family

ID=13928710

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2087933A Expired - Fee Related JP2827430B2 (en) 1990-04-02 1990-04-02 Manufacturing method of multilayer printed wiring board

Country Status (1)

Country Link
JP (1) JP2827430B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5591941A (en) * 1993-10-28 1997-01-07 International Business Machines Corporation Solder ball interconnected assembly
JP5092621B2 (en) * 2007-08-20 2012-12-05 大日本印刷株式会社 Wiring board and manufacturing method thereof
CN103198885B (en) * 2013-03-30 2014-12-17 深圳欧菲光科技股份有限公司 Conducting film, manufacturing method thereof and touch screen comprising same

Also Published As

Publication number Publication date
JPH03285388A (en) 1991-12-16

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