JP2817404B2 - Method for manufacturing charge transfer device - Google Patents
Method for manufacturing charge transfer deviceInfo
- Publication number
- JP2817404B2 JP2817404B2 JP3000647A JP64791A JP2817404B2 JP 2817404 B2 JP2817404 B2 JP 2817404B2 JP 3000647 A JP3000647 A JP 3000647A JP 64791 A JP64791 A JP 64791A JP 2817404 B2 JP2817404 B2 JP 2817404B2
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- gate
- oxide film
- charge transfer
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Description
【0001】[0001]
【産業上の利用分野】本発明は高融点金属あるいはその
シリサイドをゲート電極とする電荷転送素子の製造方法
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a charge transfer device using a refractory metal or a silicide thereof as a gate electrode.
【0002】[0002]
【従来の技術】従来の電荷転送素子としては、図2
(b)に示すように電荷転送効率を上げるため第1ゲー
ト電極8と第2ゲート電極9がオーバーラップした構造
を持ちゲート電極にはSiプロセスとの整合性を考えポ
リシリコンが用いられているものと、図3に示すように
単層ゲート構造を持ちゲート電極10a、bには高融点
金属が用いられているものがある。製造工程としては、
前者はまず図2(a)に示すようにSi基板1表面を酸
化して第1ゲート酸化膜2を形成し、その上に第1ゲー
ト電極8形成後リフレッシュし第2ゲート酸化を行い、
第1ゲート電極8と重なるように第2ゲート電極9を形
成して図2(b)に示す構造とする。後者はエッチング
により第1ゲート電極10a、第2ゲート電極10bを
同時に形成する。2. Description of the Related Art As a conventional charge transfer device, FIG.
As shown in (b), the first gate electrode 8 and the second gate electrode 9 have a structure in which the first gate electrode 8 and the second gate electrode 9 overlap to increase the charge transfer efficiency, and polysilicon is used for the gate electrode in consideration of compatibility with the Si process. Some have a single-layer gate structure as shown in FIG. 3, and gate electrodes 10a and 10b are made of a high melting point metal. As a manufacturing process,
In the former, first, as shown in FIG. 2A, the surface of the Si substrate 1 is oxidized to form a first gate oxide film 2, on which a first gate electrode 8 is formed and then refreshed to perform a second gate oxidation.
The second gate electrode 9 is formed so as to overlap with the first gate electrode 8 to obtain a structure shown in FIG. In the latter, the first gate electrode 10a and the second gate electrode 10b are simultaneously formed by etching.
【0003】[0003]
【発明が解決しようとする課題】図2の構造の場合、ポ
リシリコンの配線抵抗の大きさが原因となり高速転送時
に駆動パルスの波形がなまる等の問題が生じる。このこ
とは現在多画素化が進みポリシリコンの配線の長くなっ
ている固体撮像素子に電荷転送素子を用いた場合特に顕
著な問題となる。In the case of the structure shown in FIG. 2, problems such as the waveform of a driving pulse becoming round at the time of high-speed transfer occur due to the large wiring resistance of polysilicon. This is a particularly significant problem when a charge transfer device is used in a solid-state imaging device in which the number of pixels has been increased and the polysilicon wiring is long.
【0004】また、図3の構造の場合隣接するゲート電
極間にギャップが生じるため、電荷転送時その部分のポ
テンシャルにディップが生じ電荷転送効率の劣化を招
く。In the case of the structure shown in FIG. 3, a gap is formed between adjacent gate electrodes, so that a potential dip occurs in a portion at the time of charge transfer, resulting in deterioration of charge transfer efficiency.
【0005】しかし、図2(a)、(b)で説明したよ
うな従来のプロセスを用いてオーバーラップ構造を持つ
高融点金属またはそのシリサイドをゲート電極とする電
荷転送素子を作成した場合、第2ゲート酸化膜形成時、
高融点金属またはそのシリサイドは酸化されやすいた
め、第1ゲート電極が酸化され粉状になりゲートとして
機能しないという問題が生じる。However, when a charge transfer device having a gate electrode made of a refractory metal having an overlapping structure or a silicide thereof is formed by using the conventional process described with reference to FIGS. When forming a two-gate oxide film,
Since the high melting point metal or its silicide is easily oxidized, the first gate electrode is oxidized and becomes powdery, and does not function as a gate.
【0006】本発明は、第2ゲート酸化膜の膜質を低下
させることなく、かつ第2ゲート酸化膜形成時第1ゲー
ト電極の酸化を抑制し、オーバーラップ構造を持ち高融
点金属またはそのシリサイドをゲート電極とする電荷転
送素子を作成することを目的とする。The present invention suppresses the oxidation of the first gate electrode at the time of forming the second gate oxide film without deteriorating the film quality of the second gate oxide film. An object is to create a charge transfer element serving as a gate electrode.
【0007】[0007]
【課題を解決するための手段】第1ゲート電極上部と側
壁を低温で形成された絶縁膜により覆った後、第2ゲー
ト酸化膜を形成し、その後第2ゲート電極を一部、第1
ゲート電極にオーバーラップさせて形成することにより
上記問題を解決している。After the upper portion and the side wall of the first gate electrode are covered with an insulating film formed at a low temperature, a second gate oxide film is formed, and then the second gate electrode is partially covered with the first gate electrode.
The above problem is solved by overlapping the gate electrode.
【0008】[0008]
【作用】本発明では第1ゲート電極を高温処理する前に
低温で形成された絶縁膜で覆い第1ゲート電極が酸化さ
れることを抑制している。According to the present invention, the first gate electrode is covered with an insulating film formed at a low temperature before the high-temperature treatment, thereby preventing the first gate electrode from being oxidized.
【0009】[0009]
【実施例】図1(d)は本発明に係わる電荷転送素子の
構造の一実施例を説明するための断面図である。ゲート
電極3、7は抵抗低減のためタングステンから成り、第
1ゲート電極3は第2ゲート酸化膜6形成時に酸化され
ないよう450℃で形成されたCVD酸化膜4、5bで
覆われている。また、第2ゲート電極7は転送効率を上
げるためその一部が酸化膜を介して第1ゲート電極3に
オーバーラップしている。FIG. 1D is a sectional view for explaining an embodiment of the structure of the charge transfer device according to the present invention. The gate electrodes 3 and 7 are made of tungsten for resistance reduction, and the first gate electrode 3 is covered with CVD oxide films 4 and 5b formed at 450 ° C. so as not to be oxidized when the second gate oxide film 6 is formed. A part of the second gate electrode 7 overlaps the first gate electrode 3 via an oxide film in order to increase transfer efficiency.
【0010】ここで、かかる構成の電荷転送素子を作製
する場合について具体的に説明する。まずSi基板1の
表面に熱酸化で第1ゲート酸化膜2を厚さ700A形成
し、その後第1ゲート膜(タングステン)を厚さ200
0A、次いでCVD酸化膜(形成温度450℃)を厚さ
2000Aを形成しゲート形状3、4にエッチングする
(図1(a))。さらにCVD酸化膜5a(形成温度4
50℃)を厚さ2000A全面に形成した(図1
(b))後エッチバックしサイドウォール5bを形成す
る(図1(c))。その後第2ゲート酸化膜6(HT
O、形成温度850℃)を厚さ700A形成し第2ゲー
ト電極7(タングステン)を一部、第1ゲート電極3
(タングステン)にオーバーラップさせて厚さ2000
A形成する。なお、上記タングステンの代わりに他の高
融点金属(Mo、Ti等)またはそのシリサイド(WS
i等)を用いた場合、またCVD酸化膜の代わりに他の
低温で形成可能な絶縁膜(プラズマ窒化膜、形成温度3
00℃等)を用いた場合がある。Here, the case of manufacturing a charge transfer device having such a configuration will be specifically described. First, a first gate oxide film 2 having a thickness of 700A is formed on the surface of a Si substrate 1 by thermal oxidation, and then the first gate film (tungsten) is formed to a thickness of 200A.
0A, then a CVD oxide film (forming temperature 450 ° C.) is formed to a thickness of 2000 A and etched into gate shapes 3 and 4 (FIG. 1A). Further, the CVD oxide film 5a (forming temperature 4
50 ° C.) was formed over the entire surface of a 2000A thickness (FIG. 1).
(B)) After the etching back, the side wall 5b is formed (FIG. 1 (c)). Thereafter, the second gate oxide film 6 (HT
O, a forming temperature of 850 ° C.), a thickness of 700 A, a part of the second gate electrode 7 (tungsten), and a first gate electrode 3
(Tungsten) overlapped to a thickness of 2000
A is formed. Instead of the above tungsten, another high melting point metal (Mo, Ti, etc.) or its silicide (WS
i) or another insulating film (plasma nitride film, forming temperature 3) which can be formed at a low temperature instead of the CVD oxide film.
00 ° C.).
【0011】[0011]
【発明の効果】本発明によれば配線抵抗が小さく、かつ
転送効率の良い電荷転送素子を形成することができる。According to the present invention, it is possible to form a charge transfer element having low wiring resistance and high transfer efficiency.
【0012】また、第2ゲート酸化膜形成時、第2ゲー
ト酸化膜の膜質を低下させることなく高融点金属または
そのシリサイドからなる第1ゲート電極の酸化を抑制す
ることができる。Further, when the second gate oxide film is formed, the oxidation of the first gate electrode made of a refractory metal or a silicide thereof can be suppressed without deteriorating the film quality of the second gate oxide film.
【0013】また、本発明の方法を用い、第1ゲート電
極上部及び側壁を低温形成の絶縁膜で覆った時点でイオ
ン注入することにより注入イオンがCVD酸化膜でスト
ップされるので、高融点金属またはそのシリサイドはイ
オン注入時チャネリングを起こすという欠点が抑えら
れ、第2ゲート電極下部にセルフアラインでイオン注入
することができる。In addition, by using the method of the present invention, ion implantation is performed when the upper portion and the side wall of the first gate electrode are covered with an insulating film formed at a low temperature, so that the implanted ions are stopped by the CVD oxide film. Alternatively, the disadvantage that the silicide causes channeling at the time of ion implantation can be suppressed, and ions can be implanted below the second gate electrode by self-alignment.
【図1】本発明の一実施例の工程を示す断面図。FIG. 1 is a cross-sectional view showing a process in one embodiment of the present invention.
【図2】従来例を示す断面図。FIG. 2 is a sectional view showing a conventional example.
【図3】従来例を示す断面図。FIG. 3 is a sectional view showing a conventional example.
1 基板 2 第1ゲート酸化膜(熱酸化膜) 3 第1ゲート電極(タングステン) 4 5a、5b、CVD酸化膜 6 第2ゲート酸化膜(HTO) 7 第2ゲート電極(タングステン) 8 第1ゲート電極(ポリシリコン) 9 第2ゲート電極(ポリシリコン) 10 ゲート電極(高融点金属またはシリサイド) DESCRIPTION OF SYMBOLS 1 Substrate 2 1st gate oxide film (thermal oxide film) 3 1st gate electrode (tungsten) 4 5a, 5b, CVD oxide film 6 2nd gate oxide film (HTO) 7 2nd gate electrode (tungsten) 8 1st gate Electrode (polysilicon) 9 Second gate electrode (polysilicon) 10 Gate electrode (high melting point metal or silicide)
Claims (1)
金属またはそのシリサイドから成る膜を形成し、その上
層に絶縁膜を450℃以下の低温で形成する工程と、前
記高融点金属またはそのシリサイドから成る膜とその上
層の絶縁膜をゲート形状にパターニングする工程と、全
面に絶縁膜を450℃以下の低温で形成しエッチバック
することによりゲート電極側壁にサイドウォールを形成
する工程と、第2ゲート酸化膜を形成する工程と、第2
ゲート酸化膜上に高融点金属またはそのシリサイドから
成る第2ゲート電極を第1ゲート電極にオーバーラップ
させて形成する工程とを有することを特徴とする電荷転
送素子の製造方法。A step of forming a film made of a refractory metal or a silicide thereof on a substrate having an oxide film formed on a surface thereof, and forming an insulating film thereon at a low temperature of 450 ° C. or less ; Or a step of patterning a film made of the silicide and an insulating film thereover into a gate shape, and a step of forming an insulating film over the entire surface at a low temperature of 450 ° C. or less and etching back to form a sidewall on a gate electrode side wall. Forming a second gate oxide film;
Forming a second gate electrode made of a refractory metal or a silicide thereof on the gate oxide film so as to overlap the first gate electrode.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3000647A JP2817404B2 (en) | 1991-01-08 | 1991-01-08 | Method for manufacturing charge transfer device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3000647A JP2817404B2 (en) | 1991-01-08 | 1991-01-08 | Method for manufacturing charge transfer device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH04279036A JPH04279036A (en) | 1992-10-05 |
JP2817404B2 true JP2817404B2 (en) | 1998-10-30 |
Family
ID=11479500
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3000647A Expired - Lifetime JP2817404B2 (en) | 1991-01-08 | 1991-01-08 | Method for manufacturing charge transfer device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2817404B2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3649396B2 (en) | 2002-02-01 | 2005-05-18 | 松下電器産業株式会社 | Method for manufacturing charge coupled device |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS547864A (en) * | 1977-06-21 | 1979-01-20 | Toshiba Corp | Manufacture for semiconductor device |
JPS5660033A (en) * | 1979-10-22 | 1981-05-23 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Manufacture of semiconductor device |
JPS5947470B2 (en) * | 1981-06-09 | 1984-11-19 | 三洋電機株式会社 | Method of manufacturing a charge coupled device |
JPH03248538A (en) * | 1990-02-27 | 1991-11-06 | Oki Electric Ind Co Ltd | Charge-coupled element and manufacture thereof |
-
1991
- 1991-01-08 JP JP3000647A patent/JP2817404B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH04279036A (en) | 1992-10-05 |
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