JP2810655B2 - Substrates for electronic components - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate for electronic parts such as a package and a substrate having a multilayer structure in which a circuit pattern is formed on an upper surface of an insulating layer or between insulating layers. 2. Description of the Related Art Conventionally, there have been bases for electronic parts such as packages and substrates formed by forming a circuit pattern on a ceramic insulator. [0003] This electronic component base is generally formed by laminating a plurality of insulating layers made of ceramic, and has a multilayer structure. A circuit pattern is formed on the upper surface of the insulating layer or between the insulating layers of the electronic component base. Conventionally, when a capacitor is provided on the electronic component substrate, the capacitor is conventionally provided in a planar layer form exclusively along the upper surface of the insulating layer constituting the electronic component substrate or along the lateral direction between the insulating layers. I have. The conventional capacitor has a structure in which a ferroelectric layer is interposed and a conductor layer is widely provided on upper and lower surfaces of the ferroelectric layer. Is provided in the form of a layer in the lateral direction between the upper surface of the insulating layer or between the insulating layers constituting the electronic component substrate, the capacitor occupies an extremely large area along the upper surface of the insulating layer of the electronic component substrate or the horizontal direction between the insulating layers. Would. As a result, the capacitor hinders the degree of freedom in the arrangement of circuit patterns formed along the upper surface of the insulating layer of the same electronic component base or along the horizontal direction between the insulating layers.
The arrangement of the circuit patterns formed on the electronic component base is complicated and difficult, and the arrangement density of the circuit patterns formed on the upper surface of the insulating layer or between the insulating layers of the electronic component base is reduced. SUMMARY OF THE INVENTION The present invention has been made to solve such a problem. A capacitor is provided on a substrate for an electronic component having a circuit pattern formed on the upper surface of an insulating layer or between insulating layers.
To provide a circuit area without occupying a large area along the upper surface of the insulating layer or the horizontal direction between the insulating layers in a layered manner, and using a conventional general-purpose manufacturing apparatus and manufacturing technology to easily prepare the circuit without any trouble. It is an object of the present invention to provide an electronic component base that can be used. [0008] In order to achieve the above object, an electronic component substrate of the present invention comprises an electronic component such as a package or a substrate having a circuit pattern formed on the upper surface of an insulating layer or between insulating layers. In the base body, while providing a large-diameter via hole filled with a ferroelectric formed using a ferroelectric forming material in the vertical direction of the insulating layer portion immediately below the circuit pattern,
A large-diameter via hole filled with the ferroelectric material is provided with a small-diameter via hole filled with a conductor formed using a metallizing paste at an axial portion thereof, and an insulating layer adjacent to the left and right of the large-diameter via hole. A conductor formed using a metallized paste, and a via hole filled with a conductor connected to the circuit pattern is provided in the vertical direction of the insulating layer portion immediately below the circuit pattern. The circuit pattern portion located immediately above the via hole is removed, and the upper surface of the ferroelectric material filled in the large-diameter via hole is exposed on the surface of the circuit pattern. Is characterized in that a capacitor is provided three-dimensionally in the insulating layer portion. In this electronic component substrate, the insulating layer portion immediately below the circuit pattern is effectively used, and the insulating layer portion is filled with a ferroelectric material filled in a large-diameter via hole and the ferroelectric material. Using a conductor filled in the small-diameter via hole provided at the axial center of the large-diameter via hole and a conductor filled in each via hole adjacent to the left and right of the large-diameter via hole, the capacitor is vertically elongated in three dimensions. In preparation. Therefore, a capacitor formed using the ferroelectric substance and the conductor is an upper surface of an insulating layer or an insulating layer suitable for forming a circuit pattern, and the upper surface of the insulating layer other than where the circuit pattern is formed. Alternatively, it is possible to prevent a large area in the lateral direction between the insulating layers from being occupied. And
Another circuit pattern can be easily and freely formed on the upper surface of the insulating layer or between the insulating layers other than where the circuit pattern is formed, without being hindered by a capacitor formed using a ferroelectric substance and a conductor. In addition, the arrangement of the circuit patterns formed on the electronic component base can be facilitated and the density of the circuit patterns can be increased. In addition, the ferroelectric material forming the capacitor is formed by firing a ferroelectric material, and the conductor forming the capacitor is formed by firing a metallizing paste. A capacitor formed by combining a body and a conductor can be easily and quickly formed on a substrate for an electronic component by using a general-purpose manufacturing apparatus and manufacturing method without any trouble. 1 to 3 show a preferred embodiment of a ceramic package for a base for electronic parts according to the present invention. FIG. 1 is a partial front sectional view, and FIG. A-A
FIG. 3 is a cross-sectional view of FIG. Hereinafter, this package will be described. In the package shown in the figure, alumina 60 Wt
%, Three low-temperature firing green sheets 5a, 5b, 5 in the form of a rectangular frame containing 40% by weight of borosilicate glass.
c are sequentially stacked to form a package forming member. A cavity 4 for housing a semiconductor element is formed inside the package forming member. On the upper surface of the intermediate green sheet 5b of the package forming member, between the upper green sheet 5c and the intermediate green sheet 5b, a metallized paste line such as Au or Ag-Pd for low-temperature firing for forming the circuit pattern 14 is formed. 6 is provided. On the upper surface of the upper green sheet 5c and on the lower surface of the lower green sheet 5a, a metallized paste layer 6 of Au or Ag-Pd for low-temperature firing for forming the metallized layer 9 is provided. The portion of the intermediate green sheet 5b immediately below the metallized paste line 6 for forming the circuit pattern 14 between the upper green sheet 5c and the intermediate green sheet 5b is as shown in FIGS. The green sheet 5b is vertically penetrated to provide a large-diameter via hole 8a.
b Filled with a ferroelectric material 20 such as a composite perovskite type. The axial portion of the large-diameter via hole 8a filled with the ferroelectric material 20 is vertically penetrated through the axial portion of the large-diameter via hole 8a filled with the ferroelectric material 20 to reduce the diameter. Via hole 8b is provided. The via hole 8b is concentrically filled with a metallizing paste 7 such as Au or Ag-Pd for low-temperature firing for forming a conductor. In the lower layer green sheet 5a immediately below the small-diameter via hole 8b, the green sheet 5a is vertically penetrated to provide the small-diameter via hole 8b in the axial center of the ferroelectric material 20. It is provided so as to communicate with the via hole 8b. Then, in the via hole 8b,
A metallizing paste 7 such as Au or Ag-Pd for low-temperature firing for forming a conductor is filled. The upper and lower ends of the metallized paste 7 are connected to the metallized paste 7 filled in the via hole 8b provided in the axial center of the ferroelectric material 20 and the metallized paste layer 6 on the lower surface of the lower green sheet 5a. The portion of the intermediate green sheet 5b adjacent to the left and right of the large-diameter via hole 8a and directly below the metallized paste line 6 for forming a circuit pattern is provided with the green sheet 5b. Via holes 8 are provided to penetrate vertically. Then, the via holes 8 are filled with metallizing pastes 7 such as Au or Ag-Pd for low-temperature firing for forming conductors, and the upper ends of the metallizing pastes 7 are filled with metallizing pastes for forming circuit patterns 14. Each is connected to the track 6. As shown in FIG. 2, the portion of the metallized paste line 6 for forming the circuit pattern 14 located immediately above the large-diameter via hole 8 filled with the ferroelectric material 20 is, as shown in FIG.
Removed in a circular shape. And large diameter via hole 8
The upper surface of the ferroelectric material 20 filled in a is exposed on the surface of the metallized paste line 6 for forming the circuit pattern 14. Next, the three green sheets 5a, 5a
The ceramic package forming member formed by laminating b and 5c is placed in a furnace or the like and integrally fired at a low temperature of about 1000 ° C. to form a ceramic package 1c formed by laminating three insulating layers made of ceramic. ing. At the same time, a circuit pattern 14 is formed on the upper surface of the intermediate insulating layer, a metallized layer 9 is formed on the upper surface of the upper insulating layer, a metallized layer 9 is formed on the lower surface of the lower insulating layer, A large-diameter via hole 8a filled with the ferroelectric substance 22 is provided in the intermediate insulating layer portion, or a large-diameter via hole 8a filled with the ferroelectric substance 22 is provided.
A small-diameter via hole 8b filled with a conductor 23 connected to the metallized layer 9 on the lower surface of the lower insulating layer is provided at the axial center portion of a, or an intermediate insulating layer portion immediately below the circuit pattern 14 adjacent to the left and right of the large-diameter via hole 8a. Are provided with via holes 8 each filled with a conductor 23 connected to the circuit pattern 14. And those large diameter via holes 8
a near the left and right sides of the conductor 23 and the large-diameter via hole 8a, which are filled in the small-diameter via hole 8b provided at the axial center of the large-diameter via hole 8a filled with the ferroelectric substance 22, A capacitor 24 for electrically connecting the circuit pattern 14 and the metallized layer 9 constituting the ground on the lower surface of the lower insulating layer by using the conductor 23 filled in each via hole 8 is connected to the intermediate insulating layer portion of the ceramic package 1c. 3D in the thickness direction. Thereafter, the bottom plate 10 is brazed to the metallized layer 9 formed on the lower surface of the ceramic package 1c. The bottom surface of the cavity 4 of the ceramic package 1c is closed by the bottom plate 10. At the same time, a stage 11 is brazed to the surface of the bottom plate 10 exposed in the cavity 4. The ceramic package 1c shown in FIGS. 1 to 3 is configured as described above. Next, an example of use of the ceramic package 1c and its operation will be described. As shown in FIG. 1, a semiconductor element 12 is mounted on a stage 11 in a cavity 4. Then, the electrode 13 of the semiconductor element and the inner end of the circuit pattern 14 are electrically connected by a wire 16. Next, the upper surface of the cavity 4 is
And the cap 17 is brazed to the metallized layer 9 on the upper surface of the upper insulating layer. Then, the semiconductor element 12 is sealed in the cavity 4. The inner end of the lead 18 is connected to the outer end of the circuit pattern 14 by soldering or the like, and the lead 18 extends outside the ceramic package 1c. Then, when a power supply current or an electric signal flows through the lead 18, the current or the signal is transmitted to the electrode 13 of the semiconductor element through the circuit pattern 14 and the wire 16. Then, the semiconductor element 12 operates with the current or the signal. At this time, high-frequency noise mixed in the power supply current flowing into the electrode 13 of the semiconductor element through the circuit pattern 14 causes the circuit pattern 14 and the metallized layer 9 constituting the ground on the lower surface of the lower insulating layer to be electrically connected. (A bypass capacitor) 24 connected in parallel, and the bottom plate 1 forming a ground through the capacitor 24 formed using the ferroelectric 22 and the conductor 23 described above.
Runs to zero and is rejected. Then, the transmission of the high frequency noise to the electrode 13 of the semiconductor element is prevented. Here, in the capacitor 24 provided in the ceramic package 1c shown in FIG. 1, the circuit pattern 14 of the ceramic package 1c and the bottom plate 10 constituting the ground joined to the metallization layer 9 are electrically connected in parallel. FIG. 4 shows an equivalent circuit diagram of the connected capacitor 24. In the ceramic package 1c shown in FIGS. 1 to 3, a capacitor 24 for a bypass capacitor, a ferroelectric substance 22 filled in a large-diameter via hole 8a, and a large Small diameter via hole 8b provided at the axial center of diameter via hole 8a
A capacitor 24 formed using the conductor 23 filled in the via hole 8a and the conductor 23 filled in each via hole 8 adjacent to the left and right of the large-diameter via hole 8a is solidified in the thickness direction of the intermediate insulating layer portion immediately below the circuit pattern 14. Are prepared. Therefore, the capacitor 24 formed by using the ferroelectric 22 and the conductor 23 described above is effectively used by utilizing the intermediate insulating layer portion immediately below the circuit pattern 14 without disturbing the circuit pattern 14 on the upper surface of the intermediate insulating layer. It can be easily and accurately provided three-dimensionally with a margin. At the same time, another circuit pattern is formed on the upper surface of the intermediate insulating layer other than where the circuit pattern 14 is formed or between the upper insulating layer and the intermediate insulating layer by using a capacitor 24 formed by using the ferroelectric substance 22 and the conductor 23. It can be easily and freely formed at a high density without being disturbed. Also, three green sheets 5a, 5b,
5c is formed by laminating a ceramic package forming member
A ceramic package 1 which is placed in a furnace or the like and integrally fired at a low temperature of about 1000 ° C., and three insulating layers are laminated.
c at the same time as forming the ceramic package 1c
The circuit pattern 14 is formed on the upper surface of the intermediate insulating layer, the metallized layer 9 is formed on the upper surface of the upper insulating layer of the ceramic package 1c, the metallized layer 9 is formed on the lower surface of the lower insulating layer of the ceramic package 1c. A large-diameter via hole 8a filled with the ferroelectric substance 22 is provided in the intermediate insulating layer portion directly below the small-diameter 14 or a small-diameter via hole 8a filled with the ferroelectric substance 22 is filled with the conductor 23 in the axial center portion. A via hole 8b can be provided, or a via hole 8 filled with a conductor 23 can be provided in an intermediate insulating layer portion immediately below the circuit pattern 14 adjacent to the left and right of the large-diameter via hole 8a. The ferroelectric 22 filled in the large-diameter via hole 8a and the ferroelectric 22
The conductor 23 filled in the small-diameter via hole 8b provided in the axial center portion of the large-diameter via hole 8a filled with, and the intermediate insulating layer portion immediately below the circuit pattern 14 adjacent to the left and right of the large-diameter via hole 8a. By using the conductor 23 filled in each via hole 8 and the capacitor 24 in the thickness direction of the intermediate insulating layer portion of the ceramic package 1c, a conventional general-purpose manufacturing device and manufacturing technology can be used to easily and without trouble. It can be formed quickly and three-dimensionally. In the above-described ceramic package 1c, the green sheets 5a, 5b and 5c may be green sheets for normal high-temperature firing containing 92% by weight of alumina, or may be metallized paste lines 6, metallized paste layers 6 and 5. Approximately 1500 ° on metallizing paste 7
A metallized paste for high-temperature baking that does not melt or collapse even when a high temperature of C is applied may be used. The via holes 8a filled with the ferroelectric substance 22 and the via holes 8b and 8 filled with the conductor 23 are:
The cross-sectional shape may be not a circular shape but a polygonal shape such as a quadrangle, an elliptical shape, or the like. In the above-described ceramic package 1c, the large-diameter via hole 8a filled with the ferroelectric substance 22 and the insulating layer around the via hole 8 filled with the conductor 23 are used as the dielectric layer for forming the capacitor 24. Needless to say, it is partially used. The insulating layer for forming the electronic component base such as the package of the present invention may be a molded resin or other insulating layer. Then, via holes may be provided in the insulating layer in the vertical direction, and after filling the via holes with a metallizing paste or a ferroelectric material, the insulating layer may be exposed to a high temperature. Then, the metallized paste or the ferroelectric material may be dried, and a conductor or ferroelectric made of metallized may be integrally fixed and filled in the via hole provided in the insulating layer. Then, a capacitor made of a ferroelectric substance and a conductor may be provided vertically and three-dimensionally in the thickness direction of the insulating layer constituting the electronic component base. The present invention also relates to a substrate having a circuit pattern formed on the upper surface of the insulating layer or between the insulating layers, and a substrate for electronic components such as a package having a circuit pattern formed on the upper surface of the insulating layer and a substrate. Is also available. As described above, according to the electronic component base of the present invention, the thickness of the insulating layer portion can be effectively utilized by effectively utilizing the insulating layer portion immediately below the circuit pattern where a circuit pattern is not generally formed. In the vertical direction, a capacitor formed using a ferroelectric substance and a conductor can be easily and freely provided in a vertically long three-dimensional manner without being disturbed by a circuit pattern. A capacitor formed by using a ferroelectric substance and a conductor is provided on an upper surface or an insulating layer of an insulating layer suitable for forming a circuit pattern. A large area can be prevented from occupying a large area in a plane along the lateral direction between the insulating layers. Then, along the horizontal direction between the upper surface of the insulating layer and the insulating layer other than the portion where the circuit pattern is formed, another circuit pattern is formed at a high density without being disturbed by a capacitor formed using a ferroelectric substance and a conductor. It can be formed freely. In addition, the arrangement of the circuit patterns provided on the electronic component base can be liberalized, and the density and the integration of the circuit patterns can be increased. Further, the ferroelectrics forming the capacitors are formed by firing a ferroelectric material, and the conductors forming the capacitors are formed only by firing a metallizing paste. Capacitors combining dielectrics and conductors can be easily and quickly formed on electronic component bases using conventional general-purpose manufacturing equipment and manufacturing techniques, without using complicated and large-scale equipment, without the need for labor. .

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a partial front sectional view of a ceramic package of the present invention. FIG. 2 is a sectional view taken along line AA of FIG. FIG. 3 is a sectional view taken along line BB of FIG. 1; FIG. 4 is an equivalent circuit diagram of a capacitor provided in the ceramic package of FIG. 1; DESCRIPTION OF SYMBOLS 1 Electronic component base 1c Ceramic package 4 Cavities 5a, 5b, 5c Green sheet 6 Metallized paste line, metallized paste layer 7 Metallized paste 8a, 8b, 8 Via hole 9 Metallized layer 10 Bottom plate 11 Stage 12 Semiconductor element 14 Circuit pattern 16 Wire 17 Cap 18 Lead 20 Ferroelectric material 22 Ferroelectric material 23 Conductor 24 Capacitor

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-60-195964 (JP, A) JP-B-57-10577 (JP, B2) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 23/12 H01G 2 / 06,4 / 00 H05K 1/16

Claims (1)

(57) [Claims] In a substrate for an electronic component such as a package or a substrate in which a circuit pattern is formed on the upper surface of an insulating layer or between insulating layers, a ferroelectric substance is formed in a vertical direction of an insulating layer portion immediately below the circuit pattern.
Large-diameter window filled with a ferroelectric formed using a forming material
Large diameter with a hole and filled with ferroelectric
Use metallized paste for the center of the via hole
A small diameter via hole filled with a conductor formed by
And, wherein an insulating layer portion adjacent to the left and right of the via hole having a large diameter, on the insulating layer portion right under said circuit pattern
Downward, with a conductor formed using metallized paste
Via holes filled with conductors connected to the circuit pattern
And a circuit pattern portion located immediately above the large-diameter via hole is removed to expose the upper surface of the ferroelectric material filled in the large-diameter via hole to the circuit pattern surface. A substrate for an electronic component, wherein a capacitor is three-dimensionally provided in an insulating layer portion immediately below the circuit pattern using a dielectric and a conductor.