JP2796172B2 - Data interpolation device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] In particular, the present invention relates to a data interpolation device applied to error control of image data, audio data, and the like, with the object of improving data quality at the time of error occurrence exceeding the error detection capability. When the number of error bits in the data string is equal to or less than x bits, the error bits are corrected.
Error correction / detection means for outputting a detection signal indicating the presence of an error bit when the number of bits is less than or equal to bits, holding means for holding a data sequence passed through the error correction / detection means in chronological order; Generating means for generating interpolated data by using the interpolation data; and first selecting means for selecting interpolated data when a detection signal indicating the presence of an error bit is output, while normally selecting data one row before. A difference value detecting means for detecting a difference value with respect to the data of the immediately preceding column, and usually selecting an output of the first selecting means, and selecting interpolation data if the difference value exceeds a predetermined value.
Selecting means.

[Industrial applications]

The present invention relates to a data interpolation device, and more particularly to a data interpolation device applied to error control of image data, audio data, and the like.

In data transmission using the atmosphere as a route such as microwave communication and satellite broadcasting, the received C / N ratio may be reduced due to the influence of rainfall or the like. In order to ensure sufficient data quality even when the reception C / N ratio is reduced, it is necessary to correct errors in transmission codes.

For example, correction codes (SEC / DED or SEC / DED) included in A-mode and B-mode frames (1,350 bits / frame) of HDTV (high definition television) using satellite broadcasting
DEC / TED) is that SEC / EDE has 1-bit error correction capability and 2
DEC / TED has a two-bit error correction capability and a three-bit error detection capability, and is used in the enhanced mode.

In general, error control using an error correction code can perform error correction when each information symbol is dispersed into a code pattern other than a code word due to some error, and the dispersion area is isolated. Further, when the dispersion areas partially overlap, the error cannot be corrected but an error can be detected. FIG. 3 (a) is a conceptual diagram of error correction, and FIG. 3 (b)
Is a conceptual diagram of error detection. In these figures, a ₁ to
a ₃ and a ₁₁ ~a ₁₃ code word, b ₁ ~b ₃ and b ₁₁ ~b ₁₃ has regions dispersed by the error, C ₁ and C ₁₁ is a region of the entire sequence of length n.

That is, in the above-mentioned enhanced mode, when the transmission error is 2 bits or less, this can be corrected (error correction).
When there are more than 2 bits and not more than 3 bits, the presence of an error can be detected (error detection). When an error is detected, data interpolation processing for the purpose of improving data quality is often performed.

[Conventional technology]

FIG. 4 is a diagram showing a main part of a conventional data interpolation device.

The data sequence D _IN input in time order is sequentially stored in the first register 11, the second register 12, and the third register 13. That is, the current data string is output from the first register 11.
d _0, from the second register 12 one column before the data sequence d _1, from the third register 13 data string d ₂ of two rows before is taken out. d ₀
And d ₂ are input to the interpolation circuit 14, the output d _H of the interpolation processing circuit 14 together with d _1, it is input A of the selector 15, to the B terminal.

The interpolation processing circuit 14 generates interpolation data d _H with respect to the data d ₁ one column before the current data sequence, calculates a correlation between the current data sequence d ₀ and the data d ₂ two columns before, and calculates the correlation result. Let d _H. The selector 15 outputs A according to the state (1 or 0) of the error detection flag F to be input to the select terminal S, the one input of the B terminal as a data string D _OUT.

F = 0, the result of error correction and detection process for one column before the data d _1, indicates that that was not at least "error detection". In this case, the selector 15 selects the data d1 _one column before. F = 1 indicates that "error detection" has been performed as a result of the same error correction / detection processing. In this case, the selector 15 selects the interpolation data d _H.

Thus, instead of "error detection" has been one column before the data d _1, can output the interpolation data d _H of the d _1, can improve the data quality during error detection.

[Problems to be solved by the invention]

However, in such a conventional data interpolating device, the data d _{1 in the} immediately preceding column depends on the state of the error detection flag F.
And the interpolation data d _H are selected, so that if a bit error exceeding the error detection capability (up to 3 bits in the above-described enhanced mode) occurs, F = 0, that is, the same state as “no error detected” since made, one column before the data d ₁ there is a problem that would be selected that contains the bit errors.

The present invention has been made in view of such a problem, and has as its object to improve data quality at the time of occurrence of an error exceeding the error detection capability.

[Means for solving the problem]

In order to achieve the above object, the present invention corrects the error bits when the number of error bits in one data string is less than or equal to x bits as shown in FIG. Error correction / detection means for outputting a detection signal indicating the presence of an error bit when the number of bits exceeds y bits,
Holding means for holding the data sequence passed through the error correction / detection means in chronological order, generating means for generating interpolated data based on the data string held in the holding means, and usually selecting data one row before A first selection unit for selecting interpolation data when a detection signal indicating the presence of an error bit is output; a difference value detection unit for detecting a difference value between the interpolation data and data one column before; A second selecting unit for selecting the output of the first selecting unit and selecting the interpolation data when the difference value exceeds a predetermined value.

[Action]

In the present invention, a difference value between the interpolation data and the data of the immediately preceding column is constantly monitored, and when the difference value exceeds a predetermined value,
The interpolation data is forcibly output.

Here, the difference value represents the magnitude of the error variance of the data of the previous row. Therefore, when a multi-bit error that exceeds the error detection capability occurs, interpolation data with a small error variance can be used in place of the data of the previous column including the bit error, and the error data when the error exceeds the error detection capability can be used. Improve data quality.

〔Example〕

 Hereinafter, description will be made based on the drawings of the present invention.

FIG. 2 is a diagram showing an embodiment of a data interpolation device according to the present invention, and shows a MUSE (Multiple Sub Nyquist Sampl) of an HDTV.
This is an example in which the present invention is applied to a sound reproducing device.

The received MUSE signal is first subjected to a frame deinterleaving process 20 into 1,350-bit frames, followed by a bit deinterleaving process 21 in which the data bit order in the frame is rearranged to the original arrangement, and a predetermined bit length. Data strings are sequentially retrieved. Each data string is subjected to SEC / DED or error correction / detection circuit 22 (error correction / detection means).
Error correction control using a DEC / TED correction code is performed.
For example, in the enhancement mode, when the number of error bits in one data string is 2 bits or less (corresponding to x bits described in the summary of the invention), the error bit is corrected, and when the number of error bits exceeds 2 bits and 3 bits When it is less than or equal to y bits described in the gist of (1), the detection flag F (corresponding to the detection signal described in the gist of the invention) indicating the presence of the error bit is set (F = 1).

Each data string that has passed through the error correction / detection circuit 22 undergoes a 16-sample word deinterleave process 23, undergoes necessary processing in an interpolation processing unit 24 and a data selection unit 25, and finally has an audio reproduction unit 26 It is converted to output and output.

The interpolation processing unit 24 includes a first register 27 as a holding unit that sequentially captures and holds the data sequence input in chronological order,
Second register 28 and third register 29, interpolation processing circuit
30 (generating means) includes a current data string d ₀ from the first register 27 is retrieved, the data sequence d ₁ of the first column before the second register 28 is taken out, two columns before the third register 29 is a data sequence d ₂ is taken out. The interpolation processing circuit 30 calculates the correlation between the current data sequence d ₀ and the data sequence d ₂ two columns before, for example, by averaging the discrete distance of the code word, and calculates the correlation result as the data sequence one column before. the interpolation data d _H about d _1.

The data selection unit 25 includes a difference value comparator 31 (difference value detection means), an OR logic circuit 32, and a selector 33 (first and second selection means). ) According to the A terminal input (d ₁ ) or B
One of the terminal inputs (d _H ) is selected and output from the Y terminal. The difference value comparator 31 always outputs the A terminal input (d ₁ )
A difference value DF (DF = | A−B |) from the terminal input (d _H ) is monitored, and when the difference value DF exceeds a predetermined value Δx, the switching signal S is set to a set state (S = 1) and output. OR logic circuit 32
Indicates that the detection flag F from the error correction / detection circuit 22 is in a state (F = 1) indicating that an error bit is present, or the switching signal S from the difference value comparator 31 is (DF = | A−B |>). Δx)
(S = 1), the state of the select terminal S of the selector 33 is changed to 1 to force the terminal B input (d _H ) to be selected.

As described above, in this embodiment, when the number of bits exceeds x bits and y
When the following error bits bit if it occurs in the data d ₁ before one column and (F = 1), the difference value DF an error bit is generated in excess of y bits is increased to an extent exceeding the [Delta] x (S = any of 1), it is possible to select the interpolation data d _H in place of the first column before the data d _1. Therefore,
The selected data can be optimized, and the data quality at the time of error occurrence exceeding the error detection capability can be improved.

In this embodiment, an example of application to an HDTV has been described. However, the present invention is not limited to this. For example, digital communication in general, a laser disk, a compact disk, a video disk,
It can be applied to DAT, etc. In short, any data that handles data related to the preceding and following bits, for example, audio data and image data, and that performs error correction control may be used.

〔The invention's effect〕

According to the present invention, since the configuration is as described above, data selection at the time of occurrence of an error exceeding the error detection capability can be optimized, and data quality can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the principle of the present invention, FIG. 2 is a block diagram showing an embodiment of a data interpolation device according to the present invention, FIGS. 3 and 4 are diagrams showing a conventional example, and FIG. FIG. 4 is a diagram for explaining error correction and error detection. FIG. 4 is a configuration diagram of a main part of the data interpolation device. 22 error correction / detection circuit (error correction / detection means) 27 first register (holding means) 28 second register (holding means) 29 third register (holding means) 30 ... Interpolation processing circuit (generation means) 31... Difference value comparator (difference value detection means) 33... Selector (first and second selection means).

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-59-4345 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H04B 14/04 H04L 1/00

Claims (1)

(57) [Claims] An error correction / detection circuit for correcting an error bit when the number of error bits in one data string is x bits or less, and outputting a detection signal indicating the presence of an error bit when the number of error bits exceeds x bits and y bits or less. Means, holding means for holding the data string passed through the error correction / detection means in time order, generating means for generating interpolation data based on the data string held in the holding means, On the other hand, when a detection signal indicating that an error bit is present is output, first selection means for selecting interpolation data; difference value detection means for detecting a difference value between the interpolation data and data one column before; A data interpolation device comprising: a second selection unit that normally selects the output of the first selection unit, and selects interpolation data when the difference value exceeds a predetermined value.