JP2795716B2 - Printed wiring board - Google Patents

Description

Description: BACKGROUND OF THE INVENTION (a) Field of Industrial Application The present invention relates to a printed wiring board used for electronic equipment, and more specifically, to electromagnetic interference (EM).
The present invention relates to a printed wiring board on which the measure (I) has been taken.

(B) Conventional technology In recent years, the development of electronic devices has promoted the increase in the speed and density of circuits formed on printed wiring boards, but this has led to strict regulations on EMI. ing. A typical method among EMI measures conventionally considered is a method of reducing radiation noise and ingress noise by using a housing for housing a board as a shield case. However, this method has a problem that the electromagnetic wave energy confined in the shield case is radiated to the outside through a cable, and this method basically reduces the electromagnetic wave energy generated based on the high frequency characteristics of the circuit. Therefore, it is almost impossible to completely suppress radiation noise. So a new EMI
A printed wiring board for countermeasures has been proposed. This wiring board is formed on a substrate on which circuit patterns such as a signal line pattern (hereinafter simply referred to as a signal pattern), a ground line pattern (hereinafter simply referred to as a ground pattern), and a power supply line pattern (hereinafter simply referred to as a power pattern) are formed. An insulating layer is formed except at least a part of a ground pattern (hereinafter, this insulating layer is referred to as an undercoat layer), and a conductive layer is formed thereon so as to be connected to a non-insulated portion of the ground pattern. It is. Usually, an insulating layer (hereinafter, this insulating layer is referred to as an overcoat layer) is further formed on the conductive layer.

In the printed wiring board having such a configuration, radiation noise can be reduced mainly for four reasons.

First, the impedance of the ground pattern is reduced by the conductive layer.

Second is the removal of high frequency components from the signal pattern and the power supply pattern by the close conductive layer. That is, the undercoat layer is formed of a so-called solder resistor. Since the thickness of the undercoat layer is as thin as about 20 to 40 μm, a signal pattern and a power supply for the conductive layer formed thereon and connected to the ground pattern are formed. The distributed capacitance of the pattern increases. Therefore, unnecessary high-frequency components generated by ringing or the like are grounded at a high frequency to the ground pattern, thereby suppressing radiation noise.

Third, the impedance of the signal pattern and the power supply pattern is made uniform by the conductive layer. That is, the signal pattern and the power supply pattern are covered by the conductive layer.
The distance between these circuit patterns and the conductive layer connected to the ground pattern is made uniform, and the impedance of each circuit pattern is also made uniform. As a result, generation of an impedance mismatching part in high-frequency transmission and generation of unnecessary high-frequency components due to the generation are suppressed.

Yet another reason is the shielding effect of the conductive layer itself.

Efficient radiation noise by the above four reasons: low impedance of ground pattern by conductive layer, removal of high frequency component by close conductive layer, uniformity of impedance of circuit pattern, and normal shielding effect by conductive layer itself. Can be suppressed.

(C) Problems to be Solved by the Invention Generally, in a circuit board, a bypass capacitor (hereinafter referred to as a decap) for bypassing unnecessary high-frequency components between a ground pattern and a circuit pattern or between a power supply pattern and a ground pattern is appropriate. A number are attached. However, in the conventional printed circuit board, since this decap was mounted on the board by soldering as a discrete component, work for soldering them was necessary, and the size of the board was reduced by the presence of the decap. There was a problem that hinders conversion.

Further, there is a problem that the lead wire of the bypass capacitor acts as an inductance component with respect to a high frequency, and as a result, as will be described later, the frequency characteristic of the impedance deteriorates.

An object of the present invention is to provide a printed wiring board in which a conductive layer for shielding is laminated with an insulating layer interposed therebetween to form a bus capacitor at this portion.

(D) Means for Solving the Problems In the invention according to claim 1, a substrate, a circuit pattern including a ground line pattern and / or a power supply line pattern and a signal line pattern formed on the substrate, and the circuit pattern A first insulating layer formed so as to cover the circuit pattern except for at least a part of any one of the ground line pattern and the power supply line pattern, A first inductive layer formed on a layer so as to be connected to a non-insulated portion of the ground line pattern or the power line pattern, and a second insulating layer on the first conductive layer. A second conductive layer is laminated to form a capacitor between the first conductive layer and the second conductive layer, and the second conductive layer is connected to an arbitrary part of the circuit pattern. It is characterized by being connected to a part.

In the invention according to claim 2, a substrate, a circuit pattern including a ground line pattern and / or a power supply line pattern and a signal line pattern formed on the substrate, and a substrate on which the circuit pattern is formed,
A first insulating layer formed so as to cover the circuit pattern except for at least a part of any one of the ground line pattern and the power supply line pattern; and the ground line on the first insulating layer. A first conductive layer formed so as to be connected to a non-insulated portion of the pattern or the power supply line pattern; and a second insulating layer and a second conductive layer on the first conductive layer. A capacitor is formed between the first conductive layer and the second conductive layer by stacking, and the second conductive layer is connected to any part of the power supply line pattern or the ground line pattern.

(E) Function In the present invention, since the second insulating layer is interposed between the first conductive layer and the second conductive layer, a capacitor is formed by the first conductive layer and the second conductive layer. Is formed. Therefore, if the second conductive layer is connected to an arbitrary part of the circuit pattern, the capacitor can be used as a decap of the signal line, and if the first conductive layer is connected to the ground line pattern, the second capacitor can be used. By connecting the conductive layer to the power supply line pattern,
A bypass capacitor between the grounds can be configured. This decap is also formed when the first conductive layer is connected to the power supply line pattern and the second conductive layer is connected to the ground line pattern.

(F) Embodiment FIGS. 1A and 1B show a printed wiring board according to an embodiment of the present invention. First, a circuit pattern is formed on the surface of the substrate 1 made of an insulating material such as an epoxy resin, a phenol resin, a glass fiber, and a ceramic as shown in the figure. The circuit pattern is signal pattern 2 (20,2
1), a ground pattern 3 and a power supply pattern (not shown) are included. Each of these patterns is formed by a known photolithography technique. After the necessary patterns are formed, the first region A is left, except for a portion A of the ground pattern 3 and a portion B of the signal pattern 21.
Is formed. The undercoat layer 4 is a solder resist layer made of a resin insulating material.
The region A where the ground pattern 3 is exposed is desirably formed at a plurality of locations on the substrate.
It is good if there is a place. This undercoat layer 4 can be easily formed by screen printing. After the first undercoat layer 4 is formed, a first conductive layer 5 for shielding is applied thereon by screen printing. In this case, the first conductive layer 5 is formed on the region on the right side of the drawing, that is, on the upper surface of the first undercoat layer 4 so as not to cover the upper part of the circuit pattern 21. The reason why the first conductive layer 5 is formed so as not to cover the upper portion of the circuit pattern 21 as described later is that the first conductive layer 5 and the second conductive layer 7 which will be described later This is so as not to touch.

In the present embodiment, the first conductive layer 5 is made of copper paste, and for example, one having the following composition is used. That is, it is basically made by mixing copper fine particles as a filler, a binder for firmly bonding these fine particles to each other, and various additives for maintaining conductivity for a long period of time. Specifically, the following composition is preferable.

(Formulation Example 1) (A) 100 parts by weight of metallic copper powder, (B) 5 to 30 parts by weight of a resole type phenol resin, (C) 0.1 to 2 parts by weight of a dispersant, and 0.5 to 4 parts by weight of a chelating agent. And (D) 0.1 to 5 parts by weight of an adhesion improver, and (E) 0.5 to 7 parts by weight of a conductivity improver.

The metallic copper powder may be in any shape such as a flake, a dendrite, a sphere, and an irregular shape.

The resole type phenol resin is for binding metal copper powder and other components well, and effectively acts for maintaining long-term conductivity.

As the dispersant, fatty acids or metal salts of fatty acids are desirable. Preferred are saturated fatty acids such as palmitic acid, stearic acid and arachiic acid having 16 to 20 carbon atoms, and preferred unsaturated fatty acids are 16 to 18 carbon atoms such as somalic acid, oleic acid and linolenic acid. As the metal salt of a fatty acid, a salt of the above-mentioned fatty acid with a metal such as sodium, potassium, copper, zinc, and aluminum is preferable.

These dispersants promote fine dispersion of the copper metal powder in the resin mixture.

As the chelate forming agent, it is preferable to use at least one selected from aliphatic amines such as monoethanolamine, diethanolamine, triethanolamine, ethylenediamine, triethylenediamine, and triethylenetetramine. The chelating agent prevents oxidation of the metallic copper powder and contributes to maintaining conductivity.

 Various adhesives are included as the adhesion improver.

As the natural resin type, rosin (gum type, tall oil type, wood type), rosin dielectric, terpene resin type,
(Terpene type, terpene phenol type) and the like are preferable.
As the synthetic resin type, thermosetting type such as petroleum resin type, butyral resin type, phenol resin type, xylene resin type, etc., thermoplastic type such as vinyl acetate resin, acrylic resin, cellulose, phenoxy resin, etc. Rubber,
Synthetic rubbers such as styrene butadiene rubber, nitrile rubber, butyl rubber and the like are preferred. These are those having the property of lowering the internal stress of the resol type phenol resin as a binder, or those having a functional group (a carboxyl group, a hydroxyl group, a long-chain alkyl group, etc.) exhibiting adhesiveness.

As the conductivity improver, a compound composed of a nitrogen-containing compound or a heterocyclic compound having a phenyl group, particularly a compound capable of exhibiting conductivity by chemical oxidation polymerization or electrolytic polymerization is preferable.

In addition, this composition example is illustrated in detail in Japanese Patent Application No. 1-340782.

(Formulation Example 2) (A) 100 parts by weight of metallic copper powder and (B) melamine resin 35 to 5
Resin admixture consisting of 0% by weight, 20 to 35% by weight of polyester resin and 15 to 30% by weight of resol type phenol resin
10 to 25 parts by weight, (C) 0.1 to 2 parts by weight of dispersant,
(D) It is formed by mixing 0.5 to 4 parts by weight of a chelating agent.

Preferred specific examples of the metal copper powder, the dispersant, and the chelating agent in the above description and the functions thereof are the same as those in the above-mentioned formulation example 1.

The melamine resin in the resin mixture is an alkylated melamine resin and uses at least one selected from a methylated melamine or a butylated melamine resin.

The polyester resin in the resin admixture is a resin formed by polycondensation of a polyhydric alcohol and a polybasic acid,
An alkyd resin, a maleic acid resin, an unsaturated polyester resin and the like can be mentioned.

Resin admixture of melamine resin 35-50% by weight, polyester resin 20-35% by weight, resole phenolic resin 15-
By using 30% by weight, it is possible to obtain a conductive paint that binds metallic copper powder and other components well, maintains long-term conductivity, has good adhesion to copper foil, and has good soldering heat resistance. Can be

It should be noted that this composition example is described in detail in Japanese Patent Application No. 62-328095.

After the first conductive layer 5 is applied, the first conductive layer 5 is cured by heating, and a first overcoat layer 6 made of an insulating resin material is formed thereon so as to cover the first conductive layer 5. The first overcoat layer 6 and the undercoat layer 4 can be made of exactly the same material, and can be easily formed together with the first conductive layer 5 and the undercoat layer 4 by a printing process. After the formation of the first overcoat layer 6, a second conductive layer 7 is formed in a region above the circuit pattern 21. The second conductive layer 7 is formed of the same material as the first conductive layer 5 by screen printing, and is formed on the circuit pattern 21 to be connected to the circuit pattern 21 in the region B. The formation range of the second conductive layer 7 is determined so that a part thereof (the left side in the figure) faces a part of the first conductive layer 5. In the figure, the second conductive layer 7 and the first conductive layer 5 face each other in the region C. In this region C, the first overcoat layer 6 is sandwiched between the second conductive layer 7 and the first conductive layer 5, and a capacitor is formed in this portion. After the formation of the second conductive layer 7, a second overcoat layer 8 is formed over the entire surface of the substrate. This second overcoat layer 8
Denotes the first overcoat layer 6 and the undercoat layer 4
And in the same printing process.

In the above configuration, in the region C, the first conductive layer 5 and the second conductive layer 7 face each other with the first overcoat layer 6 interposed therebetween, and a capacitor is formed in this portion. Since the first conductive layer 5 is connected to the ground pattern 3 in the region A and the second conductive layer 7 is connected to the circuit pattern 21 in the region B, the capacitor formed in this region C is connected to the circuit pattern 21. Functions as a decap connected. Here, since the thickness of the first overcoat layer 6 is as extremely thin as about 20 to 40 μm, the capacitance of the decap formed at the portion C is sufficient to function as a decap. Moreover, the first conductive layer 5
Since the area where the second conductive layer 7 and the second conductive layer 7 face each other can be freely changed depending on the layout design of the screen mesh, a decap with a small capacitance and a decap with a large capacitance can be formed very easily.

As described above, the case where a decap is formed by the first conductive layer and the second conductive layer and the case where a bypass capacitor is used as a discrete component as in the related art are compared with actual examples. There are differences.

First, when a decap is used as a discrete component as in the prior art, assuming that the two lead wires of the decap are both a metal wire having a length of 5 mm and a diameter of 0.6 mm, the inductance L of the lead wire is calculated by equation (1). it can.

Here, μ; permeability of metal wire (= 4π × 10 ^-7 [H / m]) l; length of lead wire (= 5 × 10 ^-3 [m]) r; radius of lead wire (= 0.3 × 10 ^-3 [m]) That is, the inductance per lead wire is Now, the capacitance (C) of the bypass capacitor itself is 330 × 10
^-12 [F], the series impedance Z composed of the inductance of the two lead wires is calculated from equation (2).

However, f; frequency [Hz] Now, when we find the impedance at f = 100 MHz, Next, when a decap is formed by the first conductive layer and the second conductive layer, only the capacitance needs to be considered, and the impedance Z is calculated from the equation (3).

Where ε ₀ ; vacuum permittivity (8.854 * 10 ⁻¹² [F / m]) ε _r ; relative permittivity of undercoat layer S; facing area of conductive layer of connector land [m ² ] d; undercoat layer Now, assuming that ε _r = 5, S = 2 cm ² , and d = 30 μm, Similarly, the frequency characteristics of the impedance from 10 MHz to 1000 MHz are calculated for both, and plotted on a log-log graph as shown in FIG.

In FIG. 3, the horizontal axis represents frequency (MHz) and the vertical axis represents impedance (Ω). | Z _A | represents frequency characteristics of the conventional example, and | Z _B |

| Z _AC | and | Z _AL | indicate the frequency characteristics of the absolute value of the impedance due to the capacitance of the decap body and the inductance of the lead wire, respectively, of the conventional example.

As apparent from FIG. 3, the impedance is increased due to the inductance of the lead as the frequency increases in the conventional example, since it is added, so that an increase in the overall impedance Z _A also 100MHz or more.

On the other hand, since the decap of the embodiment has no inductance component, the impedance decreases as the frequency increases, so that it is extremely effective as a decap.

In the above embodiment, the example in which the decap is formed between the circuit pattern 21 and the ground pattern 3 has been described.
The conductive layer 5 may be connected to a power supply pattern instead of the ground pattern 3. Even in the case of such a configuration, the configuration of the region C does not change at all, and a bypass capacitor having a necessary capacity can be obtained.

FIG. 2 shows an example in which a decap is formed between a power supply pattern and a ground pattern. The difference from the wiring board shown in FIG. 1 in the configuration is that a portion to which the second conductive layer 7 is connected is replaced with a circuit pattern 21 and a power supply pattern 9. Everything else is exactly the same. Further, the first conductive layer 5 may be connected to the power supply pattern 9 and the second conductive layer 7 may be connected to the ground pattern 3. In any case, a decap for absorbing high frequency noise between the power supply and the ground pattern is formed in the area C.

(G) Effects of the Invention According to the present invention, the first EMI is reduced by the first conductive layer.
Countermeasures A radiation noise suppression effect similar to that of a printed wiring board can be obtained, and the second insulating layer and the second conductive layer are laminated thereon using the first conductive layer. A decap can be formed at a portion where the first conductive layer and the second conductive layer face each other. For this reason, it is possible to realize the radiation noise suppressing effect and the downsizing of the wiring board. Further, since no lead wire is required, there is no inductance component, and excellent frequency characteristics can be obtained as a bypass capacitor. Furthermore, since all the insulating layers and conductive layers can be formed by known screen printing, there is an advantage that the manufacturing process can be greatly simplified.

[Brief description of the drawings]

1 and 2 are cross-sectional views of a printed wiring board according to an embodiment of the present invention. FIG. 3 shows the frequency characteristics of impedance in the conventional example and the embodiment. 1 ... substrate, 2 (20, 21) ... circuit pattern, 3 ... ground pattern, 4 ... first insulating layer (undercoat layer), 5 ... first conductive layer, 6 ... second 7... A second conductive layer, 8... A second overcoat layer, 9... A power supply pattern.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hisatoshi Murakami 2-3-1, Iwatacho, Higashiosaka-shi, Osaka Tatsuta Electric Wire Co., Ltd. (72) Inventor Tsunehiko Terada 2-3-3, Iwatacho, Higashiosaka-shi, Osaka No. 1 Tatsuta Electric Wire Co., Ltd. (72) Shohei Morimoto 2-3-1, Iwatacho, Higashi-Osaka City, Osaka Prefecture Inside of Tatsuta Electric Wire Co., Ltd. (56) References JP-A-62-213194 (JP, A) 58-204516 (JP, A) (58) Field surveyed (Int. Cl. ⁶ , DB name) H05K 1/16

Claims (2)

(57) [Claims] 1. A substrate, a circuit pattern including a ground line pattern and / or a power supply line pattern and a signal line pattern formed on the substrate, and the ground line pattern or the power supply on the substrate on which the circuit pattern is formed. A first insulating layer formed so as to cover the circuit pattern except for at least a part of any one of the line patterns; and a ground line pattern or a power supply line pattern on the first insulating layer. A first conductive layer formed so as to be connected to a non-insulated portion, and a second insulating layer and a second conductive layer further laminated on the first conductive layer to form a first conductive layer. Conductive layer and second
Wherein a capacitor is formed between the conductive layers, and the second conductive layer is connected to an arbitrary portion of the circuit pattern. 2. A substrate, a circuit pattern including a ground line pattern and / or a power supply line pattern and a signal line pattern formed on the substrate, and the ground line pattern or the power supply on the substrate on which the circuit pattern is formed. A first insulating layer formed so as to cover the circuit pattern except for at least a part of any one of the line patterns; and a ground line pattern or a power supply line pattern on the first insulating layer. A first conductive layer formed so as to be connected to a non-insulated portion, and a second insulating layer and a second conductive layer further laminated on the first conductive layer to form a first conductive layer. Conductive layer and second
Wherein a capacitor is formed between the conductive layers, and the second conductive layer is connected to either the power line pattern or the ground line pattern.