JP2771912B2 - Arithmetic control method of vector arithmetic processing unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic control system for a vector arithmetic processing device comprising a plurality of arithmetic units.

[0002]

2. Description of the Related Art A conventional example will be described with reference to FIGS. 10 is a block diagram of a vector operation processing device applied to the present invention and the conventional example, FIG. 11 is a specific example of a vector register having the same configuration, FIG. 12 is a configuration diagram of a conventional arithmetic unit, and FIG. FIG. 14 shows an operation timing chart of a configuration example of a conventional arithmetic unit.

First, the configuration of a vector operation processing device will be described with reference to FIG. In order to facilitate the explanation, FIG.
0 indicates a case where the arithmetic unit is 4. Numeral 11 denotes an arithmetic unit, which executes arithmetic processing according to an instruction of the processor 15. Reference numeral 13 denotes a vector register in which data to be processed by the arithmetic unit 11 is recorded. 14 is a system bus. A bus 12 transfers data to an adjacent computing unit.

A vector register 13 is shown in FIG.
As shown, the memory corresponding to the X address and the Y address
The register of X address corresponds to X address
Is accessed. Vector arithmetic processing unit
In this case, various types of arithmetic processing are performed.
Processing for obtaining the sum is also frequently performed. That is, FIG.
Data D indicated by 1 ₀−0 to D_Three-4, for example, all
Processing for obtaining the sum of all data is frequently performed. this
In this case, each computing unit is connected to the vector
The sum of data for the corresponding X address of the
Ask. That is, the arithmetic unit 11-3 starts from the X address.
Some data D_Three−0 to D_Three-4 is obtained. afterwards,
The sum obtained by each operation unit transfers the data to the adjacent operation unit.
Transferred to a computing unit 11-0 via a bus 12
At 11-0, summation processing is executed. The present invention provides a
The present invention relates to an arithmetic control method at the time of execution of processing.

Next, a configuration example of each conventional arithmetic unit is shown in FIG.
This will be described with reference to FIG. R13, R14, R24, R5
R6 and R7 are registers capable of recording m pieces of k-byte data. That is, it is a register that can record 8 km-bit data. However, hereinafter, for the sake of simplicity, the description will be made on the assumption that k = 1 and m = 4.

Further, S1, S2 and S3 are selectors for selecting data to be input to the register. A bus 1 for transferring data of km bytes between the vector register 13 and the arithmetic unit 11 is used to transfer data to an adjacent arithmetic unit.
2 is a k-byte dedicated bus. Therefore, the register R13 divides a km-byte memory into k-byte m buses.
It can be configured as individual and store data.

The register R7 is a register R7a for storing upper (m-1) k-byte data of the register R6.
And a register R7b for storing the data of k bytes from the select S3. The selector S3 divides the km-byte data of the register R6 into k-byte m data, selects one of the divided k-byte data and the k-byte data from the register R13, and outputs the selected data to the register R7b.

Reference numeral 1 denotes an arithmetic logic unit (ALU). Next, the operation of calculating the sum of the data stored in the vector register shown in FIG. 11 will be described with reference to the operation timing chart shown in FIG. First, the CPU 15 sends an addition instruction of the data recorded in the vector register 12 connected to each operation unit to all the operation units, and each operation unit executes an addition process. FIG. 13 shows the addition process as a representative of the arithmetic unit 0.

[0009] Upon receiving the add instruction from the CPU 15, reads the data D ₀ -0~D ₀ -4 vector registers sequentially shown in FIG. 11 at T ₄ from the time T ₀ of the arithmetic unit 0, stored in the register R13, transferred to the register R14 at the next timing (T ₁ ~T _5). Further, in the next timing perform data addition register R24 and R14 in ALU1, and store the result in register R5 (T ₂ ~T _6). At the next timing, the data of the register R5 is transferred to the register R24.
(T _{3 to} T ₆ ). Note that in addition in ALU1, data (time T ₁ and T ₂₎ of the register R24 in the first and second times are set to zero.

Therefore, the time T₆At the register R
5 has data D₀−0, D₀-2 and D₀Addition of -4
The result and the data D are stored in the register R24.₀-1 and
D₀3 is stored. Time T₇Then cash register
Star R_FiveIs transferred to the register R14, and the next time
T₈With register R_FiveAnd the data of R14 are added
Star R_FiveAnd the next T ₉Moved to register R24
It is.

[0011] Note that the same addition process in calculator other than computing unit 0 is performed simultaneously at time T ₉ register R5
Is moved to the register R6. When the addition processing in each computing unit is completed, the CPU sends a command for calculating the sum of the addition results in each computing unit, and each computing unit starts terminating the sum.

[0012] First, the arithmetic unit 1 starts the process, four split register R6 (m = 4) has been transferred to a k-byte data sequentially register R7b the (T ₁₀ ~T _13). The data for the register R7b at the next timing to transfer to the register R13 of the arithmetic unit 0 using a dedicated bus 12-1 (T ₁₁ ~
T _14). That is, the addition data stored in the register R6 of the arithmetic unit 1 in T ₁₄ will be transferred to the register R13 of the arithmetic unit 0.

In the arithmetic unit 0, the time T_FifteenIn the register R13
Transfer the data to register R14, ₁₆Addition of arithmetic unit 0
Addition with register R24 storing data is performed
Is recorded in the register R5. The data in register R5 is
T for the next addition₁₇Is transferred to the register 24.

[0014] In parallel with the above operation, the arithmetic unit in 2 at time T ₁₂ through T ₁₅ were transferred data in the register R6 to register R7b, register sequentially calculator 1 at the next timing R13
Is transferred to the register storing the least significant k bytes of (T
₁₃ ~T _16). Further, following (T ₁₄ data to the register R7b through selector 3 from the arithmetic unit 2 which is stored in the least significant byte storage memory register R13 at the timing ~T
₁₇ ) Also, at the next timing, the register R13
(T _{15 to} T ₁₈ ), and the same addition processing as described in the addition with the arithmetic unit 1 is performed.

[0015] initiated from work time T ₁₄ of the arithmetic unit 3,
Performs the same operation as described in the calculator 2, through the registers R13 and R7b computing units 2 and 1 are transferred to the register R13 of the arithmetic unit 0, the sum is stored in register R5 at T _24, the following registers R6 and total addition processing at the time T ₂₆ is moved to R7 is terminated.

Although the configuration of the conventional example described above has four arithmetic units, a general vector arithmetic processing unit is composed of more arithmetic units. When the number of arithmetic units increases,
The time required to transfer data from each arithmetic unit to the arithmetic unit 0 (T _{9 to} T _{22 in} FIG. 13) becomes longer. To shorten this transfer time, a configuration shown in FIG. 14 can be considered. That is, the registers R13 and R13 involved in data transfer
It is also conceivable to separately configure the register 7b into registers FR and TR operating at high speed.

[0017]

As described above, in the processing for obtaining the sum of the data recorded in the vector registers in the conventional vector operation processing device, the addition result of each operation unit is sent to the operation unit for obtaining the sum. The time required for data transfer was very long.

Further, in order to shorten the transfer time,
It is conceivable to separately configure registers involved in data transfer into registers that operate at high speed. In this case,
Because of the separate configuration, the amount of material increases, and the cost becomes complicated and expensive. SUMMARY OF THE INVENTION It is an object of the present invention to provide an operation control method of a vector operation processing device improved so as to shorten a data transfer time for transferring data of each operation unit to a certain operation unit.

[0019]

Means adopted by the present invention to solve the above-mentioned problems will be described with reference to FIG.
FIG. 1 is a diagram illustrating the principle of the present invention. At least a register R1 for inputting a first operand from a vector register
3, a register R6 that allows input of K-byte data from a subsequent-stage arithmetic unit to each of the registers obtained by dividing the register R13 by m, and receives a second operand and an operation result for the data of the register R13; M divided data of the register R6 and the register R1
Selector S3 for selecting any one of the three k-byte data
And a register R7 divided into a register R7a for inputting k (m-1) -byte data from the register R6 and a register R7b for inputting k-byte data from the selector S3. In a vector operation processing device having a plurality of
Timing switching means A1 for switching to clock timing
00, a timing switching means B101 for switching a clock timing for operating the register R7b to a high-speed clock timing , and a generation of a selector signal for operating the selector S3 to a high-speed clock timing.
Selector switching means 102 for generating the data .

[0020]

The timing switching means A100, the timing switching means B101, and the selector switching means 102 start operating in response to a specific instruction from the CPU of the vector arithmetic processing unit, and the register R13 is operated by the timing switching means A100 and the timing switching means B101 is operated. By operating the register R7b at high speed, the selector switching means 10
2, the selector S3 sends out a signal for selecting at high speed to switch the selector.

As described above, the register and the selector involved in the data transfer to the operation unit at the preceding stage from the operation unit at the subsequent stage operate at high speed by the specific instruction from the CPU, so that the data transfer time is made very short. be able to.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to FIGS. FIG. 2 shows a configuration of the embodiment of the present invention, FIG. 3 shows a specific example of the timing control signal generation circuit of the embodiment, FIG. 4 shows a specific example of the timing switching circuit A of the embodiment, and FIG. 6 is a specific example of the select signal generation circuit of the embodiment, FIG. 7 is a specific example of the selector switch circuit of the embodiment, FIG. 8 is an operation timing chart of the embodiment, and FIG. 4 is a timing chart of the embodiment.

In FIG. 2, registers R13, R14,
R24, R5, R6, R7, selectors S1, S2, S3
ALU1 and ALU1 are as described in FIG. 12, and timing switching means A100, timing switching means B101 and selector switching means 102 are as described in FIG.

In the embodiment, the timing switching means A100
Is a counter (Fc) 2, a timing control signal generation circuit 3
And a switching circuit A4.
101 is a timing switching circuit B5, also selector SWITCHING means 102 is composed of a select signal generating circuit 6 and the selector switching circuit 7.

As shown in FIG. 3, the timing control signal generating circuit 3 includes OR circuits 31a to 31f and an AND circuit 32.
a to e. Signal Fcn input to OR circuit
N corresponds to the count value n of the counter (Fc) 2, and when the count value is n, "1" is input. Inputs “+ operation unit 0” and “− operation unit 0” to the AND circuit input “1” and “0” to input terminals corresponding to operation unit 0, respectively. Input the opposite signal. That is, "0" is input for "1", and "1" is input for "0". "SIG" will be described later.

As shown in FIG. 4, the timing switching circuit A4 includes AND circuits 41a to 41f and an OR circuit 42a.
To d. When the count value of the counter (Fc) 2 is 0, the output of the AND 41f is a normal clock , the AND 41e is "0", signals of the normal clock are output to the outputs of the OR circuits 42a to 42d, and the write of the register R13 is performed. Timing is provided. When the count value of Fc2 is other than 0, based on the control signal (R13-0 to -3 control) from the timing control signal generation circuit 3,
The write timing is supplied to the registers R13-0 to R3-3 at the timing of the double clock.

As shown in FIG. 5, the timing switching circuit B5 comprises AND circuits 51a and B and an OR circuit 52. Accordingly, although the write timing to the register R7a is not changed, the write timing to the register R7b is switched between the normal clock and the double clock signal based on the R7b control signal from the timing control signal generation circuit 3.

As shown in FIG. 6, select signal generation circuit 6 includes AND circuits 61a-61c, Rs flip-flop 6
2, a counter 63 and a 5-decoder 64.
Fc (n) input to the AND circuit 61a is made to correspond to the number n of the arithmetic unit on which the select signal generation circuit 6 is mounted, and "1" when the count value of the counter (Fc) 2 is n.
Is input, the RS-FF 62 is set, and the counter 63 starts counting at the double clock. The 5-decoder 64 detects that the count value of the counter 63 has become 5, and blocks passage of the double clock signal input to the counter 63 from the AND circuit 61c. Therefore, the control of the signal S3 output from the counter 63 takes a value of 0 to 5. Also,
The RS-FF 62 and the counter 63 are counters (Fc)
It is reset to 0 by the count value 7 of 2.

The selector switching circuit 7 includes AND circuits 71a and 71b and an OR circuit 72, as shown in FIG. The selector signal to the selector S3 is formed of a numerical signal corresponding to the select terminal number, and the numerical value of the numerical signal is decoded by a decoder (not shown) in the select S3 to select a corresponding terminal. When the count value of the counter (Fc) 2 is 0, a normal control signal is output from the selector S
When the count value of the counter (Fc) 2 is other than 0, the S3 control signal output from the select signal generating circuit 6 is applied to the selector S3.

Next, the operation of the embodiment will be described with reference to a conventional example.
Processing similar to the processing to calculate the sum of
The operation will be described with reference to FIGS. Figure
8, at time T₀~ T₈Is explained with reference to FIG.
In the same way as in
Data addition is performed. Also, the time T₉~ T _FifteenFigure 13
Each operation unit has a timing that is twice the timing described in
And the data recorded in the register R6 is
The data is transferred to the operation unit at the stage before the next stage and the sum is calculated at operation unit 0.
Desired. Also, the time T₁₆~ T₁₉Is the conventional example in FIG.
Explained time T_{twenty three}~ T₂₆The same processing as described above is performed.

The start of data transfer with a double clock of the times T _{9 to} T ₁₅ is started when the counter (Fc) 2 starts counting. The counter (Fc) 2 is repeated with a count value of 7, and the counting is started by an instruction from the CPU 15. The CPU completes the addition of the data of the vector register 13 in each arithmetic unit (T ₈ ).
Then, a command for obtaining the sum of the addition results of the respective arithmetic units is instructed. With this instruction, the count (Fc) 2 starts counting (T ₉ ).

In FIG. 9, the normal clock is the clock timing at which the arithmetic unit normally operates, the double clock is the clock timing of twice the normal clock frequency, and the SIG is the duty 50 relative to the normal clock.
%, The output is set to "1" during the period indicated by the solid line.

First, the operation of the timing control signal generation circuit 3 of the arithmetic unit 0 will be described. 3 is input to the AND circuits 32a to 32d of FIG. 3 as "1" and "0" is input to the AND circuit 32e. Output (R13-0 control)
Have count values of the counter (Fc) of 1, 3 and 5
A pulse is output during a period in which AND of signal and signal SIG is taken. Similarly, the AND circuits 32b and 32c and the OR circuit 31e have R13-1 to R13-1 shown in FIG.
-3 control is output.

As described above, the operation units other than the operation unit 0 receive "0" to the "+ operation unit 0" and "1" to the "-operation unit 0". No pulse is sent to the output (R13-0 to R13-2) corresponding to c, and only the OR circuit 31e outputs a pulse indicated by the R13-3 control in the period "1" of the count value 2 to 6 of the counter (Fc). Output.

The control signal R7b to the register R7b
In control, "1" is output from 1 to 7 in the count value of the counter (Fc) in all the arithmetic units. The R13-0 to -3 control signals generated in this manner are transmitted to the timing switching circuit A.
4, the data write timing to the register R13 is doubled as described above, and the operation is performed.
The b control signal is input to the timing switching circuit B7, and operates by doubling the data write timing to the register R7b as described above.

In the selector signal generating circuit 6, when the count value of the counter (Fc) coincides with the value corresponding to the arithmetic unit number n, the SR-FF 62 is set, and the counter 62 shown in FIG. Start counting.
Therefore, for example, the selector signal generation circuit 6 of the arithmetic unit 3 starts counting with a double clock when the count value of the counter (Fc) 2 is 1, and stops when the count value is 5. Also, when the count value of the counter (Fc) is 7, it is reset to 0. The S3 control signal output from the counter 63 is input to the selector switching circuit 7, and the selector S3 selects the terminal of the corresponding number at high speed, and
Output data to b.

By performing the operation described above, in the conventional example, the data transfer to the arithmetic unit 0 from each operation required from time T ₉ to time T ₂₂ as shown in FIG. complete with T ₉ through T _14, it can be very short processing time. Although the number of arithmetic units is four in the embodiment described above, the number is not limited to four, and the present invention is applied to a plurality of arithmetic units.

Although one embodiment of the present invention has been described above, the present invention is not limited to this embodiment, and various modifications in accordance with the gist of the invention are possible.

[0039]

As described above, according to the present invention, the following effects can be obtained. The register and the selector involved in the data transfer to the operation unit at the preceding stage from the operation unit at the subsequent stage operate at high speed by the specific instruction from the CPU, so that the data transfer time can be made very short.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a configuration diagram of one embodiment of the present invention.

FIG. 3 is a specific example of a timing control signal generation circuit of the embodiment.

FIG. 4 is a specific example of a timing switching circuit A of the embodiment.

FIG. 5 is a specific example of a timing switching circuit B of the embodiment.

FIG. 6 is a specific example of a select signal generation circuit of the embodiment.

FIG. 7 is a specific example of the selector switching circuit of the embodiment.

FIG. 8 is an operation timing chart of the embodiment.

FIG. 9 is a timing chart of the embodiment.

FIG. 10 is a configuration diagram of a vector operation processing device to which the present invention and a conventional example are applied.

FIG. 11 is a specific example of a vector register.

FIG. 12 is a configuration diagram of a conventional arithmetic unit.

FIG. 13 is a conventional operation timing chart.

FIG. 14 is a configuration diagram of a conventional arithmetic unit.

[Explanation of symbols]

REFERENCE SIGNS LIST 100 timing switching means A 101 timing switching means B 102 selector switching means 1 arithmetic logic unit (ALU) 2 counter (Fc) 3 timing control signal generating circuit 4 timing switching circuit A 5 timing switching circuit B 6 select signal generating circuit 7 selector switching Circuit 11 Operation unit 12 Dedicated bus 13 Vector register 14 System bus 15 Processor (CPU) 31, 42, 52, 72 OR circuit 32, 41, 51, 61, 71 AND circuit 62 RS flip-flop (RS-FF) 63 Counter 64 5 decoders R13, R14, R24, R5, R6, R7, FR, T
R register S1, S2, S3 selector

Claims (2)

(57) [Claims] 1. A register (R13) for inputting at least a first operand from a vector register,
A register (R6) that enables input of k-byte data from a subsequent-stage arithmetic unit to each of the registers obtained by dividing the register (R13) into m, and that receives a second operand and an operation result for the data in the register (R13). A selector (S3) for selecting one of the m-divided data of the register (R6) and the k-byte data of the register (R13); and k (m) from the register (R6).
-1) A register (R7) divided into a register (R7a) for inputting byte data and a register (R7b) for inputting k-byte data from the selector (S3).
In the vector processing unit having a plurality of computing units with bets by the particular instruction, and the timing switching means A (100) for switching the clock timing for operating the register (R13) in the high-speed clock timing, the register (R7b ), The timing switching means B (101) for switching the clock timing to the high-speed clock timing , and the generation of a select signal for operating the selector (S3).
And a selector switching means (102) for generating by switching to a high-speed clock timing . 2. The method according to claim 1, wherein the specific instruction updates data of each arithmetic unit
It is a command to be transferred to the preceding computing unit
An arithmetic control method for the vector arithmetic processing device according to claim 1.