JP2770091B2 - Silicon wafer processing method - Google Patents
Silicon wafer processing methodInfo
- Publication number
- JP2770091B2 JP2770091B2 JP3332779A JP33277991A JP2770091B2 JP 2770091 B2 JP2770091 B2 JP 2770091B2 JP 3332779 A JP3332779 A JP 3332779A JP 33277991 A JP33277991 A JP 33277991A JP 2770091 B2 JP2770091 B2 JP 2770091B2
- Authority
- JP
- Japan
- Prior art keywords
- atoms
- silicon wafer
- heat treatment
- wafer
- less
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
- H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体製造に用いられる
半導体シリコンウエハ中の欠陥、とくにＳＰＤ（Sarfac
e Particle and Defect)と称される、ウエハ表面の欠陥
及び汚損を低減させるためのウエハ処理技術に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to defects in semiconductor silicon wafers used in semiconductor manufacturing, particularly SPD (Sarfac).
The present invention relates to a wafer processing technique called e Particle and Defect) for reducing defects and contamination on a wafer surface.
【０００２】[0002]
【従来の技術】半導体デバイスの製造に当り、その特性
の簡易的評価方法として、ＭＯＳダイオードを作成し、
酸化膜耐圧を測定するものが従来から採用されている。
図２に示したように、この酸化膜耐圧による不良率とＳ
ＰＤとの関係が最近明らかになってきた。2. Description of the Related Art In manufacturing a semiconductor device, a MOS diode is prepared as a simple evaluation method of its characteristics.
A device for measuring the withstand voltage of an oxide film has been conventionally used.
As shown in FIG. 2, the defect rate due to this oxide film breakdown voltage and S
The relationship with PD has recently been revealed.
【０００３】すなわち、ＳＰＤが増加する程、酸化膜耐
圧不良が増加する。これは、デバイス歩留りでも確認さ
れており、ＳＰＤが増加する程、デバイス歩留も同様に
悪くなる。一方、このＳＰＤは図３に示すように結晶成
長条件の一つである引上げ速度とも相関関係があること
が分かっている。すなわち、引上げ速度を速くして引上
げた単結晶から得られたウエハ程、ＳＰＤは多くなる。That is, as the SPD increases, the oxide film breakdown voltage failure increases. This has been confirmed in device yield, and as SPD increases, device yield similarly worsens. On the other hand, it is known that the SPD has a correlation with the pulling speed, which is one of the crystal growth conditions, as shown in FIG. In other words, the SPD increases as the wafer obtained from a single crystal pulled at a higher pulling speed.
【０００４】[0004]
【発明が解決しようとする課題】したがつて、ＳＰＤを
減少させる手っ取りばやい手段としては、単結晶製造の
際に、引上げ速度を遅くしてやれば良いことになるが、
当然これでは生産性が低下することにもなるし、その他
の物性、たとえば酸素誘起欠陥や酸素析出能等に影響を
与える。Therefore, a quick and easy means to reduce SPD is to reduce the pulling speed during the production of a single crystal.
Naturally, this will lower the productivity and affect other physical properties such as oxygen-induced defects and oxygen precipitation ability.
【０００５】本発明は引上げ速度を上げて育成した単結
晶より得たウエハであっても、ＳＰＤを減少させること
のできる新たな技術を提供するものである。The present invention provides a new technique capable of reducing SPD even for a wafer obtained from a single crystal grown at an increased pulling speed.
【０００６】[0006]
【課題を解決するための手段】すなわち、第一の発明に
おいては、酸素濃度１×1017〜２×1018atoms/cc、炭素
濃度１×1016atoms/cc以下の未熱処理の半導体シリコン
ウエハを酸化雰囲気中で1000℃〜1300℃の温度で0.5〜5
時間熱処理するものである。That is, in the first invention, an unheated semiconductor silicon wafer having an oxygen concentration of 1 × 10 17 to 2 × 10 18 atoms / cc and a carbon concentration of 1 × 10 16 atoms / cc or less is provided. In an oxidizing atmosphere at a temperature of 1000-1300 ° C for 0.5-5
Heat treatment for a long time.
【０００７】第二の発明は、酸素濃度１×1017〜２×10
18atoms/cc、炭素濃度１×1016atoms/cc以下の未熱処理
の半導体シリコンウエハを不活性雰囲気中で1000℃〜13
00℃の温度で0.5〜5時間熱処理する。The second invention relates to an oxygen concentration of 1 × 10 17 to 2 × 10
An unheated semiconductor silicon wafer having a carbon concentration of 18 atoms / cc and a carbon concentration of 1 × 10 16 atoms / cc or less is heated to 1000 ° C. to 13 ° C. in an inert atmosphere.
Heat treatment at a temperature of 00 ° C. for 0.5 to 5 hours.
【０００８】第三の発明は、酸素濃度１×1017〜２×10
18atoms/cc、炭素濃度１×1016atoms/cc以下の未熱処理
の半導体シリコンウエハを酸化雰囲気中で1000℃〜1300
℃の温度で0.5〜5時間熱処理した後、主表面を研磨す
る。[0008] The third invention relates to an oxygen concentration of 1 × 10 17 to 2 × 10
An unheated semiconductor silicon wafer having 18 atoms / cc and a carbon concentration of 1 × 10 16 atoms / cc or less is heated to 1000 ° C. to 1300 ° C. in an oxidizing atmosphere.
After the heat treatment at a temperature of 0.5 ° C. for 0.5 to 5 hours, the main surface is polished.
【０００９】第四の発明は、酸素濃度１×1017〜２×10
18atoms/cc、炭素濃度１×1016atoms/cc以下の未熱処理
の半導体シリコンウエハを不活性雰囲気中で1000℃〜13
00℃の温度で0.5〜5時間熱処理した後、主表面を研磨す
る。In a fourth aspect of the present invention, an oxygen concentration of 1 × 10 17 to 2 × 10
An unheated semiconductor silicon wafer having a carbon concentration of 18 atoms / cc and a carbon concentration of 1 × 10 16 atoms / cc or less is heated to 1000 ° C. to 13 ° C. in an inert atmosphere.
After heat treatment at a temperature of 00 ° C. for 0.5 to 5 hours, the main surface is polished.
【００１０】[0010]
【作用】ＳＰＤは、単結晶育成中の結晶降温過程におい
て形成されるある種の欠陥ではないかと考えられるが、
現在のところ未だ明確なことは分かっていない。しか
し、酸素濃度１×1017〜２×1018atoms/cc、炭素濃度１
×1016atoms/cc以下のシリコンウエハならば、本発明の
ように1000℃以上の温度処理によりこれらが溶態化する
のではないかと考えらる。[Function] It is considered that SPD is a kind of defect formed in the crystal cooling process during single crystal growth.
At this time, nothing is clear. However, the oxygen concentration is 1 × 10 17 to 2 × 10 18 atoms / cc and the carbon concentration is 1
It is considered that silicon wafers of × 10 16 atoms / cc or less may be dissolved by a temperature treatment of 1000 ° C. or more as in the present invention.
【００１１】[0011]
【実施例１】チョクラルスキー法により製造したシリコ
ン単結晶から得た、導電型Ｎ型、結晶軸（100）、抵抗
率５〜10Ω-cm、酸素濃度15×1017atoms/cc（常温FTIR
法による）、炭素濃度１×1016atoms/cc（常温FTIR法に
よる検出限界）以下、直径５″のウエハ25枚を酸化雰囲
気で、1200℃の温度で、２時間の熱処理をした。Example 1 Conductive N-type, crystal axis (100), resistivity 5-10 Ω-cm, oxygen concentration 15 × 10 17 atoms / cc (room temperature FTIR) obtained from a silicon single crystal manufactured by the Czochralski method
25), and 25 wafers having a diameter of 5 ″ were heat-treated in an oxidizing atmosphere at a temperature of 1200 ° C. for 2 hours under a carbon concentration of 1 × 10 16 atoms / cc (detection limit by the normal temperature FTIR method).
【００１２】条件の詳細は、下記のとおりである。 酸素ガス流量：６Liter／分 熱処理炉へのウエハの入出速度：12cm／分 昇温速度：８℃／分 降温速度：３℃／分 1200℃での保持時間：２時間The details of the conditions are as follows. Oxygen gas flow rate: 6 Liter / min Wafer in / out speed to heat treatment furnace: 12 cm / min Heating rate: 8 ° C / min Cooling rate: 3 ° C / min Holding time at 1200 ° C: 2 hours
【００１３】さらに同一の物性を有するシリコン単結晶
から得られたウエハ25枚ずつを、1100℃及び1000℃でも
熱処理を施した。Further, 25 wafers each obtained from a silicon single crystal having the same physical properties were subjected to a heat treatment at 1100 ° C. and 1000 ° C.
【００１４】[0014]
【参考例１】チョクラルスキー法により製造したシリコ
ン単結晶から得た、導電型Ｎ型、結晶軸（100）、抵抗
率５〜10Ω-cm、酸素濃度15×1017atoms/cc、炭素濃度
１×1016atoms/cc（常温FTIR法による検出限界）以下、
直径５″のウエハ25枚を酸化雰囲気で、900℃の温度
で、２時間の熱処理をした。Reference Example 1 Conductive N-type, crystal axis (100), resistivity 5-10 Ω-cm, oxygen concentration 15 × 10 17 atoms / cc, carbon concentration obtained from a silicon single crystal manufactured by the Czochralski method Less than 1 × 10 16 atoms / cc (detection limit by room temperature FTIR method)
Twenty-five wafers having a diameter of 5 ″ were heat-treated in an oxidizing atmosphere at a temperature of 900 ° C. for 2 hours.
【００１５】条件の詳細は、下記のとおりである。 酸素ガス流量：６Liter／分 熱処理炉へのウエハの入出速度：12cm／分 昇温速度：８℃／分 降温速度：３℃／分 900℃での保持時間：２時間The details of the conditions are as follows. Oxygen gas flow rate: 6 Liters / min Wafer in / out speed to heat treatment furnace: 12 cm / min Heating rate: 8 ° C / min Cooling rate: 3 ° C / min Holding time at 900 ° C: 2 hours
【００１６】さらに同一の物性を有するウエハ25枚ずつ
を、800℃及び700℃でも熱処理を施した。Further, 25 wafers having the same physical properties were heat-treated at 800 ° C. and 700 ° C.
【００１７】上記実施例１及び参考例２で得られたウエ
ハのＳＰＤ数の平均値を、処理温度毎でプロットしたの
が図１である。これよりかわるように、1000℃以上の熱
処理によりウエハ中のSPD数は、激減している。FIG. 1 shows the average values of the SPD numbers of the wafers obtained in Example 1 and Reference Example 2 plotted for each processing temperature. Alternately, the number of SPDs in a wafer is drastically reduced by heat treatment at 1000 ° C. or higher.
【００１８】[0018]
【実施例２】チョクラルスキー法により製造したシリコ
ン単結晶から得た、導電型Ｐ型、結晶軸（100）、抵抗
率６〜10Ω-cm、酸素濃度15×1017atoms/cc、炭素濃度
１×1016atoms/cc以下、直径６″のウエハ25枚の酸化膜
耐圧を測定したところ、不良率60％であり、ＳＰＤは平
均300ケ/ウエハであった。これに不活性雰囲気中で1000
℃、４時間の熱処理を施したところ、ＳＰＤは平均 10
ケ/ウエハ以下減少し、酸化膜耐圧不良は５％となっ
た。Example 2 Conductive P-type, crystal axis (100), resistivity 6-10 Ω-cm, oxygen concentration 15 × 10 17 atoms / cc, carbon concentration obtained from silicon single crystal manufactured by Czochralski method Oxide film breakdown voltage of 25 wafers with a diameter of 6 ″ or less, 1 × 10 16 atoms / cc or less, was found to have a failure rate of 60% and an average SPD of 300 wafers / wafer. 1000
After heat treatment at 4 ℃ for 4 hours, SPD averaged 10
The number of wafers decreased to less than 10 / wafer, and the withstand voltage failure of the oxide film became 5%.
【００１９】[0019]
【実施例３】チョクラルスキー法により製造したシリコ
ン単結晶から得た、導電型Ｐ型、結晶軸（100）、抵抗
率１〜２Ω-cm、酸素濃度18×1017atoms/cc、炭素濃度
１×1016atoms/cc以下、直径６″のウエハ25枚を、C−M
OSデバイス形成工程を通過させ、酸化膜耐圧試験を行な
った。酸化膜耐圧試験では、良品率70％で、ウエハ中の
ＳＰＤは平均350ケ/ウエハであった。このウエハを、12
50℃、30分、酸化雰囲気中で熱処理したところ良品率は
85％に、ＳＰＤ数は平均 10ケ/ウエハであった。さら
に、これらのウエハの主表面を鏡面研磨したところ、Ｓ
ＰＤは平均 10ケ/ウエハと変化しなかったものの、良品
率は90%に向上した。Example 3 Conductive P-type, crystal axis (100), resistivity 1-2 Ω-cm, oxygen concentration 18 × 10 17 atoms / cc, carbon concentration obtained from a silicon single crystal manufactured by the Czochralski method 25 wafers of 1 × 10 16 atoms / cc or less and 6 ″ in diameter were subjected to C-M
After passing through an OS device forming process, an oxide film breakdown voltage test was performed. In the oxide film breakdown voltage test, the yield rate was 70%, and the average number of SPDs in the wafer was 350 / wafer. This wafer is
After heat treatment at 50 ° C for 30 minutes in an oxidizing atmosphere,
At 85%, the average number of SPDs was 10 / wafer. Further, when the main surfaces of these wafers were mirror-polished,
Although the average PD was unchanged at 10 wafers / wafer, the non-defective rate improved to 90%.
【００２０】なお、実施例１，２においても、熱処理後
に鏡面研磨を施しても同様の結果が得られた。In Examples 1 and 2, similar results were obtained even if mirror polishing was performed after the heat treatment.
【００２１】[0021]
【発明の効果】酸素濃度１×1017〜２×1018atoms/cc、
炭素濃度１×1016atoms/cc以下の半導体シリコンウエハ
の場合、酸化性または不活性雰囲気中で1000℃以上の熱
処理を施す本発明の熱処理方法を用いることにより、酸
化膜耐圧を大幅に向上させることができる。またさら
に、この熱処理後ウエハの主表面を鏡面研磨することで
さらに歩留りを向上させることができる。したがって、
デバイスを形成した場合、生産性を大幅に向上させるこ
とができる。According to the present invention, the oxygen concentration is 1 × 10 17 to 2 × 10 18 atoms / cc,
In the case of a semiconductor silicon wafer having a carbon concentration of 1 × 10 16 atoms / cc or less, the withstand voltage of an oxide film is significantly improved by using the heat treatment method of the present invention in which a heat treatment of 1000 ° C. or more is performed in an oxidizing or inert atmosphere. be able to. Furthermore, the yield can be further improved by mirror polishing the main surface of the wafer after the heat treatment. Therefore,
When a device is formed, productivity can be significantly improved.
【００２２】なお、インゴットより切り出された未熱処
理のウエハは、まず最初にサーマルドナー消去のための
650℃程度の熱処理を施されたるのが通常であるが、本
発明の熱処理は、サーマルドナー消去作用も併せもつの
で、必要はない。The unheated wafer cut from the ingot is first used for erasing the thermal donor.
Usually, a heat treatment of about 650 ° C. is performed, but the heat treatment of the present invention is not necessary since it also has a thermal donor erasing action.
【図１】熱処理温度とシリコンウエハ中のＳＰＤの関係
を示す図。FIG. 1 is a diagram showing a relationship between a heat treatment temperature and SPD in a silicon wafer.
【図２】酸化膜耐圧不良率とＳＰＤの関係を示す図。FIG. 2 is a diagram showing a relationship between an oxide film breakdown voltage failure rate and SPD.
【図３】チョクラルスキー法による単結晶引上げ速度と
結晶中のＳＰＤ数の関係を示す図。FIG. 3 is a diagram showing a relationship between a single crystal pulling speed according to the Czochralski method and the number of SPDs in a crystal.
Claims (4)
素濃度１×1016atoms/cc以下の未熱処理の半導体シリコ
ンウエハを酸化雰囲気中で1000℃〜1300℃の温度で0.5
〜5時間熱処理することを特徴とするシリコンウエハの
処理方法。An unheated semiconductor silicon wafer having an oxygen concentration of 1 × 10 17 to 2 × 10 18 atoms / cc and a carbon concentration of 1 × 10 16 atoms / cc or less is heated at a temperature of 1000 ° C. to 1300 ° C. in an oxidizing atmosphere. 0.5
A method for treating a silicon wafer, comprising performing heat treatment for up to 5 hours.
素濃度１×1016atoms/cc以下の未熱処理の半導体シリコ
ンウエハを不活性雰囲気中で1000℃〜1300℃の温度で0.
5〜5時間熱処理することを特徴とするシリコンウエハの
処理方法。2. An unheated semiconductor silicon wafer having an oxygen concentration of 1 × 10 17 to 2 × 10 18 atoms / cc and a carbon concentration of 1 × 10 16 atoms / cc or less is heated to a temperature of 1000 ° C. to 1300 ° C. in an inert atmosphere. At 0.
A method for treating a silicon wafer, comprising performing heat treatment for 5 to 5 hours.
素濃度１×1016atoms/cc以下の未熱処理の半導体シリコ
ンウエハを酸化雰囲気中で1000℃〜1300℃の温度で0.5
〜5時間熱処理した後、主表面を研磨することを特徴と
するシリコンウエハの処理方法。3. An unheated semiconductor silicon wafer having an oxygen concentration of 1 × 10 17 to 2 × 10 18 atoms / cc and a carbon concentration of 1 × 10 16 atoms / cc or less at a temperature of 1000 ° C. to 1300 ° C. in an oxidizing atmosphere. 0.5
A method for treating a silicon wafer, comprising polishing the main surface after heat treatment for up to 5 hours.
素濃度１×1016atoms/cc以下の未熱処理の半導体シリコ
ンウエハを不活性雰囲気中で1000℃〜1300℃の温度で0.
5〜5時間熱処理した後、主表面を研磨することを特徴と
するシリコンウエハの処理方法。4. An unheated semiconductor silicon wafer having an oxygen concentration of 1 × 10 17 to 2 × 10 18 atoms / cc and a carbon concentration of 1 × 10 16 atoms / cc or less is heated to a temperature of 1000 ° C. to 1300 ° C. in an inert atmosphere. At 0.
A method for treating a silicon wafer, comprising polishing the main surface after heat treatment for 5 to 5 hours.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3332779A JP2770091B2 (en) | 1991-11-22 | 1991-11-22 | Silicon wafer processing method |
| PCT/JP1992/000662 WO1993010557A1 (en) | 1991-11-22 | 1992-05-22 | Method for processing silicon wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3332779A JP2770091B2 (en) | 1991-11-22 | 1991-11-22 | Silicon wafer processing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05144827A JPH05144827A (en) | 1993-06-11 |
| JP2770091B2 true JP2770091B2 (en) | 1998-06-25 |
Family
ID=18258735
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3332779A Expired - Lifetime JP2770091B2 (en) | 1991-11-22 | 1991-11-22 | Silicon wafer processing method |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2770091B2 (en) |
| WO (1) | WO1993010557A1 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998005063A1 (en) * | 1996-07-29 | 1998-02-05 | Sumitomo Sitix Corporation | Silicon epitaxial wafer and method for manufacturing the same |
| US5893982A (en) * | 1997-01-08 | 1999-04-13 | Seh America, Inc. | Prevention of edge stain in silicon wafers by oxygen annealing |
| KR20010083771A (en) * | 1998-12-28 | 2001-09-01 | 와다 다다시 | Method for thermally annealing silicon wafer and silicon wafer |
| US7160385B2 (en) | 2003-02-20 | 2007-01-09 | Sumitomo Mitsubishi Silicon Corporation | Silicon wafer and method for manufacturing the same |
| WO2004008521A1 (en) * | 2002-07-17 | 2004-01-22 | Sumitomo Mitsubishi Silicon Corporation | High-resistance silicon wafer and process for producing the same |
| CN100397595C (en) * | 2003-02-14 | 2008-06-25 | 三菱住友硅晶株式会社 | Method for manufacturing silicon wafer |
| DE102007027111B4 (en) * | 2006-10-04 | 2011-12-08 | Siltronic Ag | Silicon wafer with good intrinsic gettering capability and process for its preparation |
| JP5572091B2 (en) | 2008-08-08 | 2014-08-13 | Ｓｕｍｃｏ Ｔｅｃｈｘｉｖ株式会社 | Manufacturing method of semiconductor wafer |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03184345A (en) * | 1989-12-13 | 1991-08-12 | Nippon Steel Corp | Silicon wafer and manufacture thereof |
-
1991
- 1991-11-22 JP JP3332779A patent/JP2770091B2/en not_active Expired - Lifetime
-
1992
- 1992-05-22 WO PCT/JP1992/000662 patent/WO1993010557A1/en active Application Filing
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05144827A (en) | 1993-06-11 |
| WO1993010557A1 (en) | 1993-05-27 |
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