JP2768121B2 - Multi-task processing system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multitask processing system, and more particularly, to a multitask processing system capable of reducing the overhead when swapping task programs in multitask processing.

[0002]

2. Description of the Related Art In a system having a disk device, how high-speed the data transfer between the main memory and the disk device and the load and overhead of the main processor and the system bus are reduced to improve the performance of the system. Occupies a large weight above.

For this reason, a dual port RA
For example, Japanese Patent Application Laid-Open No. 2-29845 proposes a memory access method in which the serial access memory unit is dedicated to DMA access using M and the random access memory unit is separately used for main processor access. According to this memory access method, the access of the main processor and the access of the DMA can be performed independently, so that the load and overhead of the system bus can be reduced.

[0004]

SUMMARY OF THE INVENTION The above-mentioned Japanese Patent Application Laid-Open No. 2-298 is disclosed.
In the memory access method proposed in Japanese Patent Publication No. 45, no consideration is given to the case of performing multitask processing. Therefore, there is a problem that the performance of the system is reduced due to the overhead when the task programs are swapped in the multitask processing.

An object of the present invention is to provide a multitask processing system capable of reducing the overhead when swapping task programs in multitask processing.

[0006]

Means for Solving the Problems] multitask processing system of the present invention, the main processor, and a dual-port port ram random port is connected to the main processor, disk connected to the serial port of the dual port port RAM Device and its disk device
Data transfer between the
And a data transfer controller for controlling the data transfer controller , wherein the memory cell portion of the dual port port ram is logically or physically divided into two or more banks, and the data transfer controller comprises:
Load the task program for multitasking from the disk device side one in through the serial port of the bank, executing the task program the main processor side is accessed through the random port in the task program And loading a task program for performing a multi-task process to be executed next from the disk device via the serial port to another bank during the operation. .

[0007]

[0008]

In the multitask processing system of the present invention, the memory cell section of the dual port RAM is divided into two or more banks, and the main processor accesses and executes the task program loaded in one bank via a random port. During this time, the disk device accesses another bank via the serial port and loads a task program to be executed next. That is, since the loading of the next task program can be performed in parallel during the execution of one task program, it is possible to reduce the overhead when the task programs are swapped in the multitask processing.

[0009]

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiment shown in FIG. It should be noted that the present invention is not limited by this.

FIG. 1 is a block diagram of a multitask processing system according to an embodiment of the present invention. 1 is a main processor that controls the entire system. 2 is a dual port RAM having a random port 9 and a serial port 10. 3 is a disk controller and 4 is a disk device. Reference numeral 5 denotes a data transfer controller having a sequence program necessary for performing data transfer between the dual port RAM 2 and the disk controller 3. 6 is a system bus.

The random port 9 of the dual port RAM 2 is connected to the main processor 1 via the system bus 6. The serial port 10 of the dual port RAM 2 is connected to the disk controller 3.

FIG. 2 is a block diagram of the dual port RAM 2. Reference numeral 7 denotes a memory cell unit that can be randomly accessed. The memory cell unit 7 is logically (or physically) divided into two banks A11 and B12. Reference numeral 8 denotes a data register 8 for performing serial transfer. The memory cell unit 7 is accessed from the main processor 1 via the system bus 6 and the random port 9, and is used as a main memory. Independently, the memory cell unit 7 is accessed from the disk device 4 via the data register 8, the serial port 10, and the disk controller 3.

Next, the operation when multitask processing is performed by the above system will be described. As shown in FIG. 3, the disk device 4 stores three task programs / data (task A13, task B14,
Task C15) is stored. When the system is started, the main processor 1 sends to the data transfer controller 5 information for loading the program / data of the task A13 to be executed first and information for loading the program / data of the task B14 to be executed next. Set and activate the data transfer controller 5. The data transfer controller 5 loads the task A13 from the disk device 4 to the bank A11. When the loading is completed, an internal completion flag is set.

As shown in FIG. 4, the main processor 1
Confirms that the completion flag is set, accesses the bank A11, and executes the task A13. At this time, the data transfer controller 5 loads the task B14 from the disk device 4 to the bank B12.
When the loading is completed, an internal completion flag is set.

As shown in FIG. 5, the main processor 1
Executes task A13 for a certain period of time, and then executes task A13
Interrupts the execution of. Then, task A in bank A11
The information for saving the program / data in the disk device 4 and the information for loading the program / data of the task C from the disk device 4 to the bank A11 are set in the data transfer controller 5 and activated.

As shown in FIG. 6, the main processor 1
Accesses the bank B12 and proceeds to the execution of the task B14. At this time, the data transfer controller 5 saves the program / data of the task A in the bank A11 to the disk device 4. As shown in FIG. 7, the data transfer controller 5 loads the program / data of the task C from the disk device 4 into the empty bank A11.

After executing the task B14 for a predetermined time, the main processor 1 suspends the execution of the task B14. Then, information for saving the program / data of the task B in the bank B12 to the disk device 4 and information for loading the program / data of the task A from the disk device 4 to the bank B12 are transferred to the data transfer controller 5.
And start.

As shown in FIG. 8, the main processor 1
Accesses the bank A11 and proceeds to the execution of the task C15. At this time, the data transfer controller 5 saves the program / data of the task B in the bank B12 to the disk device 4. Hereinafter, the above operation is repeated. FIG. 9 is a state diagram of the random port 9 and the serial port 10 in the above operation.

As described above, while a certain task is being executed, the previous task is saved, and the next task is loaded, so that the task switching time can be minimized. That is, overhead when swapping task programs can be reduced.

[0021]

[0022]

[0023]

[0024]

[0025]

According to the multitask processing system of the present invention, in the multitask processing, the memory swap time at the time of task switching apparently becomes almost zero, and the performance of the system can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram of a multitask processing system according to the present invention.

FIG. 2 is a block diagram of a dual port RAM.

FIG. 3 is an explanatory diagram of a program loading procedure in the system of FIG. 1;

FIG. 4 is an explanatory diagram of a program loading procedure in the system of FIG. 1;

FIG. 5 is an explanatory diagram of a program loading procedure in the system of FIG. 1;

FIG. 6 is an explanatory diagram of a program loading procedure in the system of FIG. 1;

FIG. 7 is an explanatory diagram of a program loading procedure in the system of FIG. 1;

FIG. 8 is an explanatory diagram of a program loading procedure in the system of FIG. 1;

FIG. 9 is a time chart illustrating states of a random port and a serial port.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Main processor 2 Dual port RAM 4 Disk device 9 Random port 10 Serial port 11 Memory bank A 12 Memory bank B 13 Task A 14 Task B 15 Task C

Claims (1)

(57) [Claims] 1. A main processor, a dual-port port ram random port is connected to the main processor, and a disk device connected to the serial port of the dual port port RAM, and the disk device
Controls data transfer between the dual port ports
A multi-task processing system having a data transfer controller , wherein a memory cell portion of the dual port port ram is logically or physically divided into two or more banks, and the data transfer controller
Wherein the one of the serial bank via the serial port to load a task program for multitasking from the disk apparatus, executes the task program by the main processor side access through the random port in the task program multi next task program for multitasking to execute is to b <br/> over de, it is characterized from the disk apparatus via the serial port to the other bank while you are Task processing system.