JP2765965B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor integrated circuit device,
In particular, it relates to an element isolation technique.

(Prior Art) In the past, element isolation of a semiconductor integrated circuit device was performed by a PN junction isolation method. However, as elements have been miniaturized and the degree of integration has been increased, a transition has been made to an oxide film isolation method (so-called isoplanar). Was. However, in recent years, the miniaturization of elements has been further advanced, and it has been necessary to further reduce the area of the isolation region for high integration. In addition, since it is necessary to reduce the parasitic capacitance for high-speed operation, it is becoming essential to reduce the area of the isolation region.

Recently, Reactive Ion Etching (RIE), an anisotropic etching technique for etching a film perpendicular to the substrate surface, has been put into practical use, and is a new alternative to oxide film separation. Device isolation methods have been developed. Among the new isolation technologies that have been proposed so far, a trench isolation method is one of the technologies that has attracted particular attention and is being put to practical use.

Hereinafter, a basic process of the trench isolation method will be described with reference to a process sectional view of FIG. 3 as a prior art.

First, as shown in FIG. 3A, a known selective oxidation method (LOCOS
Field silicon oxide film 202 is formed using Thereafter, a mask silicon oxide film 203 is formed on the entire surface by a CVD method, and an opening 205 is provided in the oxide films 203 and 202 in regions to be element isolation regions using a photoresist 204 as a mask using a known photolithography technique.

Next, as shown in FIG.
After removing 4, the silicon substrate 201 is etched almost vertically by RIE using the mask silicon oxide film 203 as a mask to form a groove 206.

Subsequently, as shown in FIG. 3 (C), after removing the mask silicon oxide film 203, an inner wall silicon oxide film 207 is formed on the entire surface by a thermal oxidation method or a CVD method. At this time, if necessary, an oxidation-resistant silicon nitride film may be further formed on the inner wall silicon oxide film 207.

Thereafter, as shown in FIG. 3 (D), a polycrystalline silicon layer 208 is thickly deposited on the entire surface, and a groove 206 (an opening 205 formed in the field silicon oxide film 202 is also considered as a part of the groove 206). ) Is completely backfilled.

Next, as shown in FIG. 3E, the polycrystalline silicon layer 208 is etched back by a known etching technique,
After the polycrystalline silicon layer 208 is left only in the inside, the surface of the polycrystalline silicon layer 208 is converted into a cap silicon oxide film 209, and the inner wall silicon oxide film 207 on the element forming region 201 is removed, thereby completing the separation step. .

Here, FIGS. 5A and 5B are cross-sectional views after the separation steps of the oxide film separation method and the trench separation method are completed. In the oxide film separation method (FIG. 5 (A)), the N ⁺ diffusion layer 302 as the buried diffusion layer and the P ⁺ diffusion layer 303 as the channel stopper are in direct contact, so that the junction capacitance therebetween is large. However, in the trench isolation method shown in FIG. 5B, a trench 305 is formed almost vertically to the silicon substrate 301 by RIE to a region deeper than the field oxide film 304 through the N ⁺ buried diffusion layer. ^{Since the +} diffusion layer 302 and the P ⁺ diffusion layer 303 do not directly contact each other, the junction capacitance is equal to the N ⁺ diffusion layer 302 as the buried diffusion layer.
It is only necessary to consider only the space between the substrate and the substrate 301. Therefore, the capacity is greatly reduced as compared with the oxide film separation method. As a result, a dramatic improvement in high speed can be obtained.

(Problems to be Solved by the Invention) However, the conventional trench isolation method described with reference to FIG. 3 has the following problems.

The conventional method shown in FIG. 3 has a structure in which a part of the field silicon oxide film 202 is interposed between the element forming region 210 and the groove 206 as shown in FIG. In the future, in order to further increase the speed, it is more important to reduce the capacitance between the collector and the substrate, and the structure shown in FIG. 4B in which the element forming region 210 and the groove 20 are in direct contact with each other is ideal. Conceivable.

However, since the position of the groove 206 is determined by mask alignment, it is necessary to consider an alignment deviation,
The structure shown in FIG. 4 (A) must be used. That is, in the case where the alignment margin is not added, if a deviation occurs, the silicon surface of the substrate is exposed in other than the element forming region 210 as shown in FIG. 4C, and a short circuit between the wiring metal layer and the substrate occurs. There is a problem. For this reason, the structure shown in FIG. 4 (A) must be adopted. However, as described above, the reduction of the collector-substrate capacitance is still insufficient.

Also, the current field silicon oxide film 202 and the groove 206
4B can be realized by reversing the formation order, in this case, oxidation proceeds in the vertical direction along the inner wall silicon oxide film 207 formed on the side wall of the groove 206. In addition, the generation of crystal defects due to an increase in volume poses a problem.

The present invention has been made in view of the above points, and in the trench isolation method, a structure in which an element formation region directly contacts a groove can be formed in a self-aligned manner. It is an object of the present invention to provide an excellent method for manufacturing a semiconductor integrated circuit device which greatly contributes to the development of a semiconductor device.

(Means for Solving the Problems) In this invention (first invention), the following manufacturing method is adopted. That is, a three-layer film including a first film as an oxide film, a second film as a polycrystalline semiconductor, and a third film as a nitride film is formed on the surface of the element formation region of the semiconductor substrate. Part 3
The exposed surface portion of the semiconductor substrate in the field region having no layer film is etched to form a recess having an undercut below the edge of the three-layer film, and at the same time, the edge of the second film in the three-layer film is receded. Then, the end of the first film positioned in an eaves shape on the undercut portion of the concave portion is removed, and only the end of the third film is positioned in an eaves shape on the undercut portion. Then, a fourth film, which is a nitride film, is formed on the side wall of the undercut portion, which is the end of the concave portion. Thereafter, a fifth film which is a field oxide film is formed in the concave portion by thermally oxidizing the concave bottom surface. A sixth film, which is a polycrystalline semiconductor, is formed on the fifth film except for the portion where the eave-like end of the third film is located. After that, the fourth film turned up on the third film and the fifth film is removed. The end of the fifth film exposed in this removing step is removed using the second and sixth films as a mask to form an opening. The semiconductor substrate portion exposed by the opening is etched to form a groove in the semiconductor substrate. An insulating film is formed on the groove and on the inner wall of the opening, the inside is filled with a polycrystalline semiconductor, and the insulating film is formed on the surface.

Further, in the second invention, the following manufacturing method is adopted. That is, a three-layer film including a first film as an oxide film, a second film as a polycrystalline semiconductor, and a third film as a nitride film is formed on the surface of the element region of the semiconductor substrate. A fourth film, which is a nitride film, is formed on the side wall. The exposed surface portion of the semiconductor substrate in the field region not having these films is etched to form a concave portion having an undercut under the fourth film. A fifth film, which is a nitride film, is formed on the side wall of the undercut portion below the fourth film, which is the end of the recess. Then, by thermally oxidizing the bottom of the recess,
A sixth film which is a field oxide film is formed in the recess. A seventh film, which is a polycrystalline semiconductor, is formed on the sixth film except for a portion where the fourth film is located. afterwards,
The third film, the fourth film, and the fifth film turned up on the sixth film are removed. The end of the sixth film exposed in this removing step is removed using the second and seventh films as masks to form openings. The semiconductor substrate portion exposed by the opening is etched to form a groove in the semiconductor substrate. An insulating film is formed on the groove and on the inner wall of the opening, the inside is filled with a polycrystalline semiconductor, and the insulating film is formed on the surface.

(Operation) In the present invention, as can be well understood in the examples described later, after a three-layer film is formed on a semiconductor substrate, the process is advanced by self-alignment, and a groove for element isolation is formed in the substrate by self-alignment. Is formed. Moreover, the groove is formed at the end of the field oxide film and is formed in contact with the element formation region. Further, in the second aspect of the present invention, the groove width is constant in accordance with the width of the fourth film formed on the side wall of the three-layer film, and the undercut portion when the concave portion is formed in the base is the fourth film. If it is within the width of the film, the width of the element formation region is constant irrespective of the etching amount when forming the concave portion. The element formation region width is determined by patterning when a three-layer film is first formed on a semiconductor substrate, and is constant.

Embodiment An embodiment of the present invention will be described below with reference to the drawings. First, a first embodiment of the present invention will be described with reference to FIGS. 1 (A) to 1 (K).

In the first embodiment, first, a field region is formed by applying a known improved selective oxidation method. Specifically,
As shown in FIG. 1A, a silicon oxide film 102 having a thickness of about 0.2 to 0.4 μm is formed on the entire surface of a silicon substrate 101 by a thermal oxidation method or a CVD method.
A polycrystalline silicon layer 103 having a thickness of about 1 to 0.2 μm is laminated.
Further, a silicon nitride film 104 having a thickness of about 0.4 to 0.7 μm is formed thereon by the CVD method. After that, as shown in FIG. 1 (B), the three-layered film is etched using a photoresist 105 as a mask by using a known photolithography technique, and is left only in the element formation region. Remove. At this time, by using anisotropic etching as an etching method, the side walls of the remaining three-layer film are made substantially vertical.

Next, the silicon substrate exposed by removing the three-layer film
The surface portion of 101 is isotropically etched by about 0.4 to 0.5 μm using
As shown in FIG. 3C, a concave portion 106 having an undercut below the edge of the three-layer film is formed in the substrate 101. At this time,
The polycrystalline silicon layer 103 is also partially etched, and the end of the polycrystalline silicon layer 103 recedes in the horizontal direction. Thereafter, the eaves-like end of the silicon oxide film 102 protruding above the undercut portion of the concave portion 106 is removed with a buffered hydrofluoric acid aqueous solution or the like as shown in FIG. 1 (D). As a result, the end of the silicon nitride film 104 only protrudes like an eave above the undercut portion of the recess 106.

Next, a silicon nitride film 1 having a thickness of about 0.05 to 0.1 μm
Form 07. Thereafter, the silicon nitride film 107 is etched using a known anisotropic etching technique, thereby forming the silicon nitride film 104 as shown in FIG.
Area under the eaves, specifically the underside of the eaves, and a recess
The silicon nitride film 107 is left only on the side wall of the undercut portion, which is the end of 106, and the silicon nitride film 107 is removed from all other portions.

Subsequently, the bottom surface (substrate surface) of the concave portion 106 is thermally oxidized using the silicon nitride film 104 and the silicon nitride film 107 as a mask, so that the concave portion 106 has a thickness of about 1.0 μm as shown in FIG.
An approximately thick field silicon oxide film 108 is formed.
At this time, the surface of the field silicon oxide film 108 is made to coincide with the upper surface of the silicon oxide film 102. Also, due to this field oxidation, the silicon nitride film 107 on the side wall of the undercut portion is turned up on the field silicon oxide film. The above is the step of forming the field region by applying the improved selective oxidation method.

Next, as shown in FIG. 1 (F), after a polycrystalline silicon layer 109 is laminated on the entire surface by a sputtering method so as not to enter the space between the silicon nitride films 104 and 107, a known fat film is formed. Using a lithography technique, a photoresist 110 is formed as a flattening dummy pattern on a portion of the polycrystalline silicon layer 109 having a low step. The mask alignment here does not require strict accuracy. Next, a photoresist 111 is applied on the entire surface to planarize the surface.

Thereafter, the etch-back of the photoresists 111 and 110 and the polycrystalline silicon layer 109 is performed by a known constant-speed etching technique in which the etching rates of the photoresists 111 and 110 and the polycrystalline silicon layer 109 are equal, and the surface of the silicon nitride film 104 is exposed. Do it until you do. Thereby, FIG. 1 (G)
As shown in FIG.
The part of the field silicon oxide film that does not have 04 on the surface
It will only remain on 108 surfaces. Thereafter, the residues of the photoresists 110 and 111 are completely removed. The etching at the time of the etch back may be isotropic.

Subsequently, as shown in FIG. 1H, all of the silicon nitride films 104 and 107 are removed by a known isotropic etching technique. Then, the end of the field silicon oxide film 108 exposed by removing the silicon nitride film is
Using the polycrystalline silicon layers 103 and 109 as a mask, the side walls are removed by anisotropic etching so as to be substantially vertical as shown in FIG.

Next, anisotropic etching is performed on the silicon substrate 101 where the opening 112 is exposed, and as shown in FIG. 1 (I), a groove 11 having a depth of about 2 to 4 μm and a substantially vertical sidewall.
Form 3. At this time, the polysilicon layers 103 and 109
Are removed together, and the silicon oxide film 102 and the field silicon oxide film 108 are exposed. After the silicon oxide film 102 and the field silicon oxide film 108 are exposed, the silicon oxide film 102 and the field silicon oxide film 108 serve as a mask, and the formation of the groove 113 proceeds.

After that, after the silicon oxide film 102 is removed by anisotropic etching, as shown in FIG. 1 (J), the entire surface including the inner wall 113 (the opening 112 is also considered as a part of the groove 113) is formed by the CVD method as shown in FIG. A silicon oxide film 114 is formed, and C
The polycrystalline silicon layer 115 is thickly deposited on the whole surface by the VD method, and the 113 is completely buried.

Finally, as shown in FIG. 1 (K), the polycrystalline silicon layer 115 is etched back by a known etching technique,
This polycrystalline silicon layer 115 is left only in the groove 113, and its surface is converted into a silicon oxide film 116.

As described above, a trench isolation structure in which the element formation region 117 is in contact with the groove 113 and the surface is flat can be realized by self-joining.

FIG. 2 shows a second embodiment of the present invention. In the second embodiment, in addition to realizing the structure where the element formation region and the groove are in contact with each other by self-alignment, the width of the groove is constant, and the element formation region is formed regardless of the etching amount when forming the concave portion on the substrate. The width can be made constant. The details will be described below.

In the second embodiment, as shown in FIG. 2A, a silicon oxide film 102 and a polycrystalline silicon layer are formed on an element formation region of a silicon substrate 101 in exactly the same manner as in the first embodiment.
103, a pattern of a three-layer film of silicon nitride film 104 is formed,
The three-layer film is removed from a portion to be a field region.

Next, after removing the photoresist 105 used for forming the pattern of the three-layer film, a silicon nitride film 1 is formed on the entire surface.
The silicon nitride film 121 is formed by etching the silicon nitride film 121 by anisotropic etching.
1 is left only on the side walls of the three-layer film as shown in FIG. 2 (B). The width of the remaining silicon nitride film 121 is equal to the width of a groove to be formed in a later step and is constant.

Next, the exposed surface portion of the silicon substrate 101 which does not have the silicon nitride film 121 and the three-layer film on the surface isotropically.
By etching about 0.4 to 0.5 μm, a recess 106 having an undercut under the silicon nitride film 121 is formed in the substrate 101 as shown in FIG. 2C. At this time,
Control is performed so that the undercut portion of the concave portion 106 is within the width of the silicon nitride film 121. This control is combined with the fact that the above-described groove width becomes equal to the width of the silicon nitride film 121 and becomes constant. Therefore, the width of the element formation region is constant irrespective of the etching amount when forming the concave portion 106. That is,
The width of the element formation region is determined by the photoresist 105 in FIG.
And the part where the three-layer film remains becomes an element formation region accurately.

Next, if necessary, thermal oxidation is performed on the exposed substrate surface to form an oxide film (not shown) having a thickness of 0.05 to 0.15 μm. Then, as shown in FIG. The silicon nitride film 107 is formed on the side wall of the undercut portion below the silicon nitride film 121 in exactly the same manner as in the first embodiment.

Thereafter, formation of a field silicon oxide film 108 in the recess 106 (FIG. 2D), formation of the polycrystalline silicon layer 103, formation of photoresists 110 and 111 (FIG. 2E), and etch back (FIG. 2) (F)) is performed in exactly the same manner as in the first embodiment, and the polycrystalline silicon layer 109 is left on the surface of the field silicon oxide film 108 where the silicon nitride film 121 does not have an upper portion.

Next, after removing the silicon nitride films 104, 121 and 107 by a known isotropic etching technique as shown in FIG. 2 (G), the field exposed in the silicon nitride film removing step is removed as in the first embodiment. The end of the silicon oxide film 108 is removed by anisotropic etching as shown in FIG. 2 (G), an opening 112 is formed, and the silicon substrate 101 where the opening 112 is exposed is removed. Anisotropic etching is performed in the same manner as in the first embodiment, and as shown in FIG.
Form 3. Further, after removing the silicon oxide film 102 by anisotropic etching, a silicon oxide film 114 is formed on the entire surface including the inner wall of the groove 113 by the CVD method as shown in FIG. Formed in this case, followed by CVD in this case.
After a silicon nitride film 122 is formed on the entire surface by the method, a polycrystalline silicon layer 115 is buried in the groove 113 as in the first embodiment, and the surface is converted to a silicon oxide film 116.

(Effects of the Invention) As described above in detail, according to the manufacturing method of the present invention, a three-layer film including an oxide film, a polycrystalline semiconductor, and a nitride film is formed on an element forming region of a semiconductor substrate. A recess having an undercut is formed in the field region of the semiconductor substrate below the end of the three-layer film or below the nitride film formed on the side wall of the three-layer film, and the side wall of the undercut, which is the end of the recess, is nitrided. After covering with the film, a fiolded oxide film is formed in the concave portion, and at the end of the field oxide film, the remaining nitride film is used as a groove forming region, and the remaining nitride film is removed. Using the semiconductor layer as a mask, the end of the field oxide film is etched away to form an opening of the groove, and the substrate is etched from the opening to form the groove. The trench can be formed at the end of the oxide film, and the groove can be in contact with the element formation region.

In addition, according to the method of forming a nitride film on the side wall of the three-layer film, the groove width also becomes constant in accordance with the width of the nitride film on the side wall of the three-layer film. If it is within the width of the nitride film, the width of the element formation region can be made constant irrespective of the etching amount when forming the concave portion.

Therefore, by adopting the manufacturing method of the present invention, the minimum value of the parasitic capacitance between the collector and the substrate can be obtained, and the high-speed operation of the element can be remarkably improved, and also the integration degree can be improved. A trench isolation structure having a constant element formation region width and a constant groove width can be obtained with good reproducibility.

Further, according to the present invention, since the groove is formed after the formation of the fiold oxide film, the vertical oxidation of the groove proceeds as in the case where the groove is reversed, and a crystal defect accompanying a volume increase occurs. There is an advantage that there is no such thing.

[Brief description of the drawings]

FIG. 1 is a process sectional view showing a first embodiment of a method of manufacturing a semiconductor integrated circuit device according to the present invention, and FIG.
3 is a sectional view showing a conventional trench isolation method, FIG. 4 is a sectional view showing a problem of the conventional trench isolation method, and FIG. 5 is a sectional view showing an oxide film isolation method. FIG. 6 is a cross-sectional view of the device after an isolation step of a trench isolation method is completed. 101 ... silicon substrate, 102 ... silicon oxide film, 103 ...
... polycrystalline silicon layer, 104 ... silicon nitride film, 105 ...
Photoresist, 106 recess, 107 silicon nitride film, 108 field silicon oxide film, 109 polycrystalline silicon layer, 110, 111 photoresist, 112 opening, 113 groove, 114 ... silicon oxide film, 115 ... polycrystalline silicon layer, 116 ... silicon oxide film, 117 ... element formation region, 121, 122 ... silicon nitride film.

Claims (2)

(57) [Claims] (A) forming a three-layer film including a first film as an oxide film, a second film as a polycrystalline semiconductor, and a third film as a nitride film on a surface of an element forming region of a semiconductor substrate; (B) etching the exposed surface of the semiconductor substrate in the field region not having the three-layer film to form a concave portion having an undercut below the end of the three-layer film, and (C) removing the end of the first film which is positioned in an eaves on the undercut portion of the concave portion, and removing the end portion of the first film on the undercut portion. (D) forming a fourth film, which is a nitride film, on the side wall of the undercut portion, which is the end of the concave portion, after only the end of the film of No. 3 is positioned in an eaves shape; Then, the bottom surface of the concave portion is thermally oxidized, so that a field oxide film is formed in the concave portion. Forming a fifth film; and (e) forming a sixth film of a polycrystalline semiconductor on the fifth film except for a portion where the eaves-like end of the third film is located. (F) removing the fourth film that has been turned up over the third film and the fifth film, and (g) removing the fifth film exposed by the removing step. Forming an opening by removing an end portion using the second and sixth films as a mask; and (h) forming a groove in the semiconductor substrate by etching a portion of the semiconductor substrate exposed through the opening. (I) forming an insulating film on the inner wall of the groove and the opening, filling the inside with a polycrystalline semiconductor, and forming an insulating film on the surface of the insulating film. Method. And (a) forming a three-layer film including a first film as an oxide film, a second film as a polycrystalline semiconductor, and a third film as a nitride film on the surface of an element formation region of a semiconductor substrate. (B) forming a fourth film, which is a nitride film, on the side walls of the three-layer film; and (c) etching the exposed surface of the semiconductor substrate in a field region having no such film. Forming a recess having an undercut under the fourth film; and (d) forming a nitride film on a side wall of the undercut portion under the fourth film, which is an end of the recess. Forming a film; (e) subsequently thermally oxidizing the bottom surface of the concave portion to form a sixth film which is a field oxide film in the concave portion; and (f) forming the sixth film on the sixth film. Forming a seventh film which is a polycrystalline semiconductor except for a portion where the fourth film is located; (G) a step of removing the third film, the fourth film, and the fifth film that has turned up on the sixth film; and (h) an end of the sixth film exposed by the removing step. Removing the portion using the second and seventh films as a mask to form an opening; and (i) etching a portion of the semiconductor substrate exposed by the opening to form a groove in the semiconductor substrate; (J) forming an insulating film on the inner wall of the groove and the opening, filling the inside thereof with a polycrystalline semiconductor, and further forming an insulating film on the surface thereof. .