JP3783308B2 - Semiconductor device manufacturing method and semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention particularly relates to a method of manufacturing a semiconductor device having an element isolation region that can reduce the parasitic capacitance of the element, and the semiconductor device .
[0002]
[Prior art]
FIG. 10A is a cross-sectional view showing an element isolation method for a conventional semiconductor device, and FIG. 10B is a cross-sectional view showing another element isolation method for a semiconductor device.
[0003]
2. Description of the Related Art Conventionally, well-known methods for isolating semiconductor devices using an insulating film are roughly divided into two. One of them is the trench element isolation shown in FIG. 10A, in which a trench is dug in the semiconductor substrate in the element isolation region to fill the insulating film, and the insulating film in the active region is removed by a chemical mechanical polishing method such as CMP. The other is a LOCOS isolation method shown in FIG. 10B, in which an active region of a transistor is covered with an oxidation-resistant insulating film, and an oxide insulating film is grown in the isolation region, and an improved method thereof .
[0004]
That is, the isolation method of the conventional semiconductor device, as shown in FIG. 10 (a), trenches are formed in element isolation regions in the silicon substrate 101 was deposited an insulating film on the trench and the silicon substrate 101 Thereafter, the element isolation insulating film 103 is formed by removing the insulating film existing in the element region, and the gate electrode 105, the diffusion layer 107 of the source / drain region, and the sidewall 109 are formed on the silicon substrate 101. A MOS transistor is formed in the active region of the transistor.
[0005]
Further, the isolation method of another conventional semiconductor device, as shown in FIG. 10 (b), the isolation region on the silicon substrate 101, after forming the LOCOS oxide film 111 by LOCOS isolation method, the silicon substrate 101 The MOS transistor is formed in the active region of the transistor by forming the gate electrode 105, the diffusion layer 107 in the source / drain region, and the sidewall 109.
[0006]
[Problems to be solved by the invention]
Incidentally, in the conventional well-known isolation methods described above, in the cross-sectional shape of the active region and the element isolation region of the transistor, b of the simple linear or FIG. 10 (b) in shown in a in FIG. 10 (a) When the source / drain region of the MOS transistor or the base region of the bipolar transistor is formed by forming a diffusion layer in the active region of the transistor having the boundary indicated by the curve shown in FIG. The parasitic capacitance is a value determined by the area of the opening (area of the element region) and the perimeter on the plan view.
[0007]
Particularly parasitic capacitance, the gate length, whereas such oxide film thickness is proportionally reduced, mainly contact hole formation or difficulty of forming a metal line in the upper layer Recent miniaturization of the case of the MOS type transistor not shrink in the same proportion by. For this reason, the ratio of drain parasitic capacitance to the load capacitance of the transistor is increased, which is an impediment to increasing the speed of the device and reducing power consumption.
[0008]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device capable of reducing the parasitic capacitance of an element and a method for manufacturing the same.
[0009]
[Means for Solving the Problems]
In order to solve the above problems, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a polishing stopper film on a semiconductor substrate, and an opening for forming a groove in the polishing stopper film. Forming a groove having a convex cross-sectional shape having a groove width larger than the opening formed in the polishing stopper film on the semiconductor substrate; forming an insulating film so as to fill the groove; The insulating film on the polishing stopper is removed and planarized while leaving the insulating film in the groove by a mechanical mechanical polishing method, and an element isolation region having a convex cross-sectional shape is formed in the groove as well as the steps of forming an active region having an inverted convex shape in cross section consisting of the semiconductor substrate, a step of exposing the semiconductor substrate by removing the polishing stopper film, The serial active region, characterized by comprising a step of forming a MOS transistor part of the side and bottom of at least the drain region is in contact with the element isolation region.
[0010]
In this method for manufacturing a semiconductor device, an element isolation region having a convex cross-sectional shape can be formed on a semiconductor substrate, and an active region having a reverse convex cross-sectional shape can be formed on a semiconductor substrate. Since forming the diffusion layers of the source and drain regions of the MOS transistor in the active region of the semiconductor substrate obtained in this way, since a small area and perimeter that contacts the semiconductor substrate directly, parasitic diffusion layer The capacity can be reduced. Accordingly, it is possible to realize a high-speed element and low power consumption.
[00 11 ]
The semiconductor device according to the present invention is a semiconductor device in which a MOS transistor is formed in an active region isolated by an element isolation region formed in a semiconductor substrate, wherein the element isolation region and the active region are the semiconductor A step of forming a polishing stopper film on the substrate, and after forming an opening for forming a groove in the polishing stopper film, the groove width is made larger than the opening formed in the polishing stopper film on the semiconductor substrate. Forming a groove having a convex cross-sectional shape formed;
Forming an insulating film so as to fill the groove, and removing and planarizing the insulating film on the polishing stopper while leaving the insulating film in the groove by a chemical mechanical polishing method. Forming a device isolation region having a convex cross-sectional shape in the groove, forming an active region having a reverse convex cross-sectional shape made of the semiconductor substrate, and removing the polishing stopper film. The MOS transistor is formed in the active region so that at least a part of the side and bottom of the drain region are in contact with the element isolation region. It is characterized by.
[00 12 ]
In this semiconductor device, since a part of the sides and bottom of at least the drain region is formed in contact with the element isolation region can reduce the parasitic capacitance of the device.
[00 13 ]
DETAILED DESCRIPTION OF THE INVENTION
Method of manufacturing a semiconductor device of the present invention is an type of trench isolation methods, have I lifting characteristic unprecedented. That is , the present invention intends to reduce the parasitic capacitance between the drain and the substrate of the MOS transistor or the parasitic capacitance between the base and the collector of the bipolar transistor, which is difficult to reduce by the conventional element isolation method. Was invented.
[00 14 ]
An embodiment of the present invention will be described below with reference to the drawings.
1 to 8 are sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 1 is a cross-sectional view showing the semiconductor device of the present invention.
[00 15 ]
First, as shown in FIG. 2, a thin pad oxide film 2 is grown on the surface of a semiconductor substrate (silicon substrate) 1. Next, on this pad oxide film 2, an insulating film 3 which becomes a stopper at the time of CMP and is a polishing stopper film different from the oxide film is formed by , for example, silicon nitride by a CVD (chemical vapor deposition) method. It formed by growing a ride. Thereafter, a photoresist film 4 is provided on the insulating film 3 exposed only on the element isolation region by a normal exposure technique, and the insulating film 3, the pad oxide film 2 and the semiconductor are formed using the photoresist film 4 as a mask. The substrate 1 is etched by RIE (Reactive Ion Etching). Thus, the insulating film 3 opening 5 is provided in the semiconductor substrate 1 portion of the groove to a predetermined depth is formed. Specifically, the etching depth of the semiconductor substrate 1 corresponds to the depth of a diffusion layer of a MOS transistor described later.
[00 16 ]
Thereafter, the photoresist film 4 is peeled off. Next, as shown in FIG. 3, an oxide insulating (SiO ₂ ) film is formed on the insulating film 3 and the semiconductor substrate 1 by the CVD method. Thereafter, the entire surface of the oxide insulating film is etched back to form sidewalls 6 made of the oxide insulating film on the side walls of the openings 5 of the insulating film 3 . Next, the semiconductor substrate 1 is etched using the sidewall 6 and the insulating film 3 as a mask, whereby a groove 7 a is formed in the semiconductor substrate 1.
[00 17 ]
Next, as shown in FIG. 4, by using an isotropic dry etching technique, the semiconductor substrate 1 is etched using the insulating film 3 as a mask, thereby reducing the groove width of the groove 7 to the opening 5 of the insulating film. the size Kushida to form a new groove 7 on the semiconductor substrate 1 than.
[00 18 ]
Thereafter, as shown in FIG. 5, an oxide film 8 a is grown on the bottom and side walls of the trench 7 until the width of the trench 7 becomes the same width 5 a as that between the sidewalls 6.
[00 19 ]
Next, as shown in FIG. 6, the trench 7 is backfilled with the insulating oxide film 8b by bias ECR or LPCVD (trench element isolation method). In other words, among the rest of the groove 7 (the portion surrounded by the oxide film 8a), depositing an insulating oxide film 8 b mutual sidewall 6 Kikioyobi on the insulating film 3.
[00 20 ]
Thereafter, as shown in FIG. 7, chemical mechanical polishing is performed until the insulating film 3 on the element formation region is exposed. In other words, the insulating oxide film 8b is subjected to chemical mechanical polishing using the insulating film 3 as a polishing stopper.
[00 21 ]
Next, as shown in FIG. 8, the surface of the semiconductor substrate 1 is exposed by removing the insulating film 3 and the pad oxide film 2 remaining after the polishing. Accordingly, region formed by the oxide film 8a and the insulating oxide film 8 b having a convex cross-sectional shape constitutes an element isolation region 8, the area active region having a reverse convex cross-sectional shape of the semiconductor substrate 1 (Active region) 9 is formed. The surface height of the active region 9 is lower than the surface height of the element isolation region 8.
[00 22 ]
Thereafter, as shown in FIG. 9, the gate electrode 10 of the MOS transistor, the LDD sidewall 11, the source / drain region are formed on the active region 9 in the semiconductor substrate 1 by using known exposure, CVD, ion implantation, RTA technique, or the like. The diffusion layer 12 is formed. At this time, the diffusion layer in the drain region is formed so that at least a part of the side and bottom thereof is in contact with the element isolation region 8.
[00 23 ]
Next, as shown in FIG. 1, an insulating film 13 is deposited on the surface of the MOS transistor, a window for wiring extraction is formed in the insulating film 13, and the metal wiring layer 14 is sputtered and then patterned. After that, an insulating film (protective film) 15 for surface protection is deposited on the metal wiring layer 14 and the insulating film 13, and an opening window for external end connection (bonding) (not shown) is opened to provide the semiconductor of the present invention. The device is completed.
[00 24 ]
According to the above embodiment, the cross-sectional shape of the element isolation region 8 is formed in a convex shape, the cross-sectional shape of the active region 9 is formed in a reverse convex shape, and a MOS transistor is formed in the active region 9. In the MOS transistor having such a structure, the cross-sectional shape of the diffusion layer is reverse convex, that is, the source / drain region 12 is formed on the step portion of the convex element isolation region 8. In other words, the diffusion layer in the drain region is formed so that at least a part of the side and bottom thereof is in contact with the element isolation region 8. Therefore, the junction area between the source / drain region 12 and the lower semiconductor substrate 1 can be reduced, and the drain parasitic capacitance can be reduced.
[00 25 ]
In other words, when the diffusion layer 12 of the source / drain region of the MOS transistor is formed in the active region 9 having the reverse convex cross-sectional shape, the parasitic capacitance of the diffusion layer has a small area and a peripheral length in direct contact with the semiconductor substrate. Can be small. Therefore, it is possible to realize a high speed of the device, low power consumption.
[00 26 ]
From another viewpoint, the planar size of the diffusion layer built into the semiconductor substrate 1 and the connection window interval for connection to the upper wiring layer 14 can be separately defined, and each can be optimized. It is also considered that the drain parasitic capacitance can be reduced as a design example of the optimization.
[00 27 ]
In the above embodiment, as shown in FIGS. 5 and 6, the oxide film 8 a is formed on the bottom and side walls of the trench 7 until the width of the trench 7 becomes the same width 5 a as that between the sidewalls 6. The trench 7 is backfilled with the insulating oxide film 8b , and the bottom of the trench 7 and the trench 7 until the width of the trench 7 is smaller than the width of the opening 5 of the insulating film 3 and wider than the width 5a. After growing the oxide film 8a on the side wall, the oxide film 8a is etched back by anisotropic RIE until it becomes the same width as the width of the opening 5, and the groove 7 is filled with the insulating oxide film 8b. Is also possible. In this way, by growing the oxide film 8a on the bottom and side walls of the groove 7 so that the groove 7 has the same width as the opening 5, the groove 7 is insulatively oxidized by the bias ECR in the next process. The aspect at the time of backfilling with the film 8b can be improved and the margin of the process can be increased.
[00 28 ]
Further, if it is assumed that the etching back is performed to the size of the initial opening (opening of the insulating film 3) 5 as described above, the oxide film 8a grown on the bottom and side walls of the trench 7 shown in FIG. The degree of freedom of the process is further increased, as long as the width (cavity) 5a is not as small as that between the sidewalls 6, but the cavity (width) is smaller than the size of the initial opening 5. Specifically, the method for growing the oxide film 8a can be either thermal oxidation or CVD.
[00 29 ]
【The invention's effect】
According to the invention described above, by forming a larger groove than the opening of the insulating film serving as a polishing stopper in the semiconductor substrate, forming an active region having an inverted convex shape in cross section, in the active region since the portion of the side and bottom of at least the drain region forms a MOS-type transistor, such as contact with the element isolation region, it is possible to provide a method of manufacturing a semiconductor device capable of reducing the parasitic capacitance of the element.
[Brief description of the drawings]
1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention and a method for manufacturing the semiconductor device showing the next step of FIG. 9 ;
FIG. 2 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the embodiment of the present invention and showing a step subsequent to FIG. 2;
FIG. 4 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the embodiment of the present invention and showing a step subsequent to FIG. 3;
FIG. 5 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the embodiment of the present invention and illustrating the next step of FIG. 4;
FIG. 6 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the embodiment of the present invention and showing a step subsequent to FIG. 5;
7 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the embodiment of the present invention, and showing a step subsequent to FIG. 6. FIG.
FIG. 8 is a cross-sectional view showing the next step of FIG. 7 in the method for manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 9 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention, and illustrating the next step of FIG. 8;
FIG. 10A is a cross-sectional view showing an element isolation method for a conventional semiconductor device, and FIG. 10B is a cross-sectional view showing another element isolation method for a semiconductor device.
[Explanation of symbols]
1 ... semiconductor substrate, 2 ... pad oxide film, 3: insulating film, 4 ... photoresist film, 5 ... opening of the insulating film, 5a ... sidewall inter and as wide, 6 ... side wall, 7, 7a ... trench, 8 ... element isolation region , 8a ... oxide film, 8b ... insulating oxide film, 9 ... active region, 10 ... gate electrode, 11 ... LDD sidewall , 12 ... diffusion layer of source / drain region, 13 ... Insulating film, 14 ... Metal wiring layer, 15 ... Insulating film , 101 ... Silicon substrate, 103 ... Element isolation insulating film, 105 ... Gate electrode, 107 ... Diffusion layer of source / drain region, 109 ... Side wall , 111 ... LOCOS oxidation Membrane, a ... active element and element separation boundary indicated by simple line, b ... active element and element separation boundary indicated by curve.

Claims (4)

Forming a polishing stopper film on the semiconductor substrate;
After forming an opening for forming a groove in the polishing stopper film, a groove having a convex cross-sectional shape in which the groove width is formed larger than the opening formed in the polishing stopper film is formed in the semiconductor substrate. And the process of
Forming an insulating film so as to fill the groove;
An element isolation region having a convex cross-sectional shape is formed in the groove by removing and planarizing the insulating film on the polishing stopper while leaving the insulating film in the groove by a chemical mechanical polishing method. Forming an active region having a reverse convex cross-sectional shape made of the semiconductor substrate, and
Exposing the semiconductor substrate by removing the polishing stopper film;
Above active region, and forming a MOS transistor part of the side and bottom of at least the drain region is in contact with the element isolation region,
A method for manufacturing a semiconductor device, comprising: The step of forming the insulating film so as to fill the groove includes
  After the oxide film is grown so that the widened portion of the groove becomes the width of the opening of the groove or narrower than that, the insulating film is embedded.
  The method of manufacturing a semiconductor device according to claim 1. A semiconductor device in which a MOS transistor is formed in an active region separated by an element isolation region formed in a semiconductor substrate,
  The element isolation region and the active region are:
  Forming a polishing stopper film on the semiconductor substrate;
  After forming an opening for forming a groove in the polishing stopper film, a groove having a convex cross-sectional shape in which the groove width is formed larger than the opening formed in the polishing stopper film is formed in the semiconductor substrate. And a process of
  Forming an insulating film so as to fill the groove;
  An element isolation having a convex cross-sectional shape in the groove by removing and flattening the insulating film on the polishing stopper while leaving the insulating film in the groove by a chemical mechanical polishing method Forming a region and forming an active region having a reverse convex cross-sectional shape made of the semiconductor substrate;
  Exposing the semiconductor substrate by removing the polishing stopper film;
  Formed by doing
  The MOS transistor is
  The active region is formed such that at least a part of the side and bottom of the drain region is in contact with the element isolation region.
  A semiconductor device. The step of forming the insulating film so as to fill the groove includes
  After the oxide film is grown so that the widened portion of the groove becomes the width of the opening of the groove or narrower than that, the insulating film is embedded.
  The semiconductor device according to claim 3.

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