JP2752148B2 - Wafer exposure method - Google Patents

Wafer exposure method

Info

Publication number
JP2752148B2
JP2752148B2 JP1100858A JP10085889A JP2752148B2 JP 2752148 B2 JP2752148 B2 JP 2752148B2 JP 1100858 A JP1100858 A JP 1100858A JP 10085889 A JP10085889 A JP 10085889A JP 2752148 B2 JP2752148 B2 JP 2752148B2
Authority
JP
Japan
Prior art keywords
wafer
exposing
peripheral portion
resist film
periphery
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP1100858A
Other languages
Japanese (ja)
Other versions
JPH02278814A (en
Inventor
一男 島根
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1100858A priority Critical patent/JP2752148B2/en
Publication of JPH02278814A publication Critical patent/JPH02278814A/en
Application granted granted Critical
Publication of JP2752148B2 publication Critical patent/JP2752148B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】 〔概要〕 ウエハの露光方法に係り,特にウエハ周縁部の露光方
法に関し, 周縁露光位置を正確に決めて1枚のウエハからとれる
チップ数を大きくすると共に,ウエハ上のチップの位置
を確定することを目的とし, 全面にレジスト膜の形成されたウエハ上の領域を分割
し、分割された領域ごとに露光するウエハの露光方法に
おいて、最小の露光領域となる単位矩形を網目とする仮
想網をウエハの全面に掛けたときに、 1.ウエハの周縁部と重なる網目を周縁部の全周にわた
って露光し、ウエハの周縁部のレジスト膜を除去した
後、レジスト膜が残されたチップ形成領域の露光を行う
ウエハの露光方法と、 2.ウエハのほぼ中心を通る仮想網の直交する2本の仮
想糸がウエハの周縁部と交叉する点を位置確認点とし、
位置確認点の両側の網目以外で、ウエハの周縁部と重な
る網目を周縁部の全周にわたって露光し、位置確認点の
両側は未露光領域を設けるように隙間を空けて露光し、
ウエハの周縁部のレジスト膜を除去した後、レジスト膜
が残されたチップ形成領域の露光を行うウエハの露光方
法とによって構成する。
DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to an exposure method for a wafer, and particularly to an exposure method for a peripheral portion of a wafer. In order to determine the position of the chip, the area on the wafer where the resist film is formed over the entire surface is divided, and in a wafer exposure method that exposes each divided area, a unit rectangle that is the minimum exposure area is When a virtual net as a mesh is applied to the entire surface of the wafer, 1.A mesh overlapping the peripheral portion of the wafer is exposed over the entire peripheral portion, and after the resist film on the peripheral portion of the wafer is removed, the resist film remains. A method of exposing a wafer for exposing the formed chip forming area; and 2. a point at which two orthogonal virtual threads of a virtual net passing substantially at the center of the wafer intersect with the peripheral edge of the wafer,
Except for the mesh on both sides of the position confirmation point, a mesh overlapping with the periphery of the wafer is exposed over the entire periphery of the periphery, and both sides of the position confirmation point are exposed with a gap so as to provide an unexposed area,
After the resist film on the peripheral portion of the wafer is removed, the wafer is exposed by exposing the chip formation region where the resist film remains.

〔産業上の利用分野〕[Industrial applications]

本発明はウエハの露光方法に係り,特にウエハ周縁部
の露光方法に関する。
The present invention relates to a method for exposing a wafer, and more particularly, to a method for exposing a wafer peripheral portion.

半導体のフォト工程においては,ウエハ全面にレジス
ト膜を形成した後でウエハ周縁部のレジストを除いてお
く必要がある。レジストの塗膜は通常ウエハ周縁部で厚
くなり,その後の工程でその一部が剥離したりすること
がある。また,ウエハをキャリアに収納する時ウエハ周
縁部がキャリアの溝と接触し,その部分のレジストが剥
離したりする。剥離したレジストはごみとなって,その
後の工程に支障を来す。そういう理由からウエハ全面に
レジスト膜を形成した後でウエハ周縁部のレジストを除
くことが行われる。
In the semiconductor photo process, it is necessary to remove the resist at the peripheral portion of the wafer after forming a resist film on the entire surface of the wafer. The resist coating film usually becomes thicker at the periphery of the wafer, and a part of the resist film may be peeled off in a subsequent process. In addition, when the wafer is stored in the carrier, the peripheral edge of the wafer comes into contact with the groove of the carrier, and the resist at that portion is peeled off. The stripped resist becomes dust and hinders subsequent processes. For this reason, after the resist film is formed on the entire surface of the wafer, the resist on the peripheral portion of the wafer is removed.

しかも,集積回路の製造では,ウエハ周縁部のレジス
トの除去する領域を必要最小限におさえて1枚のウエハ
からとれるチップ数を大きくすることも要求される。
In addition, in the manufacture of integrated circuits, it is also required to increase the number of chips that can be obtained from one wafer while minimizing the area of the peripheral edge of the wafer from which the resist is removed.

さらに,素子形成を終えた大量のチップが配置されて
いるウエハからチップを取ってダイパッドにボンディン
グする際,チップの取り違え等を防止することも要求さ
れている。
In addition, when chips are taken from a wafer on which a large number of chips on which elements have been formed are arranged and bonded to die pads, it is also required to prevent chips from being mixed up.

〔従来の技術〕[Conventional technology]

従来,ウエハ周縁部のレジストを除去する方法の一つ
として,第5図の従来例Iに示すような方法がある。第
5図において,1は全面にレジスト膜の形成されたウエ
ハ,61はウエハステージ,62は回転用モータ,63は台,66は
露光装置の一部をなす光学レンズ系を表す。
Conventionally, as one of the methods for removing the resist at the peripheral portion of the wafer, there is a method as shown in a conventional example I in FIG. In FIG. 5, reference numeral 1 denotes a wafer having a resist film formed on the entire surface, 61 denotes a wafer stage, 62 denotes a rotation motor, 63 denotes a table, and 66 denotes an optical lens system forming a part of an exposure apparatus.

この方法では,ほぼ円形のウエハ1を中心軸の周りに
回転させることにより,ウエハ周縁部からのある幅を光
学レンズ系66により露光することにより,ウエハ周縁部
のレジストを除去する。ところが,ウエハの寸法にばら
つきがあること,ウエハから将来取るべきチップの形状
は四角形であること等の理由から,ウエハの位置設定の
精度が悪いと,後の工程でウエハ周縁部に近いチップに
不良が生じたり,ウエハ上のチップの位置が正確に定ま
らないといった問題があった。
In this method, the resist on the wafer peripheral portion is removed by rotating the substantially circular wafer 1 around the central axis and exposing a certain width from the wafer peripheral portion by the optical lens system 66. However, if the accuracy of the wafer position setting is poor due to variations in the dimensions of the wafer and the shape of the chip to be taken from the wafer in the future in the future, the chip near the wafer edge in the subsequent process There have been problems such as the occurrence of defects and the inaccurate determination of chip positions on the wafer.

また,ウエハの周縁位置を自動的に検出しながらウエ
ハ周縁部から一定の幅を露光する露光装置もある。第6
図の従来例IIはこれを説明するための図で,1は全面にレ
ジスト膜の形成されたウエハ,61はウエハステージ,62は
回転用モータ,63は台,66は露光装置の一部をなす光学レ
ンズ系,67は発光系,68は受光系,81は移動ステージを表
す。
There is also an exposure apparatus that exposes a fixed width from the wafer peripheral portion while automatically detecting the peripheral position of the wafer. Sixth
Conventional example II in the figure is a diagram for explaining this. An optical lens system, 67 is a light emitting system, 68 is a light receiving system, and 81 is a moving stage.

この装置は,ウエハの形状が円形から若干はずれた場
合,受光系68に入る光量が変化し,その変化量を移動ス
テージ81にフィードバックして移動ステージ81を動か
し,常にウエハの周縁部を一定の幅で露光するようにし
たものである。
In this apparatus, when the shape of the wafer slightly deviates from the circle, the amount of light entering the light receiving system 68 changes, and the amount of change is fed back to the moving stage 81 to move the moving stage 81 so that the peripheral portion of the wafer is always kept at a constant level. The exposure is performed in a width.

この装置によれば,ウエハ周縁部のレジストは一定の
幅をもって均一に除去され,ウエハ周縁部のレジストが
剥離してごみとなる問題は解決されるが,この装置によ
っても,ウエハの寸法にばらつきがあると,後の工程で
ウエハ周縁部に近いチップに不良が生じたり,ウエハ上
のチップの位置が正確に定まらないといった問題があ
る。
According to this apparatus, the resist at the peripheral portion of the wafer is uniformly removed with a certain width, and the problem that the resist at the peripheral portion of the wafer peels off and is solved can be solved. In such a case, there is a problem that a defect occurs in a chip near the peripheral portion of the wafer in a later process, and a position of the chip on the wafer cannot be accurately determined.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

本発明は,以上の従来法の欠点に鑑み,ウエハ周縁部
のレジストが剥離してごみとなる問題を解決すると共
に,ウエハ周縁部に近いチップでも不良を生じないよう
に周縁露光位置を正確に定めて,1枚のウエハからとれる
チップ数を大きくすると共に,ウエハ上のチップの位置
を確定し,ダイスボンディング等の際のチップの取り違
えを防止することを目的とする。
In view of the drawbacks of the conventional method described above, the present invention solves the problem that the resist on the peripheral edge of the wafer is peeled and becomes garbage, and accurately determines the peripheral exposure position so that a chip near the peripheral edge of the wafer does not cause a defect. It is an object of the present invention to increase the number of chips that can be taken from one wafer, determine the positions of the chips on the wafer, and prevent chips from being mixed at the time of die bonding or the like.

〔課題を解決するための手段〕[Means for solving the problem]

第1図は本発明の原理説明図であり,第1図(a)は
ウエハ周縁部を全部露光する方法,第1図(b)はウエ
ハ周縁部の一部に位置確認用の未露光領域を残し,それ
以外の周縁部を全部露光する方法を説明するための図で
ある。
FIG. 1 is a view for explaining the principle of the present invention. FIG. 1 (a) shows a method of exposing the entire periphery of the wafer, and FIG. 1 (b) shows an unexposed area for position confirmation on a part of the periphery of the wafer. FIG. 7 is a diagram for explaining a method of exposing the entire peripheral portion except for the above.

第1図(a)及び(b)において,1は全面にレジスト
膜の形成されたウエハ,11はウエハの周縁部,2は仮想網,
21はウエハの周縁部と重なる網目,22は位置確認点の両
側の網目,31,32は仮想糸,41,42は位置確認点,51,52は未
露光領域を表す。
1 (a) and 1 (b), 1 is a wafer having a resist film formed on the entire surface, 11 is a peripheral portion of the wafer, 2 is a virtual net,
Reference numeral 21 denotes a mesh overlapping the peripheral portion of the wafer, 22 denotes a mesh on both sides of the position confirmation point, 31 and 32 denote virtual threads, 41 and 42 denote position confirmation points, and 51 and 52 denote unexposed areas.

上記課題は、 1.全面にレジスト膜の形成されたウエハ上の領域を分
割し、分割された領域ごとに露光するウエハの露光方法
において、 最小の露光領域となる単位矩形を網目とする仮想網を
ウエハの全面に掛けたときに、ウエハの周縁部と重なる
網目を周縁部の全周にわたって露光し、ウエハの周縁部
のレジスト膜を除去した後、レジスト膜が残されたチッ
プ形成領域の露光を行うウエハの露光方法と、 2.全面にレジスト膜の形成されたウエハ上の領域を分割
し、分割された領域ごとに露光するウエハの露光方法に
おいて、 最小の露光領域となる単位矩形を網目とする仮想網を
ウエハの全面に掛けたときに、ウエハのほぼ中心を通る
仮想網の直交する2本の仮想糸がウエハの周縁部と交叉
する点を位置確認点とし、位置確認点の両側の網目以外
で、ウエハの周縁部と重なる網目を周縁部の全周にわた
って露光し、位置確認点の両側は未露光領域を設けるよ
うに隙間を空けて露光し、ウエハの周縁部のレジスト膜
を除去した後、レジスト膜が残されたチップ形成領域の
露光を行うウエハの露光方法によって解決される。
The object of the present invention is to: 1. A method of exposing a wafer in which a resist film is formed on an entire surface and dividing the area on the wafer, and exposing each divided area. Is applied over the entire surface of the wafer, the mesh overlapping the peripheral portion of the wafer is exposed over the entire peripheral portion, the resist film on the peripheral portion of the wafer is removed, and the chip forming region where the resist film is left is exposed. 2. In the wafer exposure method in which the area on the wafer where the resist film is formed on the entire surface is divided and the wafer is exposed in each divided area, the unit rectangle that is the minimum exposure area is meshed. When a virtual net is put on the entire surface of the wafer, a point at which two orthogonal virtual yarns of the virtual net passing substantially at the center of the wafer cross the peripheral edge of the wafer is defined as a position confirmation point, and both sides of the position confirmation point The mesh After exposing the mesh overlapping the peripheral portion of the wafer over the entire periphery of the peripheral portion, exposing the both sides of the position confirmation point with a gap so as to provide an unexposed area, and removing the resist film at the peripheral portion of the wafer. The problem is solved by a wafer exposing method for exposing a chip forming region where a resist film is left.

〔作用〕[Action]

本発明では,先ず最小の露光領域となる単位矩形を定
める。この単位矩形はウエハから将来取るべきチップの
形状に対応するものである。
In the present invention, first, a unit rectangle serving as a minimum exposure area is determined. This unit rectangle corresponds to the shape of a chip to be taken in the future from the wafer.

この単位矩形を網目とする仮想網をウエハ全面にかけ
たとすると,ウエハ内部にあってウエハ周縁部と重なら
ない網目に対応する領域は将来チップとして使用できる
領域であり、ウエハ周縁部と重なる網目に対応する領域
はチップとして使用することができない。ウエハ周縁部
と重なる網目の部分に露光してその部分のレジスト膜を
除去すれば,その後の工程でウエハ周縁部のレジスト膜
が剥離して悪影響を及ぼすという問題はなくなる。
If a virtual net having the unit rectangle as a net is applied to the entire surface of the wafer, an area corresponding to a mesh inside the wafer that does not overlap with the periphery of the wafer is an area that can be used as a chip in the future, and corresponds to a mesh that overlaps with the periphery of the wafer. Area cannot be used as a chip. If the portion of the mesh that overlaps with the wafer periphery is exposed to remove the resist film at that portion, the problem that the resist film at the wafer periphery is peeled off in a subsequent process and adversely affects is eliminated.

また,単位矩形を網目とする仮想網により将来取るべ
きチップの位置が確定して,チップとして使用できるチ
ップ数を最大限にまであげることができる。
Further, the position of a chip to be taken in the future is determined by a virtual network having a unit rectangle as a mesh, and the number of chips that can be used as a chip can be maximized.

さらに,位置確認点を設け,そこを含む未露光領域を
形成しておけば,ウエハ毎に寸法にばらつきがあっても
ウエハ単独でチップを形成すべき位置が確定されるの
で,ウエハ内のチップの位置が確定し,例えばダイスボ
ンディングの際チップの取り違えを生じることがない。
Further, if a position confirmation point is provided and an unexposed area including the position confirmation point is formed, the position where the chip is to be formed on the wafer alone is determined even if the dimensions vary from wafer to wafer. Is determined, and for example, there is no case where chips are mixed up at the time of die bonding.

仮想網の網目毎の露光は,例えばウエハをX方向及び
Y方向に移動するX−Yステージの上にのせ,単位矩形
の両辺の方向をX方向及びY方向に合わせ,X方向及びY
方向に単位矩形の寸法を単位としてステップ的に移動
し,露光することにより,達成される。
Exposure for each mesh of the virtual net is performed, for example, by placing a wafer on an XY stage that moves in the X and Y directions, aligning the directions of both sides of the unit rectangle in the X and Y directions, and setting the X and Y directions.
This is achieved by moving stepwise in the direction with the unit rectangle dimension as the unit and exposing.

位置確認点はウエハの中心を通るX軸及びY軸をきめ
るものであるが,ウエハとチップの公称寸法は予め分か
っているから,その位置を予め設定することは可能であ
る。
The position confirmation point determines the X-axis and the Y-axis passing through the center of the wafer. However, since the nominal dimensions of the wafer and the chip are known in advance, the position can be set in advance.

〔実施例〕〔Example〕

以下,本発明の実施例について説明する。 Hereinafter, embodiments of the present invention will be described.

第4図は本発明を実施するための装置を説明するため
の図で,第4図(a)はステップ移動機構を,第4図
(b)はセンサの配置を説明するための図である。
FIG. 4 is a view for explaining an apparatus for carrying out the present invention. FIG. 4 (a) is a view for explaining a step moving mechanism, and FIG. 4 (b) is a view for explaining an arrangement of sensors. .

第4図(a)及び(b)において,1は全面にレジスト
膜の形成されたウエハ,61はウエハステージ,62は回転用
モータ,63は台,64はX方向リニアパルスモータ,65はY
方向リニアパルスモータ,66は光学レンズ系,71,72,73は
センサを表す。
4 (a) and 4 (b), 1 is a wafer having a resist film formed on the entire surface, 61 is a wafer stage, 62 is a rotation motor, 63 is a table, 64 is an X-direction linear pulse motor, and 65 is Y
A directional linear pulse motor, 66 represents an optical lens system, and 71, 72, 73 represent sensors.

ウエハ1はウエハステージ61に真空吸引により固定さ
れている。ウエハステージ61は回転用モータ62によって
回転し,さらにウエハステージ61はX方向リニアパルス
モータ64によってX方向に,Y方向リニアパルスモータ65
によってY方向に移動する。
The wafer 1 is fixed to the wafer stage 61 by vacuum suction. The wafer stage 61 is rotated by a rotation motor 62, and the wafer stage 61 is further moved in the X direction by an X
Moves in the Y direction.

回転用モータ62及びリニアパルスモータ64,65によっ
てウエハ1を移動し,予めウエハのインチ数に応じて設
定されたセンサ71,72,73によりウエハ1の位置を確定す
る。
The wafer 1 is moved by the rotation motor 62 and the linear pulse motors 64, 65, and the position of the wafer 1 is determined by the sensors 71, 72, 73 set in advance according to the number of inches of the wafer.

センサは例えばフォトセンサで,ウエハの周縁部がそ
の位置にきたことを検知する。センサの配置は,例えば
センサ71,72はウエハ1のオリフラをX方向に合わすよ
うに,センサ73はウエハ1の中心を通るX方向をとるよ
うに配置される。
The sensor is, for example, a photo sensor, and detects that the peripheral portion of the wafer has reached that position. For example, the sensors 71 and 72 are arranged so that the orientation flat of the wafer 1 is aligned in the X direction, and the sensor 73 is arranged in the X direction passing through the center of the wafer 1.

このようにして,ウエハ1の位置を確定した後,ウエ
ハはX方向リニアパルスモータ64,Y方向リニアパルスモ
ータ65によって単位矩形の寸法だけステップ状に動かさ
れ,単位矩形にウエハ周縁部が入る所だけ露光される。
After the position of the wafer 1 is thus determined, the wafer is moved stepwise by the size of a unit rectangle by the X-direction linear pulse motor 64 and the Y-direction linear pulse motor 65, and the portion where the wafer periphery enters the unit rectangle. Only exposed.

第2図は実施例Iで,6インチウエハの周縁部を含む単
位矩形を全部露光した例である。第2図において,1は全
面にレジスト膜の形成されたウエハ,11はウエハの周縁
部,21はウエハの周縁部と重なる網目を表す。
FIG. 2 shows an example in which a unit rectangle including a peripheral portion of a 6-inch wafer is entirely exposed in Example I. In FIG. 2, 1 is a wafer having a resist film formed on the entire surface, 11 is a peripheral portion of the wafer, and 21 is a mesh overlapping with the peripheral portion of the wafer.

まず,単位矩形の寸法は縦,横とも5mmとし,6インチ
ウエハの公称寸法に合わせて露光すべき周縁部の位置を
求めておく。単位矩形の寸法は,素子形成後に切り出す
チップの寸法に対応するものである。
First, the size of the unit rectangle is set to 5 mm both vertically and horizontally, and the position of the peripheral edge to be exposed is determined in accordance with the nominal size of the 6-inch wafer. The dimensions of the unit rectangle correspond to the dimensions of the chip to be cut out after forming the element.

次に,例えばオリフラの位置から露光を開始し,次々
に単位矩形の縦の長さ或いは横の長さだけウエハを移動
して露光して行き,ウエハの全周を露光する。
Next, for example, the exposure is started from the position of the orientation flat, and the wafer is successively moved by the vertical length or the horizontal length of the unit rectangle to perform the exposure, and the entire periphery of the wafer is exposed.

その後,現像することによりウエハの周縁部を含む単
位矩形のレジスト膜は除去される。内部に残るレジスト
膜の形成されたウエハ領域はチップとして使用可能な領
域である。
Thereafter, the resist film having a unit rectangular shape including the peripheral portion of the wafer is removed by development. The wafer region in which the resist film remaining inside is a region that can be used as a chip.

第3図は実施例IIで,6インチウエハの周縁部の一部に
位置確認用の未露光領域を残し,それ以外の周縁部を含
む単位矩形を全部露光した例である。第3図において,1
は全面にレジスト膜の形成されたウエハ,11はウエハの
周縁部,21はウエハの周縁部と重なる網目,41,42は位置
確認点,22は位置確認点の両側の網目,51,52は未露光領
域を表す。
FIG. 3 shows an example II in which an unexposed area for position confirmation is left in a part of the peripheral portion of a 6-inch wafer, and the entire unit rectangle including the other peripheral portion is exposed. In Fig. 3, 1
Is a wafer having a resist film formed on the entire surface, 11 is a peripheral portion of the wafer, 21 is a mesh overlapping the peripheral portion of the wafer, 41 and 42 are position confirmation points, 22 is a mesh on both sides of the position confirmation point, 51 and 52 are Indicates an unexposed area.

まず,前述のセンサ71乃至73で6インチウエハの公称
寸法による円部の中心を定めておく。その中心を基準と
して,未露光領域を形成するためのX方向及びY方向の
位置確認点41,42が予め与えられる。単位矩形の寸法は
縦,横とも5mmとし,6インチウエハの公称寸法に合わせ
て露光すべき周縁部の位置を求めておく。単位矩形の寸
法は,チップの寸法に対応する。
First, the center of the circular portion of the nominal size of the 6-inch wafer is determined by the sensors 71 to 73 described above. Based on the center, position confirmation points 41 and 42 in the X and Y directions for forming an unexposed area are given in advance. The dimensions of the unit rectangle are 5 mm both vertically and horizontally, and the position of the peripheral edge to be exposed is determined according to the nominal size of the 6-inch wafer. The dimensions of the unit rectangle correspond to the dimensions of the chip.

位置確認点41,42の両側の網目を除き,ウエハ周縁部1
1と重なる網目を露光する。
Except for the mesh on both sides of the position confirmation points 41 and 42,
The mesh overlapping with 1 is exposed.

位置確認点41の両側の網目はY方向に,位置確認点42
の両側の網目はX方向に,お互いに離れるように1mmづ
つ移動した後,その網目を露光する。
The mesh on both sides of the position confirmation point 41 is
The meshes on both sides are moved in the X direction by 1 mm so as to be separated from each other, and then the meshes are exposed.

露光後,現像すれば基準確認点41,42を含む未露光領
域51,52の部分に2mm幅のレジストが残る。このレジスト
残は,後の工程においてウエハの中心位置を確認し,ウ
エハ上のチップの位置を確定するのに使うことができ
る。
After the exposure, if developed, the resist having a width of 2 mm remains in the unexposed areas 51 and 52 including the reference confirmation points 41 and 42. The remaining resist can be used to confirm the center position of the wafer in a later process and to determine the position of the chip on the wafer.

特にウエハのチップに素子形成を完了し,ウエハから
チップを選び出してダイスボンディングする際,中心位
置が確認できるので,位置が座標付けされたチップを間
違いなく選び出すことができる。
In particular, when element formation is completed on a chip on a wafer, and a chip is selected from the wafer and die-bonded, the center position can be confirmed, so that a chip whose position is coordinated can be selected without fail.

公称6インチウエハといっても,寸法にばらつきがあ
るが,そのばらつきは通常プラスマイナス1mm程度であ
るので,単位矩形の寸法を縦,横ともに5mmとし,公称
値で露光する周縁部を予め設定しておいても実際上問題
はない。安全のためマージンをみて設定しておくことも
できる。
Although the nominal 6-inch wafer has variations in dimensions, the variations are usually about ± 1 mm, so the dimensions of the unit rectangle are set to 5 mm both vertically and horizontally, and the peripheral edge to be exposed at the nominal value is set in advance. There is no practical problem. You can also set the margins for safety.

〔発明の効果〕〔The invention's effect〕

以上説明した様に,本発明によれば,ウエハ周縁部の
露光位置を正確にきめて,1枚のウエハからとれるチップ
数を大きくすることができると共にダイスボンディング
等の際のチップの取り違えを防止することができる。
As described above, according to the present invention, it is possible to accurately determine the exposure position of the peripheral portion of the wafer, to increase the number of chips that can be obtained from one wafer, and to prevent chip mixing during die bonding and the like. can do.

本発明はチップ数が多い大きなウエハにおいて特に大
きな効果を奏し,集積回路の製造に寄与するところが大
きい。
The present invention is particularly effective for a large wafer having a large number of chips, and greatly contributes to the manufacture of integrated circuits.

【図面の簡単な説明】[Brief description of the drawings]

第1図は本発明の原理説明図で,第1図(a)はウエハ
周縁部を全部露光する場合,第1図(b)はウエハ周縁
部に未露光領域を残す場合, 第2図は実施例Iを説明するための図, 第3図は実施例IIを説明するための図, 第4図は本発明を実施する装置を説明するための図で,
第4図(a)はステップ移動機構,第4図(b)はセン
サの配置, 第5図は従来例Iを説明するための図, 第6図は従来例IIを説明するための図 である。図において, 1はウエハであって全面にレスジト膜の形成されたウエ
ハ,11はウエハの周縁部,2は仮想網,21はウエハの周縁部
と重なる網目,22は位置確認点の両側の網目,31,32は仮
想網を形成する仮想糸,41,42は位置確認点,51,52は未露
光領域,61はウエハステージ,62は回転用モータ,63は台,
64はX方向はリニアパルスモータ,65はY方向はリニア
パルスモータ,66は光学レンズ系,67は発光系,68は受光
系,71乃至73はセンサ,81は移動ステージ を表す。
FIG. 1 is a view for explaining the principle of the present invention. FIG. 1 (a) shows a case where the entire periphery of the wafer is exposed, FIG. 1 (b) shows a case where an unexposed area is left on the periphery of the wafer, and FIG. FIG. 3 is a diagram for explaining embodiment I, FIG. 3 is a diagram for explaining embodiment II, and FIG. 4 is a diagram for explaining an apparatus for implementing the present invention.
4 (a) is a step moving mechanism, FIG. 4 (b) is an arrangement of sensors, FIG. 5 is a diagram for explaining Conventional Example I, and FIG. 6 is a diagram for explaining Conventional Example II. is there. In the figure, 1 is a wafer, on which a resit film is formed on the entire surface, 11 is a peripheral portion of the wafer, 2 is a virtual net, 21 is a mesh overlapping the peripheral portion of the wafer, and 22 is a mesh on both sides of the position confirmation point. , 31 and 32 are virtual threads forming a virtual net, 41 and 42 are position confirmation points, 51 and 52 are unexposed areas, 61 is a wafer stage, 62 is a rotation motor, 63 is a table,
64 is a linear pulse motor in the X direction, 65 is a linear pulse motor in the Y direction, 66 is an optical lens system, 67 is a light emitting system, 68 is a light receiving system, 71 to 73 are sensors, and 81 is a moving stage.

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】全面にレジスト膜の形成されたウエハ上の
領域を分割し、分割された領域ごとに露光するウエハの
露光方法において、 最小の露光領域となる単位矩形を網目とする仮想網を該
ウエハの全面に掛けたときに、該ウエハの周縁部と重な
る網目を該周縁部の全周にわたって露光し、該ウエハの
周縁部のレジスト膜を除去した後、レジスト膜が残され
たチップ形成領域の露光を行うことを特徴とするウエハ
の露光方法。
1. A wafer exposure method for dividing a region on a wafer having a resist film formed on the entire surface and exposing each divided region, comprising the steps of: forming a virtual net having a unit rectangle serving as a minimum exposure region as a mesh; When the entire surface of the wafer is hung, a mesh overlapping the peripheral portion of the wafer is exposed over the entire periphery of the peripheral portion, and after the resist film on the peripheral portion of the wafer is removed, a chip formation in which the resist film is left is formed. A method of exposing a wafer, comprising exposing a region.
【請求項2】全面にレジスト膜の形成されたウエハ上の
領域を分割し、分割された領域ごとに露光するウエハの
露光方法において、 最小の露光領域となる単位矩形を網目とする仮想網を該
ウエハの全面に掛けたときに、該ウエハのほぼ中心を通
る該仮想網の直交する2本の仮想糸が該ウエハの周縁部
と交叉する点を位置確認点とし、該位置確認点の両側の
網目以外で、該ウエハの周縁部と重なる網目を該周縁部
の全周にわたって露光し、該位置確認点の両側は未露光
領域を設けるように隙間を空けて露光し、該ウエハの周
縁部のレジスト膜を除去した後、レジスト膜が残された
チップ形成領域の露光を行うことを特徴とするウエハの
露光方法。
2. A wafer exposure method for dividing an area on a wafer having a resist film formed on the entire surface and exposing each divided area, comprising: forming a virtual net having a unit rectangle serving as a minimum exposure area as a mesh; A point at which two virtual threads of the virtual net, which pass through substantially the center of the wafer and intersect with the periphery of the wafer when the entire surface of the wafer is crossed, is defined as a position confirmation point. Exposing a mesh overlapping with the periphery of the wafer over the entire periphery of the periphery of the wafer, exposing both sides of the position confirmation point with a gap so as to provide an unexposed area, and exposing the periphery of the wafer to the periphery of the wafer. A method of exposing a wafer, comprising: exposing a chip forming region where the resist film remains after removing the resist film.
JP1100858A 1989-04-20 1989-04-20 Wafer exposure method Expired - Fee Related JP2752148B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1100858A JP2752148B2 (en) 1989-04-20 1989-04-20 Wafer exposure method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1100858A JP2752148B2 (en) 1989-04-20 1989-04-20 Wafer exposure method

Publications (2)

Publication Number Publication Date
JPH02278814A JPH02278814A (en) 1990-11-15
JP2752148B2 true JP2752148B2 (en) 1998-05-18

Family

ID=14285012

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1100858A Expired - Fee Related JP2752148B2 (en) 1989-04-20 1989-04-20 Wafer exposure method

Country Status (1)

Country Link
JP (1) JP2752148B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2593831B2 (en) * 1991-03-20 1997-03-26 ウシオ電機株式会社 Apparatus and method for exposing unnecessary resist on wafer

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6328231A (en) * 1986-07-18 1988-02-05 日立電子エンジニアリング株式会社 Electric source control circuit
JPS6338231A (en) * 1986-08-01 1988-02-18 Fujitsu Ltd Forming method for resist mask
JPS63188938U (en) * 1987-05-28 1988-12-05

Also Published As

Publication number Publication date
JPH02278814A (en) 1990-11-15

Similar Documents

Publication Publication Date Title
US3844655A (en) Method and means for forming an aligned mask that does not include alignment marks employed in aligning the mask
JPH11345866A (en) Semiconductor device and positioning method thereof
US6614507B2 (en) Apparatus for removing photoresist edge beads from thin film substrates
US6071315A (en) Two-dimensional to three-dimensional VLSI design
US4477182A (en) Pattern exposing apparatus
JP2752148B2 (en) Wafer exposure method
US4461567A (en) Method of and apparatus for the positioning of disk-shaped workpieces, particularly semiconductor wafers
JP3157751B2 (en) Dicing method for semiconductor substrate
JP2534567B2 (en) Wafer edge exposure method and wafer edge exposure apparatus
JPH01264220A (en) Reduction projection aligner
JPH04291914A (en) Exposing method for unnecessary resist on wafer
JP2652043B2 (en) Peripheral exposure apparatus and peripheral exposure method for photoresist film
JPH0664337B2 (en) Photomask for semiconductor integrated circuit
JP3198309B2 (en) Exposure apparatus, exposure method and work processing method
JPH08203808A (en) Projection exposure system and method for manufacturing semiconductor device
JPS6246522A (en) High speed alignment exposure
JPH09306806A (en) X-ray mask and its alignment method
JP2001249462A (en) Exposure device
JPH03191348A (en) Reticle for reduction stepper
JPH04214612A (en) Projection aligner
JPH02246313A (en) Target pattern and window pattern for mask alignment of aligner
JP2610601B2 (en) Wafer periphery exposure system
JPH08102439A (en) Exposure device for unwanted resist on wafer
JP2946637B2 (en) Projection exposure method
JPS6341020A (en) Manufacture of semiconductor device

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees