JPH02278814A - Exposure of wafer - Google Patents

Exposure of wafer

Info

Publication number
JPH02278814A
JPH02278814A JP10085889A JP10085889A JPH02278814A JP H02278814 A JPH02278814 A JP H02278814A JP 10085889 A JP10085889 A JP 10085889A JP 10085889 A JP10085889 A JP 10085889A JP H02278814 A JPH02278814 A JP H02278814A
Authority
JP
Japan
Prior art keywords
wafer
mesh
peripheral edge
exposed
chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10085889A
Other languages
Japanese (ja)
Other versions
JP2752148B2 (en
Inventor
Kazuo Shimane
島根 一男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1100858A priority Critical patent/JP2752148B2/en
Publication of JPH02278814A publication Critical patent/JPH02278814A/en
Application granted granted Critical
Publication of JP2752148B2 publication Critical patent/JP2752148B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PURPOSE:To accurately decide an exposure position at a peripheral edge part of a wafer, to increase the number of chips available from the wafer and to prevent a wrong chip from being taken by a method wherein a virtual net which uses a unit rectangle as a mesh is put on the whole surface of the wafer, each mesh which is overlapped with the peripheral edge part of the wafer is exposed and the peripheral edge part of the water is exposed. CONSTITUTION:A position of a wafer 1 where a resist film has been formed on the whole surface is decided; after that, the wafer is moved in a step manner by a size of a unit rectangle by using an X-direction linear pulse motor 64 and a Y-direction linear pulse motor 65; only parts where a peripheral edge part of the wafer is included in unit rectangles are exposed. After that, a developing operation is executed; the resist film of the unit rectangles including the peripheral edge part of the wafer is removed. A region of the wafer where the resist film remaining at the inside is a region which can be used as chips. Thereby, an exposure position at the peripheral edge part of the wafer is decided accurately; the number of chips which are available from one wafer can be increased; it is possible to prevent a wrong chip from being taken at a die bonding operation or the like.

Description

【発明の詳細な説明】 〔概要] ウェハの露光方法に係り、特にウェハ周縁部の露光方法
に関し。
DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a method of exposing a wafer, and particularly to a method of exposing a peripheral portion of a wafer.

周縁露光位置を正確に決めて1枚のウェハからとれるチ
ップ数を大きくすると共に、ウェハ上のチップの位置を
確定することを目的とし。
The purpose is to accurately determine the peripheral edge exposure position to increase the number of chips that can be taken from one wafer, and to determine the position of the chips on the wafer.

(1)全面にレジスト膜の形成されたウェハの周縁部を
露光するウェハの露光方法において、最小の露光領域と
なる単位矩形を定め、該ウェハ全面に該単位矩形を網目
とする仮想網をかけたとした時に、該ウェハの周縁部と
重なる網目を網目毎に露光して、該ウェハの周縁部の全
部を露光するウェハの露光方法、及び〔2〕全面にレジ
スト膜の形成されたウェハの周縁部を露光するウェハの
露光方法において、最小の露光領域となる単位矩形を定
め、該ウェハ全面に該単位矩形を網目とする仮想網をか
けたとした時に、該ウェハのほぼ中心を通る該仮想網の
直交する2本の仮想糸が該ウェハの周縁部と交叉する点
を位置確認点と定め、該位置確認点の両側の網目を除き
該ウェハの周縁部と重なる網目を網目毎に露光し、該位
置確認点の両側の網目は該位置確認点の両側に離れるよ
うに移動して露光することにより、該位置確認点を含む
未露光領域を形成するウェハの露光方法により構成する
(1) In a wafer exposure method that exposes the peripheral edge of a wafer on which a resist film is formed on the entire surface, a unit rectangle is determined as the minimum exposure area, and a virtual mesh is created over the entire surface of the wafer using the unit rectangle as a mesh. [2] A wafer exposure method that exposes the entire periphery of the wafer by exposing meshes that overlap with the periphery of the wafer mesh by mesh, and [2] the periphery of the wafer with a resist film formed on the entire surface. In a wafer exposure method in which a unit rectangle is defined as the minimum exposure area, and a virtual mesh having the unit rectangle as a mesh is applied to the entire surface of the wafer, the virtual mesh passing through approximately the center of the wafer is The point where the two orthogonal virtual threads intersect with the peripheral edge of the wafer is set as a position confirmation point, and the meshes that overlap with the peripheral edge of the wafer are exposed mesh by mesh, excluding the meshes on both sides of the position confirmation point, The meshes on both sides of the position confirmation point are formed by a wafer exposure method in which an unexposed area including the position confirmation point is formed by moving the meshes on both sides of the position confirmation point and exposing them.

〔産業上の利用分野〕[Industrial application field]

本発明はウェハの露光方法に係り、特にウェハ周縁部の
露光方法に関する。
The present invention relates to a method for exposing a wafer, and more particularly to a method for exposing a peripheral portion of a wafer.

半導体のフォト工程においては、ウェハ全面にレジスト
膜を形成した後でウェハ周縁部のレジストを除いておく
必要がある。レジストの塗膜は通常ウェハ周縁部で厚く
なり、その後の工程でその一部が剥離したりすることが
ある。また、ウェハをキャリアに収納する時ウェハ周縁
部がキャリアの溝と接触し、その部分のレジストが剥離
したりする。剥離したレジストはごみとなって、その後
の工程に支障を来す。そういう理由からウェハ全面にレ
ジスト膜を形成した後でウェハ周縁部のレジストを除く
ことが行われる。
In a semiconductor photo process, it is necessary to remove the resist from the periphery of the wafer after forming a resist film over the entire surface of the wafer. The resist coating is usually thicker at the wafer periphery, and some of it may peel off during subsequent steps. Further, when the wafer is stored in the carrier, the peripheral edge of the wafer comes into contact with the groove of the carrier, and the resist in that area may peel off. The peeled resist becomes dust and interferes with subsequent processes. For this reason, after forming a resist film over the entire surface of the wafer, the resist at the periphery of the wafer is removed.

しかも、集積回路の製造では、ウェハ周縁部のレジスト
の除去する領域を必要最小限におさえて1枚のウェハか
らとれるチップ数を大きくすることも要求される。
Moreover, in the manufacture of integrated circuits, it is also required to increase the number of chips that can be obtained from one wafer by minimizing the area from which resist is removed at the periphery of the wafer.

さらに、素子形成を終えた大量のチップが配置されてい
るウェハからチップを取ってグイバッドにボンディング
する際、チップの取り違え等を防止することも要求され
ている。
Furthermore, when chips are taken from a wafer on which a large number of chips on which device formation has been completed are placed and bonded to a Guibad, it is also required to prevent mix-ups of chips.

〔従来の技術〕[Conventional technology]

従来、ウェハ周縁部のレジストを除去する方法の一つと
して、第5図の従来例■に示すような方法がある。第5
図において、lは全面にレジスト膜の形成されたウェハ
、61はウェハステージ、62は回転用モータ、63は
台、66はn光装置の一部をなす光学レンズ系を表す。
Conventionally, as one of the methods for removing the resist at the periphery of a wafer, there is a method as shown in the conventional example (2) in FIG. Fifth
In the figure, l represents a wafer having a resist film formed on its entire surface, 61 represents a wafer stage, 62 represents a rotation motor, 63 represents a stand, and 66 represents an optical lens system forming a part of the n-light device.

この方法では、はぼ円形のウェハlを中心軸の周りに回
転させることにより、ウェハ周縁部からのある幅を光学
レンズ系66により露光することにより、ウェハ周縁部
のレジストを除去する。ところが、ウェハの寸法にばら
つきがあること、ウェハから将来取るべきチップの形状
は四角形であること等の理由から、ウェハの位置設定の
精度が悪いと、後の工程でウェハ周縁部に近いチップに
不良が生じたり、ウェハ上のチップの位置が正確に定ま
らないといった問題があった。
In this method, a roughly circular wafer l is rotated around a central axis, and a certain width from the wafer periphery is exposed to light by an optical lens system 66, thereby removing the resist at the wafer periphery. However, due to variations in wafer dimensions and the fact that the shape of chips to be taken from the wafer in the future is rectangular, if the accuracy of wafer positioning is poor, chips near the wafer edge may be placed in later processes. There were problems such as defects occurring and the position of the chips on the wafer not being accurately determined.

また、ウェハの周縁位置を自動的に検出しなからウェハ
周縁部から一定の幅を露光する露光装置もある。第6図
の従来例■はこれを説明するための図で、lは全面にレ
ジスト膜の形成されたウェハ261はウェハステージ、
62は回転用モータ、63は台、66は露光装置の一部
をなす光学レンズ系。
There is also an exposure apparatus that does not automatically detect the position of the wafer's periphery and exposes a certain width from the wafer's periphery. Conventional example ■ in FIG. 6 is a diagram for explaining this, and l is a wafer 261 on which a resist film is formed on the entire surface, a wafer stage,
62 is a rotation motor, 63 is a stand, and 66 is an optical lens system forming a part of the exposure device.

67は発光系、68は受光系、81は移動ステージを表
す。
67 represents a light emitting system, 68 represents a light receiving system, and 81 represents a moving stage.

この装置は、ウェハの形状が円形から若干はずれた場合
、受光系68に入る光量が変化し、その変化量を移動ス
テージ81にフィードバックして移動ステージ81を動
かし、常にウェハの周縁部を一定の幅で露光するように
したものである。
In this device, when the shape of the wafer slightly deviates from a circle, the amount of light entering the light receiving system 68 changes, and the amount of change is fed back to the moving stage 81 to move the moving stage 81, so that the peripheral edge of the wafer is always kept at a constant level. It is designed to expose in width.

この装置によれば、ウェハ周縁部のレジストは一定の幅
をもって均一に除去され、ウェハ周縁部のレジストが剥
離してごみとなる問題は解決されるが、この装置によっ
ても、ウェハの寸法にばらつきがあると、後の工程でウ
ェハ周縁部に近いチップに不良が生じたり、ウェハ上の
チップの位置が正確に定まらないといった問題がある。
According to this device, the resist on the wafer edge is removed uniformly with a certain width, which solves the problem of the resist peeling off on the wafer edge and becoming dust, but this device also allows for variations in wafer dimensions. If this occurs, there are problems such as defects occurring in chips near the wafer periphery in later steps or the position of the chips on the wafer not being accurately determined.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

本発明は2以上の従来法の欠点に鑑み、ウエハ周縁部の
レジストが剥離してごみとなる問題を解決すると共に、
ウェハ周縁部に近いチップでも不良を生じないように周
縁露光位置を正確に定めて。
In view of two or more drawbacks of the conventional method, the present invention solves the problem of resist peeling off at the wafer edge and becoming dust, and
The edge exposure position is precisely determined to prevent defects even in chips near the wafer edge.

1枚のウェハからとれるチップ数を大きくすると共に、
ウェハ上のチップの位置を確定し、ダイスボンディング
等の際のチップの取り違えを防止することを目的とする
Increasing the number of chips that can be obtained from one wafer,
The purpose is to determine the position of chips on a wafer and prevent mix-ups of chips during die bonding, etc.

〔課題を解決するための手段〕[Means to solve the problem]

第1図は本発明の原理説明図であり、第1図(a)はウ
ェハ周縁部を全部露光する方法、第1図(b)はウェハ
周縁部の一部に位置確認用の未露光領域を残し、それ以
外の周縁部を全部露光する方法を説明するための図であ
る。
FIG. 1 is a diagram explaining the principle of the present invention. FIG. 1(a) shows a method of exposing the entire wafer periphery, and FIG. 1(b) shows an unexposed area on a part of the wafer periphery for position confirmation. FIG. 4 is a diagram for explaining a method of exposing all the peripheral parts except for the periphery.

第1図(a)及び(b)において、■は全面にレジスト
膜の形成されたウェハ、11はウェハの周縁部、2は仮
想網、 21はウェハの周縁部と重なる網目、22は位
置確認点の両側の網目、 31.32は仮想糸、 41
.42は位置確認点、 51.52は未露光領域を表す
In FIGS. 1(a) and (b), ■ is a wafer with a resist film formed on the entire surface, 11 is the periphery of the wafer, 2 is a virtual mesh, 21 is a mesh that overlaps the wafer's periphery, and 22 is a position confirmation. Mesh on both sides of the point, 31.32 is virtual thread, 41
.. 42 represents a position confirmation point, and 51.52 represents an unexposed area.

上記課題は、 〔1〕全面にレジスト膜の形成されたウ
ェハ1周縁部11を露光するウェハの露光方法において
、最小の露光領域となる単位矩形を定め6該ウ工ハ全面
に該単位矩形を網目とする仮想′yI2をかけたとした
時に、該ウェハ1の周縁部11と重なる網目21を網目
毎に露光して、該ウェハ1の周縁部11の全部を露光す
るウェハの露光方法、及び〔2〕全面にレジスト膜の形
成されたウェハ1の周縁部11を露光するウェハの露光
方法において。
[1] In a wafer exposure method that exposes the peripheral edge 11 of a wafer 1 on which a resist film is formed on the entire surface, a unit rectangle is determined to be the minimum exposure area, and 6 the unit rectangle is spread over the entire surface of the wafer. A wafer exposure method in which the entire peripheral edge 11 of the wafer 1 is exposed by exposing each mesh 21 that overlaps the peripheral edge 11 of the wafer 1 to light when a virtual 'yI2 as a mesh is applied; 2] In a wafer exposure method that exposes the peripheral portion 11 of the wafer 1 on which a resist film is formed on the entire surface.

最小の露光領域となる単位矩形を定め、該ウェハ全面に
該単位矩形を網目とする仮想網2をかけたとした時に、
該ウェハ1のほぼ中心を通る該仮想網2の直交する2本
の仮想糸31.32が該ウェハ1の周縁部11と交叉す
る点を位置確認点41.42と定め、該位置確認点41
.42の両側の網目22を除き該ウェハ1の周縁部11
と重なる網目21を網目毎に露光し、該位置確認点41
.42の両側の網目22は該位置確認点41.42の両
側に離れるように移動して露光することにより5該位置
確認点41.42を含む未露光領域51.52を形成す
るウェハの露光方法によって解決される。
When a unit rectangle serving as the minimum exposure area is determined and a virtual mesh 2 with the unit rectangle as a mesh is applied over the entire surface of the wafer,
The point where the two orthogonal virtual threads 31.32 of the virtual network 2 passing through the approximate center of the wafer 1 intersect the peripheral edge 11 of the wafer 1 is defined as a position confirmation point 41.42, and the position confirmation point 41
.. The peripheral edge 11 of the wafer 1 except for the meshes 22 on both sides of the wafer 42
The meshes 21 that overlap with each other are exposed mesh by mesh, and the position confirmation point 41 is
.. A wafer exposure method in which the meshes 22 on both sides of 42 are moved to both sides of the position confirmation point 41.42 and exposed, thereby forming an unexposed area 51.52 including the position confirmation point 41.42. solved by.

〔作用〕[Effect]

本発明では、先ず最小の露光領域となる単位矩形を定め
る。この単位矩形はウェハがら将来取るべきチップの形
状に対応するものである。
In the present invention, first, a unit rectangle that is the minimum exposure area is determined. This unit rectangle corresponds to the shape of the chip to be taken in the future from the wafer.

この単位矩形を網目とする仮想網をウェハ全面にかけた
とすると、ウェハ内部にある網目に対応する領域は将来
チップに使用できる領域であり。
If a virtual network with meshes of this unit rectangle is applied over the entire surface of the wafer, the area inside the wafer corresponding to the network is an area that can be used for chips in the future.

網目と重なるウェハ周縁部を含む領域はチップとして使
用することはできない。ウェハ周縁部と重なる網目の部
分に露光してその部分のレジスト膜を除去すれば、その
後の工程でウェハ周縁部のレジスト膜が剥離して悪影響
を及ぼすという問題はなくなる。
The area including the wafer periphery that overlaps with the mesh cannot be used as a chip. If the portion of the mesh that overlaps the wafer periphery is exposed to light and the resist film in that portion is removed, the problem that the resist film on the wafer periphery is peeled off in subsequent steps and has an adverse effect is eliminated.

また、単位矩形を網目とする仮想網により将来取るべき
チップの位置が確定して、チップとして使用できるチッ
プ数を最大限にまであげることができる。
Further, the positions of chips to be taken in the future can be determined by a virtual network having unit rectangles as meshes, and the number of chips that can be used as chips can be maximized.

さらに1位置確認点を設け、そこを含む未露光領域を形
成しておけば、ウェハ毎に寸法にばらつきがあってもウ
ェハ単独でチップを形成すべき位置が確定されるので、
ウェハ内のチップの位置が確定し2例えばダイスボンデ
ィングの際チップの取り違えを生じることがない。
Furthermore, by setting one position confirmation point and forming an unexposed area that includes that point, the position where chips should be formed on the wafer alone can be determined even if the dimensions vary from wafer to wafer.
The position of the chips within the wafer is determined, and there is no possibility of mixing up chips during die bonding, for example.

仮想網の網目毎の露光は2例えばウェハをX方向及びX
方向に移動するX−Yステージの上にのせ、単位矩形の
両辺の方向をX方向及びX方向に合わせ、X方向及びX
方向に単位矩形の寸法を単位としてステップ的に移動し
、露光することにより、達成される。
The exposure for each mesh of the virtual mesh is 2, for example, the wafer is exposed in the X direction and
Place it on an X-Y stage that moves in the direction, align the directions of both sides of the unit rectangle with the
This is achieved by moving stepwise in units of unit rectangular dimensions and exposing.

位置確認点はウェハの中心を通るY軸及びY軸をきめる
ものであるが、ウェハとチップの公称寸法は予め分かっ
ているから、その位置を予め設定することは可能である
The position confirmation points are for determining the Y-axis passing through the center of the wafer and the Y-axis, but since the nominal dimensions of the wafer and chips are known in advance, the positions can be set in advance.

〔実施例〕〔Example〕

以下1本発明の実施例について説明する。 An embodiment of the present invention will be described below.

第4図は本発明を実施するための装置を説明するための
図で、第4図(a)はステップ移動a構を、第4図(b
)はセンサの配置を説明するための図である。
FIG. 4 is a diagram for explaining an apparatus for carrying out the present invention. FIG. 4(a) shows a step movement a structure, and FIG. 4(b)
) is a diagram for explaining the arrangement of sensors.

第4図(a)及び(b)において、1は全面にレジスト
膜の形成されたウェハ、 61はウェハステージ、62
は回転用モータ、63は台、64はX方向リニアパルス
モータ、65はX方向リニアパルスモータ、66は光学
レンズ系、 71.72.73はセンサを表す。
In FIGS. 4(a) and (b), 1 is a wafer with a resist film formed on the entire surface, 61 is a wafer stage, and 62
63 is a rotation motor, 63 is a stand, 64 is an X-direction linear pulse motor, 65 is an X-direction linear pulse motor, 66 is an optical lens system, and 71, 72, and 73 are sensors.

ウェハlはウェハステージ61に真空吸引により固定さ
れている。ウェハステージ61は回転用モータ62によ
って回転し、さらにウェハステージ61はX方向リニア
パルスモータ64によってX方向に。
The wafer l is fixed to the wafer stage 61 by vacuum suction. The wafer stage 61 is rotated by a rotation motor 62, and the wafer stage 61 is rotated in the X direction by an X direction linear pulse motor 64.

X方向リニアパルスモータ65によってX方向に移動す
る。
It moves in the X direction by the X direction linear pulse motor 65.

回転用モータ62及びリニアパルスモークロ4.65に
よってウェハlを移動し、予めウェハのインチ数に応じ
て設定されたセンサ71.72.73によりウェハlの
位置を確定する。
The wafer l is moved by the rotation motor 62 and the linear pulse aperture 4.65, and the position of the wafer l is determined by sensors 71, 72, and 73 set in advance according to the number of inches of the wafer.

センサは例えばフォトセンサで、ウェハの周縁部がその
位置にきたことを検知する。センサの配置は1例えばセ
ンサ71.72はウェハlのオリフラをX方向に合わす
ように、センサ73はウェハ1の中心を通るX方向をと
るように配置される。
The sensor is, for example, a photosensor, which detects when the peripheral edge of the wafer has reached that position. For example, the sensors 71 and 72 are arranged so that the orientation flat of the wafer 1 is aligned with the X direction, and the sensor 73 is arranged so that the X direction passes through the center of the wafer 1.

このようにして、ウェハ1の位置を確定した後。After determining the position of the wafer 1 in this way.

ウェハはX方向リニアパルスモータ64.X方向リニア
パルスモータ65によって単位矩形の寸法だけステップ
状に動かされ、単位矩形にウェハ周縁部が入る所だけ露
光される。
The wafer is moved by an X-direction linear pulse motor 64. The X-direction linear pulse motor 65 moves the wafer stepwise by the size of the unit rectangle, and only the area where the peripheral edge of the wafer falls within the unit rectangle is exposed.

第2図は実施例■で、6インチウェハの周縁部を含む単
位矩形を全部露光した例である。第2図において、lは
全面にレジスト膜の形成されたウェハ、11はウェハの
周縁部、21はウェハの周縁部と重なる網目を表す。
FIG. 2 shows Example 2, in which the entire unit rectangle including the peripheral edge of a 6-inch wafer was exposed. In FIG. 2, l represents a wafer on which a resist film is formed on the entire surface, 11 represents the peripheral edge of the wafer, and 21 represents a mesh that overlaps the peripheral edge of the wafer.

まず、単位矩形の寸法は縦、横とも5mmとし。First, the dimensions of the unit rectangle are 5 mm both in length and width.

6インチウェハの公称寸法に合わせて露光すべき周縁部
の位置を求めておく。単位矩形の寸法は。
The position of the peripheral edge to be exposed is determined in accordance with the nominal dimensions of the 6-inch wafer. The dimensions of the unit rectangle are.

素子形成後に切り出すチップの寸法に対応するものであ
る。
This corresponds to the size of a chip cut out after element formation.

次に9例えばオリフラの位置から露光を開始し5次々に
単位矩形の縦の長さ或いは横の長さだけウェハを移動し
て露光して行き、ウェハの全周を露光する。
Next, exposure is started from the position of the orientation flat, for example, and the wafer is exposed by moving the wafer five times one after another by the length or width of the unit rectangle, thereby exposing the entire circumference of the wafer.

その後、現像することによりウェハの周縁部を含む単位
矩形のレジスト膜は除去される。内部に残るレジスト膜
の形成されたウェハ領域はチップとして使用可能な領域
である。
Thereafter, the unit rectangular resist film including the periphery of the wafer is removed by development. The wafer area where the resist film remains inside is an area that can be used as a chip.

第3図は実施例■で、6インチウェハの周縁部の一部に
位置確認用の未露光領域を残し、それ以外の周縁部を含
む単位矩形を全部露光した例である。第3図において、
lは全面にレジスト膜の形成されたウェハ、11はウェ
ハの周縁部、21はウェハの周縁部と重なる網目、 4
1.42は位置確認点。
FIG. 3 is an example (2) in which an unexposed area for position confirmation was left in a part of the periphery of a 6-inch wafer, and the entire unit rectangle including the other periphery was exposed. In Figure 3,
1 is a wafer on which a resist film is formed on the entire surface; 11 is a peripheral edge of the wafer; 21 is a mesh that overlaps with the peripheral edge of the wafer; 4
1.42 is the location confirmation point.

22は位置確認点の両側の網目、 5L 52は未露光
領域を表す。
22 represents mesh on both sides of the position confirmation point, and 5L 52 represents an unexposed area.

まず、前述のセンサ71乃至73で6インチウェハの公
称寸法による内部の中心を定めておく。その中心を基準
として、未露光領域を形成するためのX方向及びX方向
の位置確認点41.42が予め与えられる。単位矩形の
寸法は縦、横とも5mmとし。
First, the internal center of the 6-inch wafer according to its nominal dimensions is determined using the sensors 71 to 73 described above. With the center as a reference, position confirmation points 41 and 42 in the X direction and in the X direction for forming an unexposed area are given in advance. The dimensions of the unit rectangle are 5 mm both in length and width.

6インチウェハの公称寸法に合わせて露光すべき周縁部
の位置を求めておく。単位矩形の寸法は。
The position of the peripheral edge to be exposed is determined in accordance with the nominal dimensions of the 6-inch wafer. The dimensions of the unit rectangle are.

チップの寸法に対応する。Corresponds to the dimensions of the chip.

位置確認点41.42の両側の網目を除き、ウェハ周縁
部11と重なる網目を露光する。
The meshes on both sides of the position confirmation points 41 and 42 are removed, and the meshes that overlap the wafer peripheral edge 11 are exposed.

位置確認点41の両側の網目はX方向に1位置確認点4
2の両側の網目はX方向に、お互いに離れるように1m
l1lづつ移動した後、その網目を露光する。
The mesh on both sides of the position confirmation point 41 has one position confirmation point 4 in the X direction.
The meshes on both sides of 2 are 1m apart from each other in the X direction.
After moving by l1l, the mesh is exposed.

露光後、現像すれば基準確認点41.42を含む未露光
領域51.52の部分に2mm幅のレジストが残る。
After exposure and development, a resist with a width of 2 mm remains in an unexposed area 51.52 including the reference confirmation point 41.42.

このレジスト残は、後の工程においてウェハの中心位置
を確認し、ウェハ上のチップの位置を確定するのに使う
ことができる。
This resist residue can be used in later steps to confirm the center position of the wafer and determine the position of the chips on the wafer.

特にウェハのチップに素子形成を完了し、ウェハからチ
ップを選び出してダイスボンディングする際、中心位置
が確認できるので1位置が座標付けされたチップを間違
いなく選び出すことができる。
In particular, when elements are formed on chips on a wafer and chips are selected from the wafer for die bonding, the center position can be confirmed, so chips with coordinates assigned to one position can be selected without fail.

公称6インチウェハといっても1寸法にばらつきがある
が、そのばらつきは通常プラスマイナス1mm程度であ
るので、単位矩形の寸法を縦、横ともに5IIIIIl
とし、公称値で露光する周縁部を予め設定しておいても
実際上問題はない。安全のためマージンをみて設定して
おくこともできる。
Even though it is a nominally 6-inch wafer, there is variation in one dimension, but the variation is usually about plus or minus 1 mm, so the dimensions of the unit rectangle are 5IIIIIIl both vertically and horizontally.
There is no problem in practice even if the peripheral portion to be exposed to light is set in advance at a nominal value. For safety, you can also set a margin.

〔発明の効果〕〔Effect of the invention〕

以上説明した様に2本発明によれば、ウェハ周縁部の露
光位置を正確にきめて、1枚のウェハからとれるチップ
数を太き(することができると共にダイスボンディング
等の隙のチップの取り違えを防止することができる。
As explained above, according to the present invention, it is possible to accurately determine the exposure position on the wafer periphery, increase the number of chips that can be taken from one wafer, and prevent mix-up of chips during die bonding etc. can be prevented.

本発明はチップ数が多い大きなウェハにおいて特に大き
な効果を奏し、集積回路の製造に寄与するところが大き
い。
The present invention is particularly effective in large wafers with a large number of chips, and greatly contributes to the manufacture of integrated circuits.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の原理説明図で、第1図(a)はウェハ
周縁部を全部露光する場合、第1図(b)はウェハ周縁
部に未露光領域を残す場合。 第2図は実施例Iを説明するための図。 第3図は実施例■を説明するための図。 第4図は本発明を実施する装置を説明するための図で、
第4図(a)はステップ移動機構、第4図(b)はセン
サの配置。 第5図は従来例■を説明するための図。 第6図は従来例■を説明するための図 である。図において。 ■はウェハであって全面にレジスト膜の形成されたウェ
ハ。 11はウェハの周縁部。 2は仮想網。 21はウェハの周縁部と重なる網目。 22は位置確認点の両側の網目。 31、32は仮想網を形成する仮想糸。 41、42は位置確認点。 51、52は未露光領域。 61はウェハステージ。 62は回転用モータ。 63は台。 64はX方向はリニアパルスモーク。 65はY方向はリニアパルスモータ1 66は光学レンズ系。 67は発光系。 68は受光系。 71乃至73はセンサ。 81はf多動ステージ (a) ↑そ日月の月五¥説B月図 男 6 図(fの1) +し+ 不te14のR理説朗図 男 イ 図 (その2) 一 カ 」
FIG. 1 is a diagram illustrating the principle of the present invention. FIG. 1(a) shows the case where the entire periphery of the wafer is exposed, and FIG. 1(b) shows the case where an unexposed area is left at the periphery of the wafer. FIG. 2 is a diagram for explaining Example I. FIG. 3 is a diagram for explaining embodiment (2). FIG. 4 is a diagram for explaining an apparatus for carrying out the present invention,
FIG. 4(a) shows the step movement mechanism, and FIG. 4(b) shows the arrangement of the sensors. FIG. 5 is a diagram for explaining conventional example (2). FIG. 6 is a diagram for explaining conventional example (2). In fig. ■ is a wafer with a resist film formed on its entire surface. 11 is the periphery of the wafer. 2 is a virtual network. 21 is a mesh that overlaps the periphery of the wafer. 22 is the mesh on both sides of the position confirmation point. 31 and 32 are virtual threads forming a virtual network. 41 and 42 are position confirmation points. 51 and 52 are unexposed areas. 61 is the wafer stage. 62 is a rotation motor. 63 is the stand. 64 is a linear pulse smoke in the X direction. 65 is a linear pulse motor 1 in the Y direction, and 66 is an optical lens system. 67 is a light emitting system. 68 is the light receiving system. 71 to 73 are sensors. 81 is the f-hyperactive stage (a) ↑So Sun Moon's Moon 5 ¥ Theory B Moon Picture Man 6 Picture (f 1) + Shi+ Fute14's R theory Rou Picture Man I Picture (Part 2) Ichika

Claims (1)

【特許請求の範囲】 〔1〕全面にレジスト膜の形成されたウェハ(1)の周
縁部(11)を露光するウェハの露光方法において、最
小の露光領域となる単位矩形を定め、該ウェハ全面に該
単位矩形を網目とする仮想網(2)をかけたとした時に
、該ウェハ(1)の周縁部(11)と重なる網目(21
)を網目毎に露光して、該ウェハ(1)の周縁部(11
)の全部を露光することを特徴とするウェハの露光方法
。 〔2〕全面にレジスト膜の形成されたウェハ(1)の周
縁部(11)を露光するウェハの露光方法において、最
小の露光領域となる単位矩形を定め、該ウェハ全面に該
単位矩形を網目とする仮想網(2)をかけたとした時に
、該ウェハ(1)のほぼ中心を通る該仮想網(2)の直
交する2本の仮想糸(31、32)が該ウェハ(1)の
周縁部(11)と交叉する点を位置確認点(41、42
)と定め、該位置確認点(41、42)の両側の網目(
22)を除き該ウェハ(1)の周縁部(11)と重なる
網目(21)を網目毎に露光し、該位置確認点(41、
42)の両側の網目(22)は該位置確認点(41、4
2)の両側に離れるように移動して露光することにより
、該位置確認点(41、42)を含む未露光領域(51
、52)を形成することを特徴とするウェハの露光方法
[Scope of Claims] [1] In a wafer exposure method in which a peripheral portion (11) of a wafer (1) on which a resist film is formed on the entire surface is exposed, a unit rectangle serving as the minimum exposure area is determined, and the entire surface of the wafer is exposed. When a virtual mesh (2) having the unit rectangle as a mesh is applied to the wafer (1), a mesh (21
) is exposed mesh by mesh to expose the peripheral edge (11) of the wafer (1).
) A wafer exposure method characterized by exposing the entire wafer. [2] In a wafer exposure method that exposes the peripheral edge (11) of a wafer (1) on which a resist film is formed on the entire surface, a unit rectangle is determined to be the minimum exposure area, and the unit rectangle is patterned over the entire surface of the wafer. When a virtual net (2) is applied to the wafer (1), two orthogonal virtual threads (31, 32) of the virtual net (2) passing through approximately the center of the wafer (1) are located at the periphery of the wafer (1). The point that intersects the part (11) is the position confirmation point (41, 42).
), and the meshes (
The meshes (21) that overlap with the peripheral edge (11) of the wafer (1) except for the position confirmation points (41, 22) are exposed mesh by mesh.
The meshes (22) on both sides of the position confirmation points (41, 4)
2), the unexposed area (51) including the position confirmation points (41, 42) is exposed.
, 52).
JP1100858A 1989-04-20 1989-04-20 Wafer exposure method Expired - Fee Related JP2752148B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1100858A JP2752148B2 (en) 1989-04-20 1989-04-20 Wafer exposure method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1100858A JP2752148B2 (en) 1989-04-20 1989-04-20 Wafer exposure method

Publications (2)

Publication Number Publication Date
JPH02278814A true JPH02278814A (en) 1990-11-15
JP2752148B2 JP2752148B2 (en) 1998-05-18

Family

ID=14285012

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1100858A Expired - Fee Related JP2752148B2 (en) 1989-04-20 1989-04-20 Wafer exposure method

Country Status (1)

Country Link
JP (1) JP2752148B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04291938A (en) * 1991-03-20 1992-10-16 Ushio Inc Aligner and exposure method for inessential resist on wafer

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6328231A (en) * 1986-07-18 1988-02-05 日立電子エンジニアリング株式会社 Electric source control circuit
JPS6338231A (en) * 1986-08-01 1988-02-18 Fujitsu Ltd Forming method for resist mask
JPS63188938U (en) * 1987-05-28 1988-12-05

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6328231A (en) * 1986-07-18 1988-02-05 日立電子エンジニアリング株式会社 Electric source control circuit
JPS6338231A (en) * 1986-08-01 1988-02-18 Fujitsu Ltd Forming method for resist mask
JPS63188938U (en) * 1987-05-28 1988-12-05

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04291938A (en) * 1991-03-20 1992-10-16 Ushio Inc Aligner and exposure method for inessential resist on wafer

Also Published As

Publication number Publication date
JP2752148B2 (en) 1998-05-18

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