JP2748304B2 - Method of manufacturing press-contact type semiconductor device - Google Patents

Method of manufacturing press-contact type semiconductor device

Info

Publication number
JP2748304B2
JP2748304B2 JP26461594A JP26461594A JP2748304B2 JP 2748304 B2 JP2748304 B2 JP 2748304B2 JP 26461594 A JP26461594 A JP 26461594A JP 26461594 A JP26461594 A JP 26461594A JP 2748304 B2 JP2748304 B2 JP 2748304B2
Authority
JP
Japan
Prior art keywords
semiconductor substrate
jig
insulating
insulating member
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP26461594A
Other languages
Japanese (ja)
Other versions
JPH08107122A (en
Inventor
根三 李
尚博 清水
昌士 由良
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyo Denki Seizo KK
Original Assignee
Toyo Denki Seizo KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyo Denki Seizo KK filed Critical Toyo Denki Seizo KK
Priority to JP26461594A priority Critical patent/JP2748304B2/en
Publication of JPH08107122A publication Critical patent/JPH08107122A/en
Application granted granted Critical
Publication of JP2748304B2 publication Critical patent/JP2748304B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、半導体基板の外周を、
絶縁被覆する半導体素子、特に治具にまつわる欠点を改
良した圧接型半導体素子の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention
The present invention relates to a method for manufacturing a semiconductor device to be insulated and, in particular, a press-contact type semiconductor device in which defects associated with a jig are improved.

【0002】[0002]

【従来の技術】従来の圧接型半導体素子(以下単に半導
体素子という)は、図4に示すように、半導体基板11と
その外周のベベル端面12を全周に渡って被覆するように
形成した絶縁部材13とからなる表面絶縁構造が用いられ
ている。この絶縁部材13は半導体基板11を保護する目的
も有しており、ゴム弾性に富んだ材料である必要があ
る。またこの絶縁部材13は、半導体基板11との密着性が
非常に高いことや、耐湿性或いは耐熱性に非常に優れて
いること等を特徴とする絶縁樹脂を、半導体基板11のベ
ベル端面12に形成した上で、ゴム弾性に富む絶縁部材を
形成するというような多層構造であるものもよく用いら
れている。
2. Description of the Related Art As shown in FIG. 4, a conventional pressure contact type semiconductor device (hereinafter simply referred to as "semiconductor device") is an insulating device formed so as to cover a semiconductor substrate 11 and a bevel end surface 12 on the outer periphery thereof over the entire circumference. A surface insulating structure including the member 13 is used. The insulating member 13 also has a purpose of protecting the semiconductor substrate 11 and needs to be made of a material rich in rubber elasticity. Further, the insulating member 13 is formed by applying an insulating resin, which is characterized by having extremely high adhesion to the semiconductor substrate 11 and being extremely excellent in moisture resistance or heat resistance, to the bevel end surface 12 of the semiconductor substrate 11. A multilayer structure in which an insulating member rich in rubber elasticity is formed after being formed is often used.

【0003】次に、図4に示す従来構造例を得るための
製造工程の一例について図5を用いて説明する。図5は
その一例を示す正面断面図であり、異なる導電型の半導
体層どうしの接合面を少なくとも1個以上有する半導体
基板11を準備する工程を最初に行う。次に、この半導体
基板11を上下から2個の治具14,15で挟み込み、重り16
を上側の治具14上にのせて半導体基板11をセットする工
程を行う。重り16を上側の治具14上にのせる目的は、上
下方向からの圧力により半導体基板11、上下の治具14,
15の三者間の接触を良くして部品間の合わせ目から次の
工程で注入される絶縁樹脂が漏れ出ることを防止するこ
とであるので、必ずしも重り16をのせる方法でなくと
も、例えば上下からネジで締め合わせる方法であっても
全く構わない。そして、次に上側の治具14に設けられた
注入孔14aから液状の絶縁部材を注入する工程と、注入
した絶縁部材を硬化させて絶縁部材13と半導体基板11と
を一体化させる工程を順次行う。その後、半導体基板11
と絶縁部材13とを一体化させた半導体素子を治具14,15
から取り外す工程を行って、図4に示した従来の圧接型
半導体素子の構造例が得られる。この半導体基板11を治
具14,15から取り外す工程に於いては、絶縁部材13と治
具15の表面15aとの間に存在する摩擦力以上の力を、半
導体素子に上下方向から加えなければならないが、絶縁
部材13の材料として一般に用いられる熱硬化型シリコー
ンゴム等の材料は、他の物質との接着性が高いため、絶
縁部材13と治具15の表面15aとの間に存在する摩擦力は
非常に大きくなり、それに伴って取り外しの工程で半導
体素子に加える上下方向の力も非常に大きくなる。
Next, an example of a manufacturing process for obtaining an example of the conventional structure shown in FIG. 4 will be described with reference to FIG. FIG. 5 is a front cross-sectional view showing one example, and a step of preparing a semiconductor substrate 11 having at least one bonding surface between semiconductor layers of different conductivity types is first performed. Next, the semiconductor substrate 11 is sandwiched between two jigs 14 and 15 from above and
Is placed on the upper jig 14 to set the semiconductor substrate 11. The purpose of placing the weight 16 on the upper jig 14 is that the semiconductor substrate 11, the upper and lower jigs 14,
Because it is to prevent the insulating resin injected in the next step from leaking from the joint between the parts by improving the contact between the three members of 15, it is not necessarily a method of putting the weight 16, for example, A method of tightening with screws from above and below may be used at all. Then, a step of injecting a liquid insulating member from an injection hole 14a provided in the upper jig 14 and a step of curing the injected insulating member to integrate the insulating member 13 with the semiconductor substrate 11 are sequentially performed. Do. Then, the semiconductor substrate 11
Jigs 14 and 15
Then, the structure example of the conventional pressure contact type semiconductor device shown in FIG. 4 is obtained. In the step of removing the semiconductor substrate 11 from the jigs 14 and 15, a force higher than the frictional force existing between the insulating member 13 and the surface 15a of the jig 15 must be applied to the semiconductor element from above and below. However, since a material such as a thermosetting silicone rubber generally used as a material of the insulating member 13 has high adhesiveness to other substances, a friction existing between the insulating member 13 and the surface 15a of the jig 15 is present. The force becomes very large, and accordingly, the vertical force applied to the semiconductor element in the removal process becomes very large.

【0004】[0004]

【発明が解決しようとする課題】しかし、図4に示した
従来構造例では、絶縁部材13を成形した後に、半導体基
板11と絶縁部材13とを一体化して成る半導体素子を図5
に示した治具15から取り外す工程が必要となる。一般
に、絶縁部材13と治具15との密着性は高い場合が多く、
この半導体素子を治具15から取り出す際に治具15の表面
15aでの摩擦力が非常に大きくなり、取り出しの際に半
導体素子に加わる上下方向の力も大きくなって半導体素
子が歪む等するため、絶縁部材13に亀裂が入ったり半導
体基板11を損傷したりといった不具合が生じる危険性が
ある。例えば、フッソ樹脂等の材料は絶縁部材13との離
型性が比較的高いので、図5中の治具15の表面にフッソ
樹脂等の材料をコーティングする方法や、治具15の材料
にフッソ樹脂等の材料を用いたりする方法もあるが、上
記問題点は半導体素子の径が大きくなればそれだけ強く
顕われる性格のものである為、完全な解決策とはなりえ
ない。また、半導体素子をスムーズに治具15から取り外
す為に、治具15の表面に離型剤等を塗布することは、半
導体基板11のベベル端面12を汚染する危険性が高く、十
分高い逆耐圧を得られなくなることが考えられるので避
けるべきであり、従来より用いられている治具15から半
導体素子を取り出す工程中に存在する問題点は依然とし
て残ったままである。
However, in the conventional structure shown in FIG. 4, after the insulating member 13 is formed, the semiconductor element formed by integrating the semiconductor substrate 11 and the insulating member 13 is shown in FIG.
The step of removing from the jig 15 shown in FIG. Generally, the adhesion between the insulating member 13 and the jig 15 is often high,
When removing this semiconductor element from the jig 15, the surface of the jig 15
The frictional force at 15a becomes very large, and the vertical force applied to the semiconductor element at the time of taking out also becomes large and the semiconductor element is distorted, so that the insulating member 13 is cracked or the semiconductor substrate 11 is damaged. There is a risk of malfunction. For example, since a material such as a fluororesin has relatively high releasability from the insulating member 13, a method of coating the surface of the jig 15 in FIG. Although there is a method of using a material such as a resin, the above-mentioned problems are more likely to be manifested as the diameter of the semiconductor element becomes larger, and thus cannot be a complete solution. In addition, applying a release agent or the like to the surface of the jig 15 to remove the semiconductor element from the jig 15 smoothly has a high risk of contaminating the bevel end surface 12 of the semiconductor substrate 11 and has a sufficiently high reverse withstand voltage. It should be avoided because it is considered impossible to obtain the semiconductor device, and the problem existing during the process of taking out the semiconductor element from the jig 15 conventionally used remains.

【0005】[0005]

【課題を解決するための手段】つまり、その目的を達成
するための手段は、異なる導電型の半導体層どうしの接
合面を少なくとも1個以上有する半導体基板と、この半
導体基板の外周端面を全周に渡って被覆するように形成
した表面絶縁構造において半導体基板の外周端面より大
きい内径を有する弾性の小さいリング状の絶縁器具を具
備し、前記半導体基板と絶縁器具との間隙を、少なくと
も1層以上の弾性に富んだ絶縁部材により互いに接着す
るように充填して、半導体基板の外周端面全周を絶縁し
たことにある。また、リング状の絶縁器具の内周面に少
なくとも1つ以上の環状の溝を設けることもある。この
ようにして得る半導体素子の製造工程は、前記半導体基
板を準備する工程と、前記半導体基板と前記絶縁器具と
を同心円状に配置して、少なくとも2個以上の治具で上
下から挟み込み液状の前記絶縁部材を注入する準備の工
程と、液状の前記絶縁部材を前記半導体基板の外周部分
に注入する工程と、注入した前記絶縁部材を硬化させて
前記半導体基板と前記絶縁器具と前記絶縁部材とを一体
化させる工程と、該半導体素子を挟み込んだ前述の2個
以上の治具と該半導体素子とを分離して取りはずす工程
とからなる。すなわち、本発明に係わる圧接型半導体素
子では、半導体基板の外周のベベル端面を全周に渡って
被覆する弾性に富んだ絶縁部材の外側に、弾性の小さい
フッソ樹脂等の材料からなる絶縁器具を付加したFW構
造(フラットウェーハ構造)を採用し、更に最外周の絶
縁器具の内壁に凹状部分或いは凸状部分を設ける手法を
採用した。
In order to achieve the object, a semiconductor substrate having at least one junction surface between semiconductor layers of different conductivity types, and an outer peripheral end face of the semiconductor substrate are formed over the entire circumference. A ring-shaped insulating device having a smaller inner diameter than the outer peripheral end surface of the semiconductor substrate in the surface insulating structure formed so as to cover the semiconductor substrate, wherein a gap between the semiconductor substrate and the insulating device is at least one layer or more. In this case, the semiconductor device is filled with the elastic insulating member so as to be bonded to each other to insulate the entire outer peripheral end face. Also, at least one or more annular grooves may be provided on the inner peripheral surface of the ring-shaped insulating device. The manufacturing process of the semiconductor element obtained in this manner includes a process of preparing the semiconductor substrate, a process of arranging the semiconductor substrate and the insulating device concentrically, sandwiching the semiconductor device with at least two or more jigs from above and below, and forming a liquid. A step of preparing to inject the insulating member, a step of injecting the liquid insulating member into an outer peripheral portion of the semiconductor substrate, and curing the injected insulating member to cure the semiconductor substrate, the insulating device, and the insulating member. And a step of separating and removing the two or more jigs sandwiching the semiconductor element and the semiconductor element. That is, in the press-contact type semiconductor device according to the present invention, an insulating device made of a material such as a less elastic fluororesin is provided on the outside of the highly elastic insulating member that covers the entire peripheral surface of the bevel end surface of the semiconductor substrate. The added FW structure (flat wafer structure) was adopted, and a method of providing a concave portion or a convex portion on the inner wall of the outermost insulating device was adopted.

【0006】[0006]

【作用】素子の最外周部に絶縁器具を付加したことによ
って、半導体基板と弾性に富んだ絶縁部材と最外周の弾
性の小さい絶縁器具とが一体化され、従来構造を製作す
る工程の内、治具から半導体素子を取り出す工程におい
て、半導体素子をその上下方向に力を加えずに治具から
取り外すことが出来る。このことによって、従来素子を
治具から取り外す工程中で発生していた不具合は起こら
なくなり、歩留まりの著しい向上を得ることが出来る。
The semiconductor device, the insulating member having high elasticity and the insulating member having low elasticity at the outermost periphery are integrated by adding an insulating device to the outermost peripheral portion of the element. In the step of taking out the semiconductor element from the jig, the semiconductor element can be removed from the jig without applying a vertical force. As a result, the problem that has conventionally occurred during the step of removing the element from the jig does not occur, and the yield can be significantly improved.

【0007】また、一般に弾性の小さい絶縁器具は他の
物質との密着性が高く、半導体素子取扱いの際に最外周
の弾性の小さい絶縁器具が半導体素子から外れてしまう
ことにより、弾性に富んだ絶縁部材や半導体基板に損傷
を与える危険性は少ないけれども、弾性の小さい絶縁器
具の内壁に設けられた凹状部分或いは凸状部分の存在に
よって、弾性の小さい絶縁器具と弾性に富んだ絶縁部材
が全体にわたって良好な接着となる為、半導体素子の取
扱いの際、弾性の小さい絶縁器具が半導体素子から外れ
て弾性に富んだ絶縁部材や、半導体基板に損傷を与える
危険性がほとんどなくなり、信頼性も更に向上する。以
下、本発明の一実施例を、図面に基づいて詳述する。
In general, an insulating device having low elasticity has high adhesion to other substances, and the insulating device having low elasticity on the outermost periphery is detached from the semiconductor element when handling the semiconductor device. Although there is little danger of damaging the insulating member and the semiconductor substrate, the presence of the concave or convex portions provided on the inner wall of the insulating device with low elasticity allows the insulating device with low elasticity and the insulating member with high elasticity as a whole. Good adhesion over the entire surface, there is almost no danger that the insulating device with low elasticity will separate from the semiconductor device and damage the insulating member with high elasticity and the semiconductor substrate when handling the semiconductor device. improves. Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

【0008】[0008]

【実施例】図1はFW構造を適用した圧接型半導体素子
の一実施例を示す構成図である。図1において、1は半
導体基板であり、材料として、Si,SiC,GaAs 等いずれの
半導体材料を用いてもよく、また各種のダイオード、ト
ランジスタ、或いはサイリスタのいずれであっても構わ
ない。いずれにせよ圧接型半導体素子は大電力用に用い
られる場合が多く、その場合、特に、pn接合が露出す
る半導体基板1の端面に傾斜を設けてベベル端面1aを
形成することによって高耐圧を確保している。このベベ
ル端面1aの外側には、ベベル端面1aを保護する目的
と理論限界値に近い耐圧を確保する目的とを兼ねて、ベ
ベル端面1aを全周に渡って覆う形で絶縁部材2が形成
される。この絶縁部材2はゴム弾性に富んでいて外力に
よるストレスを緩和できる材質の物である必要がある。
またこの絶縁部材2は、半導体基板1との密着性が非常
に高いことや耐湿性或いは耐熱性に非常に優れたこと等
を特徴とする絶縁体層をベベル端面1a上に形成した上
で、ゴム弾性に富む絶縁体層を形成するというような多
層構造であっても良い。
FIG. 1 is a structural view showing one embodiment of a pressure contact type semiconductor device to which an FW structure is applied. In FIG. 1, reference numeral 1 denotes a semiconductor substrate, which may be any semiconductor material such as Si, SiC, or GaAs, and may be any of various diodes, transistors, or thyristors. In any case, the pressure contact type semiconductor element is often used for high power. In this case, in particular, a high withstand voltage is ensured by forming a bevel end surface 1a with an inclined end surface of the semiconductor substrate 1 where the pn junction is exposed. doing. Outside the bevel end face 1a, an insulating member 2 is formed so as to cover the bevel end face 1a over the entire circumference for both the purpose of protecting the bevel end face 1a and the purpose of ensuring a pressure resistance close to the theoretical limit value. You. The insulating member 2 needs to be made of a material that is rich in rubber elasticity and can reduce stress due to external force.
The insulating member 2 has an insulating layer formed on the bevel end face 1a, which is characterized by having extremely high adhesion to the semiconductor substrate 1 and having extremely excellent moisture resistance or heat resistance. A multilayer structure in which an insulator layer rich in rubber elasticity is formed may be used.

【0009】本発明の構造では、この絶縁部材2の外側
に、例えばフッ素樹脂等の材料からなる絶縁器具3が存
在する。この絶縁器具3は、シリコーンゴムのような弾
性に富んだ絶縁物ではなく、フッ素樹脂等の弾性の小さ
い絶縁体であるため、絶縁器具3の加工はより精度良く
なされ、それに伴ってシールに組み立てる際の中心合わ
せをより高精度で簡単に行うことが出来る。また、絶縁
器具3の外壁に多樣な加工を施すことによって、小さな
体積で大きな沿面長を持つ形状が得られ、半導体素子の
有効面積を損なわずに高耐圧化することが出来るように
なったりするといった波及効果を持つ。
In the structure of the present invention, an insulating device 3 made of a material such as a fluororesin exists outside the insulating member 2. Since the insulating device 3 is not a highly elastic insulator such as silicone rubber, but an insulator having a low elasticity such as a fluororesin, the processing of the insulating device 3 is performed with higher precision, and as a result, the insulating device 3 is assembled into a seal. The center can be easily adjusted with higher precision. Further, by performing various processes on the outer wall of the insulating device 3, a shape having a large creepage length with a small volume can be obtained, and a high breakdown voltage can be achieved without impairing the effective area of the semiconductor element. It has a ripple effect.

【0010】以下、本発明FW構造の製造工程について
図3を用いて説明する。先ず、異なる導電型の半導体ど
うしの接合面を少なくとも1個以上有する半導体基板1
を準備する工程を行う。次いでこの半導体基板1と絶縁
器具3とを位置合わせを行った上で、2個の治具6,7
で上下から挟み込み、上側の治具6に重り9をのせて絶
縁部材2を成形するための準備工程を行う。この重り9
を上側の治具6上にのせる目的は、上下方向からの圧力
により半導体基板1と絶縁器具3と、上下の治具6,7
の四者間の接触を良くして部品の合わせ目から液状の絶
縁部材が漏れ出することを防止することであるので、必
ずしも重り9をのせる方法でなくとも、例えば上下から
ネジで締め合わせる方法等であっても全く構わない。
また、半導体基板1と絶縁器具3との位置合わせの為
に、治具6或いは治具7に位置合わせ用の目印を付ける
ことや、位置合わせ用の治具を新たに加えることも本発
明の主旨を何等揺るがすものではなく全く問題は無い。
そして、次に上側の治具6に設けられた注入孔8から液
状の絶縁部材を注入する工程と、注入した液状の絶縁部
材を硬化させて、半導体基板1と絶縁部材2と絶縁器具
3とを一体化させる工程を順次行う。その後、一体化し
た半導体素子を治具6或いは治具7から取り外す際、本
発明による構造では半導体基板1と絶縁部材2と絶縁器
具3とが一体化されているため、従来、図5中治具15の
表面15aと絶縁部際13との間に在る大きな摩擦力以上の
大きな力を半導体素子の上下方向に加えることが無いの
に加えて、従来構造に比べて、治具6,7のいずれかと
絶縁部材2との接着面積が小さくなるため、治具6,7
からの取り外しが極めて容易になり、従来半導体素子を
治具から取り外す工程に於いて存在した問題点はほとん
ど解決されている。
Hereinafter, the manufacturing process of the FW structure of the present invention will be described with reference to FIG. First, a semiconductor substrate 1 having at least one bonding surface between semiconductors of different conductivity types
Is performed. Next, after positioning the semiconductor substrate 1 and the insulating device 3, the two jigs 6 and 7 are aligned.
A preparatory process for forming the insulating member 2 with the weight 9 placed on the upper jig 6 is performed. This weight 9
Is placed on the upper jig 6 by applying pressure from above and below to the semiconductor substrate 1, the insulating device 3, and the upper and lower jigs 6, 7.
This is to prevent the liquid insulating member from leaking out from the joint of the parts by improving the contact between the four members, so that it is not always necessary to put the weight 9 on, for example, tightening with screws from above and below It does not matter even if it is a method.
In addition, in order to align the semiconductor substrate 1 and the insulating device 3, a mark for alignment may be provided on the jig 6 or the jig 7, or a new jig for alignment may be added. It does not shake the gist at all and there is no problem at all.
Then, a step of injecting a liquid insulating member from an injection hole 8 provided in the upper jig 6, and curing the injected liquid insulating member so that the semiconductor substrate 1, the insulating member 2, the insulating device 3, Are sequentially performed. Thereafter, when the integrated semiconductor element is removed from the jig 6 or the jig 7, the semiconductor substrate 1, the insulating member 2, and the insulating device 3 are integrated in the structure according to the present invention. In addition to not applying a large force greater than the large frictional force existing between the surface 15a of the tool 15 and the insulating portion 13 in the vertical direction of the semiconductor element, the jigs 6, 7 Since the bonding area between any one of them and the insulating member 2 becomes small, the jigs 6 and 7
Removal of the semiconductor element from the jig is extremely easy, and the problems that have conventionally been encountered in the step of removing the semiconductor element from the jig have been almost solved.

【0011】また、絶縁器具3の内壁面、即ち絶縁部材
2との接着面には、絶縁器具3に凹状部分3aを設け、
絶縁器具3と絶縁部材2との密着を良くしている。この
ことによって、半導体素子を取り扱う際に絶縁部材2と
絶縁器具3とが離れてしまって、半導体基板1や絶縁部
材2に損傷を与えてしまうことが防止され、信頼性がよ
り高められる。この凹状部分3aの形状としては、図2
(a)〜(f)に示すように、多種類の形状が適用出来
る。つまり具体例として、図(a)は各溝の凹形状3a
である例、図(b)はクサビが打ち込まれるような凸形
状3bの例、図(c)は球面状の凹形状3cである例、
図(d)は凹形状も凸形状も設けない例、図(e)角型
の突起形状3dである例、図(f)はクサビ状の突起を
有する形状3e例である。
Further, a concave portion 3a is provided on the inner wall surface of the insulating device 3, that is, on the bonding surface with the insulating member 2,
The close contact between the insulating member 3 and the insulating member 2 is improved. This prevents the insulating member 2 and the insulating device 3 from being separated from each other when handling the semiconductor element, thereby preventing the semiconductor substrate 1 and the insulating member 2 from being damaged, thereby further improving reliability. The shape of the concave portion 3a is shown in FIG.
As shown in (a) to (f), various types of shapes can be applied. That is, as a specific example, FIG.
(B) is an example of a convex shape 3b into which a wedge is driven, FIG. (C) is an example of a spherical concave shape 3c,
FIG. 4D shows an example in which neither a concave shape nor a convex shape is provided, FIG. 5E shows an example in which a rectangular projection shape 3d is provided, and FIG. 5F shows an example in which a shape 3e having wedge-shaped projections is provided.

【0012】[0012]

【発明の効果】以上説明したように本発明によれば、治
具から半導体素子を取り出す工程において、従来半導体
素子に加えられていた上下方向の力を加えず非常に簡単
に半導体素子を治具から取り外せるようになるため、従
来半導体素子を治具から取り外す際に存在していた、弾
性に富んだ絶縁部材に亀裂が入ったり、半導体基板を歪
めてしまったり、また損傷したりするといった問題を解
決することが出来る。
As described above, according to the present invention, in the step of taking out the semiconductor element from the jig, the jig can be very easily attached without applying the vertical force applied to the conventional semiconductor element. To remove the semiconductor element from the jig, which has caused cracks in the highly elastic insulating member, distorted the semiconductor substrate, and damage. Can be solved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例を示す構成図である。FIG. 1 is a configuration diagram showing one embodiment of the present invention.

【図2】本発明の絶縁器具の各種の形状を示す説明図で
ある。
FIG. 2 is an explanatory view showing various shapes of the insulating device of the present invention.

【図3】本発明の圧接型半導体素子を得る製造方法を説
明する説明図である。
FIG. 3 is an explanatory view illustrating a manufacturing method for obtaining a pressure contact type semiconductor device of the present invention.

【図4】従来の一例を示す構造図である。FIG. 4 is a structural diagram showing an example of the related art.

【図5】従来の圧接型半導体素子を得る製造方法を説明
する説明図である。
FIG. 5 is an explanatory view for explaining a manufacturing method for obtaining a conventional pressure contact type semiconductor element.

【符号の説明】[Explanation of symbols]

1 半導体基板 2 絶縁部材 3 絶縁器具 1a ベベル端面 3a 凹形状 3b 凹形状 3c 凹形状 3d 突起形状 3e 突起形状 6 治具 7 治具 8 注入孔 9 重り Reference Signs List 1 semiconductor substrate 2 insulating member 3 insulating device 1a bevel end surface 3a concave shape 3b concave shape 3c concave shape 3d projection shape 3e projection shape 6 jig 7 jig 8 injection hole 9 weight

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 半導体基板の外周を、絶縁被覆する半導
体素子において、治具と、半導体基板と、絶縁器具から
なり、治具は、上下を重ね合わせて一体とするものであ
って、相対向する部分に環状突起部並びにこの環状突起
部の外側に絶縁部材を注入する孔を設け、更に上下の治
具を重ね合わせたときに半導体基板の外周部分に空間が
出来るよう形成したものであり、絶縁器具は、機械加工
が出来、且つ弾性変化の小さい材質の環状部材で、しか
も半導体基板を前記治具で挟持したとき、前記空間が密
閉されるような半導体基板外周近傍に配置されたもので
あり、絶縁部材が治具の孔から注入され、これが硬化し
て半導体基板の外周に密着した絶縁体を形成し、この絶
縁体に絶縁器具が固着されているよう構成したことを特
徴とする圧接型半導体素子の製造方法。
1. A semiconductor device for insulatingly covering the outer periphery of a semiconductor substrate, comprising a jig, a semiconductor substrate, and an insulating device, wherein the jig is vertically integrated to be integral with each other. A hole for injecting an insulating member outside the annular protrusion and an annular protrusion at the portion to be formed, and further formed such that a space is formed in the outer peripheral portion of the semiconductor substrate when the upper and lower jigs are overlapped, The insulating device is an annular member made of a material that can be machined and has a small change in elasticity, and is disposed near the outer periphery of the semiconductor substrate so that the space is sealed when the semiconductor substrate is sandwiched by the jig. An insulation member is injected from a hole in the jig, and is cured to form an insulator closely adhered to the outer periphery of the semiconductor substrate, and an insulating device is fixed to the insulator. Mold semiconductive Method for manufacturing a body element.
【請求項2】 前記絶縁器具の内径側に、少なくとも一
箇所以上の凹又は凸部を形成せしめたことを特徴とする
請求項1記載の圧接型半導体素子の製造方法。
2. The method according to claim 1, wherein at least one concave or convex portion is formed on the inner diameter side of the insulating device.
【請求項3】 異なるpn接合の導電型又は不純物濃度
の半導体層どうしの接合面を、少なくとも1個以上有す
る半導体基板とする請求項1又は2記載の圧接型半導体
素子の製造方法。
3. The method according to claim 1, wherein the semiconductor substrate has at least one junction surface between semiconductor layers having different pn junction conductivity types or impurity concentrations.
JP26461594A 1994-10-03 1994-10-03 Method of manufacturing press-contact type semiconductor device Expired - Fee Related JP2748304B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26461594A JP2748304B2 (en) 1994-10-03 1994-10-03 Method of manufacturing press-contact type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26461594A JP2748304B2 (en) 1994-10-03 1994-10-03 Method of manufacturing press-contact type semiconductor device

Publications (2)

Publication Number Publication Date
JPH08107122A JPH08107122A (en) 1996-04-23
JP2748304B2 true JP2748304B2 (en) 1998-05-06

Family

ID=17405795

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26461594A Expired - Fee Related JP2748304B2 (en) 1994-10-03 1994-10-03 Method of manufacturing press-contact type semiconductor device

Country Status (1)

Country Link
JP (1) JP2748304B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5054755B2 (en) * 2009-12-28 2012-10-24 株式会社日立製作所 Semiconductor device

Also Published As

Publication number Publication date
JPH08107122A (en) 1996-04-23

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