JPS60103649A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60103649A JPS60103649A JP58210798A JP21079883A JPS60103649A JP S60103649 A JPS60103649 A JP S60103649A JP 58210798 A JP58210798 A JP 58210798A JP 21079883 A JP21079883 A JP 21079883A JP S60103649 A JPS60103649 A JP S60103649A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- case
- heat sink
- substrate
- heat dissipating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1301—Thyristor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は半導体装置に係り、特にパワーモジュールの樹
脂封止構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device, and particularly to a resin-sealed structure for a power module.
近年パワー半導体素子等の回路素子を絶縁基板上に固定
し、結線して回路としての単位機能を持たせた所謂パワ
ーモジュールの利用が広まっている。中でも平面寸法が
３ｃｒｎ程度の小型のものは全体を樹脂で１体モールド
した構造が採られているが、平面寸法の一辺が１０ｃ１
ｎ程度の比較的大型のものは第１図、第２図で示すよう
な構造が採られている。In recent years, the use of so-called power modules, in which circuit elements such as power semiconductor elements are fixed on an insulating substrate and wired together to provide a unit function as a circuit, has become widespread. Among them, the small ones with a planar dimension of about 3 crn have a structure in which the whole is molded as a single piece of resin, but the planar dimension of one side is 10 crn.
Comparatively large ones of about n size have a structure as shown in FIGS. 1 and 2.
両図において、放熱板１には、金属板２、絶縁基板３、
金属板４を介して回路素子としてダイオード５ａ１ゲー
トターンオフサイリスタ５ｂが固定されている。アノー
ドリード６ａが金属板４に固着され、ゲートリード、カ
ソードリード６ｂ。In both figures, the heat sink 1 includes a metal plate 2, an insulating substrate 3,
A diode 5a1 and a gate turn-off thyristor 5b are fixed as circuit elements via a metal plate 4. An anode lead 6a is fixed to the metal plate 4, a gate lead, and a cathode lead 6b.
６Ｃは金属板４上の絶縁板７に固着されており、ダイオ
ード５ａ、ゲートターンオフサイリスタ５ｂの上面はボ
ンデインワイヤ８８〜８Ｃにより、ゲートリード６ａ、
カソードリード６Ｃと接続されている。放熱板１上には
ケース９が設けられ、ケース９内にはゲル状樹脂１０ａ
と硬質樹脂１０ｂが注入硬化され、ダイオード５ａ、ゲ
ートターンオフサイリスタ５ｂを封止している。6C is fixed to the insulating plate 7 on the metal plate 4, and the upper surfaces of the diode 5a and the gate turn-off thyristor 5b are connected to the gate leads 6a,
It is connected to the cathode lead 6C. A case 9 is provided on the heat sink 1, and inside the case 9 is a gel-like resin 10a.
A hard resin 10b is injected and hardened to seal the diode 5a and gate turn-off thyristor 5b.
ダイオード５ａとゲートターンオフサイリスタ５ｂはア
ノードリード６ａ、カソードリード６０間で逆並列接続
されている。金属板４は画素子５ａ、５ｂの共通電極板
となっており、ゲル状樹脂１０ａとしてシリコーン樹脂
、硬質樹脂１０ｂとしてエポキシ樹脂が用いられている
。The diode 5a and the gate turn-off thyristor 5b are connected in antiparallel between the anode lead 6a and the cathode lead 60. The metal plate 4 serves as a common electrode plate for the pixel elements 5a and 5b, and silicone resin is used as the gel-like resin 10a, and epoxy resin is used as the hard resin 10b.
ゲル状樹脂１０ａは内部応力により画素子５ａ。The gel-like resin 10a is attached to the pixel element 5a due to internal stress.
５ｂが破損することを防ぐために用いられているが、一
般に水分の透過性が高く、ゲル状樹脂１０ａが放熱板１
に接している第１図の例では耐湿試験あるいはプレッシ
ャークツカー試験を行うと、放熱板１とケース９、ゲル
状樹脂１０ａの界面から水分が浸入して、絶縁基板３の
絶縁耐圧や、画素子の阻止耐圧を低下させる問題があっ
た。第２図の例ではこのような問題を回避するために硬
質樹脂１０ｂを放熱板１に接触させ、強固に接着してい
る。Although it is used to prevent the heat dissipation plate 10 from being damaged, the gel-like resin 10a is generally highly permeable to moisture.
In the example shown in FIG. 1, when a moisture resistance test or pressure tester is performed, moisture infiltrates from the interface between the heat sink 1, the case 9, and the gel-like resin 10a, and the dielectric strength of the insulating substrate 3 and the pixel There was a problem of lowering the blocking voltage of the child. In the example shown in FIG. 2, in order to avoid such a problem, the hard resin 10b is brought into contact with the heat sink 1 and firmly adhered thereto.
放熱板１として銅を用いた場合、その熱膨張係数は１６
Ｘ １ ｏ−”／ｃで、エポキシ樹脂ｉｏｂは２６Ｘ
１０−＠／Ｃと差があるため、エポキシ樹脂１０ｂの注
入硬化後の収縮により、放熱板１が凸状になるよう全体
的に反ってしまう。極端な例では放熱板１の中央と周辺
で反りが０．４ｍ＋ｎもあり、放熱板１とこれを取付け
る支持部材の間の熱抵抗が大きくなって、使用不可能と
なる。また、エポキシ樹脂１０ｂ内の内部応力は太きい
ため、熱衝撃試験や温度サイクル試験を行うと、放熱板
１とエポキシ樹脂１０ｂの接着がはがれ、かえって、水
分が浸入することが確認された。When copper is used as the heat sink 1, its thermal expansion coefficient is 16
X 1 o-”/c, epoxy resin iob is 26X
10-@/C, the heat dissipating plate 1 is warped as a whole to become convex due to shrinkage of the epoxy resin 10b after injection hardening. In an extreme example, the heat sink 1 is warped by as much as 0.4 m+n at the center and periphery, and the thermal resistance between the heat sink 1 and the support member to which it is attached increases, making it unusable. Further, since the internal stress within the epoxy resin 10b is large, it was confirmed that when a thermal shock test or a temperature cycle test was performed, the adhesive between the heat sink 1 and the epoxy resin 10b was peeled off, and moisture entered instead.
放熱板１の反りは、第２図の構造を採るかぎシにおいて
銅とエポキシ樹脂の組合せに係らず、概その材料の組合
せにおいて生じるものである。Warpage of the heat sink 1 generally occurs due to the combination of materials in the lock having the structure shown in FIG. 2, regardless of the combination of copper and epoxy resin.
本発明の目的は、放熱板に殆んど反シを生ぜず、また、
耐湿性を備えた樹脂封止型の半導体装置を提供すること
である。The object of the present invention is to cause almost no damage to the heat sink, and
An object of the present invention is to provide a resin-sealed semiconductor device having moisture resistance.
上記目的を達成する本発明の特徴とするところは、放熱
板上の絶縁基板とケースの間に絶縁基板とほぼ同じ厚さ
で第一の硬質樹脂を設け、次にケースの中程までゲル状
樹脂を設けて回路素子を覆い、更にケースの上端部まで
第二の硬質樹脂を設けたことにある。A feature of the present invention that achieves the above object is that a first hard resin is provided between the insulating substrate on the heat sink and the case with approximately the same thickness as the insulating substrate, and then a gel-like resin is provided to the middle of the case. The reason is that a resin is provided to cover the circuit elements, and a second hard resin is further provided up to the upper end of the case.
第３図は本発明の一実施例を示しており、第１図、第２
図に示したものと同一物、相当物には同一符号を付けで
ある。FIG. 3 shows an embodiment of the present invention, and FIG.
Components that are the same or equivalent to those shown in the figures are given the same reference numerals.
第３図において、１０Ｃは本発明になる硬質樹脂で、放
熱板１上の絶縁基板３とケース９の間に絶縁基板３とほ
ぼ同じ厚さに設けられたものである。実施例では金属板
２があるため、金属板２の厚さも持たせである。硬質樹
脂１０Ｃは硬質樹脂１０ｂと同様エポキシ樹脂を用いた
が、放熱板１との接着性の良いものであれば、異種のも
のでも良い。ダイオード５ａやゲートターンオフサイリ
スタ５ｂへの内部応力を与えないようにするため、硬質
樹脂１０ｃは金属板４上にまでは設けない方が良い。ゲ
ル状樹脂１０ａはケース９内の中程まで注入し、ダイオ
ード５ａやゲートターンオアサイリスタ５ｂがすつかｂ
ｍわれるようにする。最後に硬質樹脂１０ｂを注入し硬
化させる。In FIG. 3, 10C is a hard resin according to the present invention, which is provided between the insulating substrate 3 on the heat sink 1 and the case 9 to have almost the same thickness as the insulating substrate 3. In the embodiment, since the metal plate 2 is provided, the thickness of the metal plate 2 is also determined. Although epoxy resin is used as the hard resin 10C like the hard resin 10b, a different type of resin may be used as long as it has good adhesion to the heat sink 1. In order to avoid applying internal stress to the diode 5a and the gate turn-off thyristor 5b, it is better not to provide the hard resin 10c on the metal plate 4. The gel-like resin 10a is injected to the middle of the case 9, and the diode 5a and gate turn-or-thyristor 5b are completely filled.
Make sure to get hurt. Finally, hard resin 10b is injected and hardened.
第４図は本発明の他の実施例を示しており、ダイオード
５ａ、ゲートターンオフサイリスタ５ｂはそれぞれ放熱
板１上の互に分離した金属板２ａ。FIG. 4 shows another embodiment of the present invention, in which a diode 5a and a gate turn-off thyristor 5b are respectively mounted on metal plates 2a separated from each other on a heat sink 1.
２ｂ、絶縁基板３ａ、３ｂ、金属板４ａ、４ｂ上に固着
され、アノードリード６ａは金属板４ａ上にあって、ボ
ンディングワイヤ８ｄがアノードリード６ａと金属板４
ｂを接続している。ゲートリード６ｂ、カソードリード
６Ｃは金属板４ｂ上の絶縁基板７に設けられている。こ
の実施例ではケース９の上端に蓋１１が設けられており
、各り−ド６ａ〜６Ｃは蓋１１から導出される。2b, insulating substrates 3a, 3b, and metal plates 4a, 4b, the anode lead 6a is on the metal plate 4a, and the bonding wire 8d is connected between the anode lead 6a and the metal plate 4.
b is connected. The gate lead 6b and the cathode lead 6C are provided on the insulating substrate 7 on the metal plate 4b. In this embodiment, a lid 11 is provided at the upper end of the case 9, and each of the leads 6a to 6C is led out from the lid 11.
以上の実施例で示されるように、本発明によれば絶縁基
板３．３ａ、３ｂ上のダイオード５ａ。As shown in the above embodiments, according to the invention a diode 5a on an insulating substrate 3.3a, 3b.
ケートターンオフサイリスタ５ｂは全周を接着性の良い
硬質樹脂で封止されているため、水分の浸入は困難で、
画素子５ａ、５ｂの耐圧低下、絶縁基板３．３ａ、３ｂ
の絶縁耐圧の低下はない。そして、硬質樹脂１０ｂは放
熱板１に接していないから、硬質樹脂１０ｂの熱収縮に
よる応力はゲル状樹脂１０ａに吸収されてしまい、放熱
板１に伝わらない。硬質樹脂１０ｃが放熱板１に固着し
ているが、薄くされているため、放熱板１は殆んで、反
シを生じない。硬質樹脂１０ｃとしてエポキシ樹脂を用
い、絶縁基板３，３ａ、３ｂを取囲んだ結果、放熱板１
と１０ＣｒＩＴの長さで接１〜ておシ１、厚さが２ｒｒ
ｍで、放熱板は銅製で厚さが３．２＃である時、放熱板
１０反りは０．０５闘であった。一般に放熱板１の反り
は０．２龍が限界とされており、０、１ ｗａｒ＋程度
では使用を許されているので、０．０５鰭の反りは殆ん
ど反シが無いと云える。The entire circumference of the turn-off thyristor 5b is sealed with a hard resin with good adhesive properties, so it is difficult for moisture to enter.
Decreased breakdown voltage of pixel elements 5a, 5b, insulating substrates 3.3a, 3b
There is no decrease in dielectric strength voltage. Since the hard resin 10b is not in contact with the heat sink 1, stress due to thermal contraction of the hard resin 10b is absorbed by the gel-like resin 10a and is not transmitted to the heat sink 1. Although the hard resin 10c is fixed to the heat sink 1, since it is made thin, the heat sink 1 hardly causes warping. As a result of using epoxy resin as the hard resin 10c and surrounding the insulating substrates 3, 3a, and 3b, the heat sink 1
The length of 10CrIT is 1 to 1, and the thickness is 2rr.
When the heat sink was made of copper and had a thickness of 3.2 mm, the warpage of the heat sink 10 was 0.05 mm. Generally, the limit for the warpage of the heat dissipation plate 1 is 0.2 degrees, and it is allowed to be used at around 0.1 war+, so it can be said that there is almost no warpage of 0.05 degrees.
このように反りが少ないのは、硬質樹脂１０ｃが放熱板
１と接しているにせよ、厚さが薄く、内部応力が小さい
ためである。そして放熱板１を湾曲させると云うより、
硬質樹脂１０Ｃが熱収縮しようとしても、放熱板１の抗
力が太きいため、かえって、硬質樹脂１０Ｃが伸びた状
態になっている。The reason why there is so little warpage is that even though the hard resin 10c is in contact with the heat sink 1, its thickness is thin and the internal stress is small. And rather than curve the heat sink 1,
Even if the hard resin 10C tries to shrink due to heat, the resistance of the heat sink 1 is strong, so the hard resin 10C ends up being stretched.
以上の実施例では、回路素子として、ダイオード５ａと
ゲートターンオフサイリスタ５ｂのみ°を（７）
示したが、本発明はこれに限定されるものではなく、抵
抗、コンデンサ、通常のサイリスタ、トランジスタ等各
種の回路素子を用い、回路を構成するだめに、絶縁基板
３．３ａ、ａｂ上に所定の金鵬配線膜を設けて、各配線
喚問にこれら回路素子を固定させるような混成集積回路
等にも適用可能である。In the above embodiment, only the diode 5a and the gate turn-off thyristor 5b are shown as (7) as circuit elements, but the present invention is not limited to this, and various types such as resistors, capacitors, ordinary thyristors, transistors, etc. It is also applicable to hybrid integrated circuits, etc., in which circuit elements are used, and a predetermined metal wiring film is provided on the insulating substrates 3.3a and 3.ab to form a circuit, and these circuit elements are fixed to each wiring board. It is possible.
以上述べたように、本発明によれば、放熱板に殆んど反
りがなく、耐湿性を備えた樹脂刺止型の半導体装置を得
ることができる。As described above, according to the present invention, it is possible to obtain a resin-inserted semiconductor device with a heat sink having almost no warpage and moisture resistance.
第１図、第２図は従来の半導体装置の縦断面図、第３図
、第４図は本発明の異なる実施例になる半導体装置を示
しておシ、（ａ）は縦断面図、（ｂ）はゲル状樹脂、第
二の硬質樹脂を除いた状態での平面図である。
１・・・放熱板、２．４−・・金属板、３，３ａ、３ｂ
。
７・・・絶縁基板、５ａ、５ｂ・・・回路素子、６ａ〜
６Ｃ・・・リード、８ａ〜８ｄ・・・ポンディングワイ
ヤ、（８）
９・・・ケース、１０ ａ ・・・ゲル状樹脂、１０
ｂ 、 １０ｃ・・・硬質樹脂。
代理人 弁理士 高橋明夫
Ｙ１■
Ｙ２図
珊３図
（Ｉ））
１４図 ６６
（１））1 and 2 are longitudinal sectional views of a conventional semiconductor device, FIGS. 3 and 4 show semiconductor devices according to different embodiments of the present invention, and (a) is a longitudinal sectional view; b) is a plan view with the gel-like resin and the second hard resin removed. 1... Heat sink, 2.4-... Metal plate, 3, 3a, 3b
. 7... Insulating substrate, 5a, 5b... Circuit element, 6a~
6C...Lead, 8a-8d...Ponding wire, (8) 9...Case, 10a...Gel-like resin, 10
b, 10c...hard resin. Agent Patent Attorney Akio Takahashi Y1■ Y2 Diagram 3 (I)) Figure 14 66 (1))
Claims (1)
の放熱板上に絶縁基板を介して回路素子が固定され、ケ
ースから回路素子へのリードが導出され、ケース内に樹
脂が封止される半導体装置において、樹脂は、絶縁基板
とほぼ同じ厚さで絶縁基板とケースの間の放熱板上に封
止された第一の硬質樹脂層と、回路素子を覆う厚さでケ
ース内全面に封止されたゲル状樹脂層および、ゲル状樹
脂層上にケースの上端部までケース内全面に封止された
第二の硬質樹脂層からなることを特徴とする半導体装置
。1. A case is fixed on a metal heat sink, a circuit element is fixed on the heat sink inside the case via an insulating substrate, leads are led from the case to the circuit element, and a resin is sealed inside the case. In the semiconductor device that is manufactured, the resin is applied to the first hard resin layer, which is approximately the same thickness as the insulating substrate and sealed on the heat sink between the insulating substrate and the case, and the entire inside of the case with a thickness that covers the circuit elements. 1. A semiconductor device comprising: a gel-like resin layer sealed with a gel-like resin layer; and a second hard resin layer sealed over the gel-like resin layer over the entire inside of the case up to the upper end of the case.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58210798A JPS60103649A (en) | 1983-11-11 | 1983-11-11 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58210798A JPS60103649A (en) | 1983-11-11 | 1983-11-11 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60103649A true JPS60103649A (en) | 1985-06-07 |
| JPS6361779B2 JPS6361779B2 (en) | 1988-11-30 |
Family
ID=16595304
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58210798A Granted JPS60103649A (en) | 1983-11-11 | 1983-11-11 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60103649A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4987478A (en) * | 1990-02-20 | 1991-01-22 | Unisys Corporation | Micro individual integrated circuit package |
| EP0645812A1 (en) * | 1993-09-21 | 1995-03-29 | Fuji Electric Co., Ltd. | Resin-sealed semiconductor device |
| US5408128A (en) * | 1993-09-15 | 1995-04-18 | International Rectifier Corporation | High power semiconductor device module with low thermal resistance and simplified manufacturing |
-
1983
- 1983-11-11 JP JP58210798A patent/JPS60103649A/en active Granted
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4987478A (en) * | 1990-02-20 | 1991-01-22 | Unisys Corporation | Micro individual integrated circuit package |
| US5408128A (en) * | 1993-09-15 | 1995-04-18 | International Rectifier Corporation | High power semiconductor device module with low thermal resistance and simplified manufacturing |
| EP0645812A1 (en) * | 1993-09-21 | 1995-03-29 | Fuji Electric Co., Ltd. | Resin-sealed semiconductor device |
| US5539253A (en) * | 1993-09-21 | 1996-07-23 | Fuji Electric Co., Ltd. | Resin-sealed semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6361779B2 (en) | 1988-11-30 |
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