JPH06151657A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH06151657A JPH06151657A JP32240492A JP32240492A JPH06151657A JP H06151657 A JPH06151657 A JP H06151657A JP 32240492 A JP32240492 A JP 32240492A JP 32240492 A JP32240492 A JP 32240492A JP H06151657 A JPH06151657 A JP H06151657A
- Authority
- JP
- Japan
- Prior art keywords
- alumina layer
- chip
- main surface
- insulating film
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は放熱体（ヒートシンク）
を備えた半導体装置に関する。FIELD OF THE INVENTION The present invention relates to a heat sink.
The invention relates to a semiconductor device.
【０００２】[0002]
【従来の技術及び発明が解決しようとする課題】半導体
チップが固着されたリードフレームとヒートシンクとを
組み合せたものを樹脂封止して半導体装置に形成するこ
とは公知である。この種の半導体装置ではリードフレー
ムをヒートシンクから絶縁しなければならない。例え
ば、この絶縁は特開昭６１−２４８５３８号公報に記載
されているようにリードフレームとヒートシンクとを金
型内に離間配置させ、両者の間に樹脂を注入することで
達成できる。しかしながら、この方法ではヒートシンク
とリードフレームとの間に樹脂が良好に注入されるよう
に両者の間隔を０．５ｍｍ以上のように比較的大きく設
定しなければならず、この絶縁層によって放熱効果が良
好に得られないという欠点があった。また、特公平４−
１５０２号公報に記載されているようにヒートシンクの
上面全体に絶縁層を予め設け、更にこの絶縁層の上に銅
層を設けたものを用意し、銅層にリードフレームを半田
付けして半導体装置を構成する方法がある。この方法に
よれば絶縁層を比較的薄く形成することができる。しか
しながら、銅層にリードフレームを固着するための半田
層はあまり薄くできないし、また半田層中に気泡等が発
生することがあり、やはり十分な放熱効果を得ることが
できない。また、製造工程が複雑になり、且つ絶縁層の
信頼性に問題がある。2. Description of the Related Art It is known that a combination of a lead frame having a semiconductor chip fixed thereto and a heat sink is resin-sealed to form a semiconductor device. In this type of semiconductor device, the lead frame must be insulated from the heat sink. For example, this insulation can be achieved by disposing a lead frame and a heat sink in a mold with a space therebetween and injecting a resin between them, as described in JP-A-61-248538. However, in this method, the distance between the heat sink and the lead frame must be set relatively large, such as 0.5 mm or more, so that the resin can be injected well between the heat sink and the lead frame. There was a drawback that it could not be obtained well. In addition,
As described in Japanese Patent Publication No. 1502, an insulating layer is previously provided on the entire upper surface of a heat sink, and a copper layer is further provided on the insulating layer. A lead frame is soldered to the copper layer to solder the semiconductor device. There is a way to configure. According to this method, the insulating layer can be formed relatively thin. However, the solder layer for fixing the lead frame to the copper layer cannot be made very thin, and bubbles or the like may occur in the solder layer, so that a sufficient heat dissipation effect cannot be obtained. In addition, the manufacturing process is complicated and the reliability of the insulating layer is problematic.
【０００３】そこで、本発明の目的は比較的簡単に製作
することが可能であり且つ高い信頼性及び良好な放熱性
を有する半導体装置及びその製造方法を提供することに
ある。Therefore, an object of the present invention is to provide a semiconductor device which can be manufactured relatively easily, has high reliability and excellent heat dissipation, and a method for manufacturing the same.
【０００４】[0004]
【課題を解決するための手段】上記目的を達成するため
の本発明は、半導体チップと、一方の主面に前記半導体
チップが固着された導電性を有するチップ支持体と、前
記半導体チップを外部回路に接続するための外部リード
と、前記半導体チップの熱を放出するために前記チップ
支持体の他方の主面に対向配置された放熱体と、前記チ
ップ支持体と前記放熱体との間に配置された絶縁膜とを
備え、前記放熱体がアルミニウム板とこのアルミニウム
板の一方の主面上に形成されたアルミナ層とから成り、
前記絶縁膜が前記アルミナ層と前記チップ支持体とを接
着する材料から成る半導体装置に係わるものである。ま
た、製造方法の発明は、半導体チップが一方の主面に固
着されたチップ支持体と外部リードとを有するリードフ
レームを用意すると共に、アルミニウム板とこのアルミ
ニウム板の一方の主面に形成されたアルミナ層とから成
る放熱板を用意し、前記アルミナ層の主面のほぼ全部に
粘着性を有する絶縁性接着材を塗布し、前記絶縁性接着
材によって前記アルミナ層の上に前記チップ支持体を接
着し、前記絶縁性接着材を硬化して前記アルミナ層に前
記チップ支持体を固着すると共に絶縁膜を得る半導体装
置の製造方法に係わるものである。SUMMARY OF THE INVENTION To achieve the above object, the present invention provides a semiconductor chip, a conductive chip support having the semiconductor chip fixed to one main surface, and the semiconductor chip externally. Between an external lead for connecting to a circuit, a radiator disposed opposite to the other main surface of the chip support for radiating heat of the semiconductor chip, and between the chip support and the radiator An insulating film is arranged, the heat radiator comprises an aluminum plate and an alumina layer formed on one main surface of the aluminum plate,
The present invention relates to a semiconductor device in which the insulating film is made of a material that bonds the alumina layer and the chip support. Further, in the invention of the manufacturing method, a lead frame having a chip support in which a semiconductor chip is fixed to one main surface and external leads is prepared, and an aluminum plate and one main surface of the aluminum plate are formed. A heat dissipation plate composed of an alumina layer is prepared, and an insulating adhesive material having adhesiveness is applied to almost the entire main surface of the alumina layer, and the chip support is provided on the alumina layer by the insulating adhesive material. The present invention relates to a method for manufacturing a semiconductor device in which an insulating film is obtained by adhering and curing the insulating adhesive to fix the chip support to the alumina layer.
【０００５】[0005]
【発明の作用及び効果】請求項１の発明によれば、アル
ミナ層が絶縁を低下させるような孔を有していたとして
も、絶縁膜によって絶縁が強化されているので、チップ
支持体とアルミニウム板との間の絶縁を確実に達成する
ことができる。また、絶縁膜は接着材としても機能して
いるので、チップ支持体の固着のために更に別の接着材
を使用することが不要になり、放熱性の低下を防ぐこと
ができる。請求項２の発明によれば、絶縁性接着材でア
ルミナ層上にチップ支持体を仮固着するので、リードフ
レームを使用した半導体装置の製造を容易に達成するこ
とができる。According to the first aspect of the present invention, even if the alumina layer has pores that lower the insulation, the insulation is reinforced by the insulation film. The insulation between the plates can be reliably achieved. Further, since the insulating film also functions as an adhesive, it is not necessary to use another adhesive for fixing the chip support, and it is possible to prevent deterioration of heat dissipation. According to the second aspect of the invention, the chip support is temporarily fixed on the alumina layer with the insulating adhesive, so that the semiconductor device using the lead frame can be easily manufactured.
【０００６】[0006]
【実施例】次に、図１〜図４を参照して本発明の一実施
例に係わる樹脂封止型の電力用半導体装置及びその製造
方法を説明する。図１に示す電力用半導体装置は、トラ
ンジスタチップ及びＩＣチップから成る複数個の半導体
チップ１と、リードフレームに基づいて得られた金属板
からなる複数のチップ支持体２と、外部リード３と、内
部接続導体４及び５と、アルミニウム板６ａとアルミナ
層６ｂとから成る放熱体即ちヒートシンク６と、接着材
として機能している絶縁膜７と、絶縁物封止体即ち樹脂
封止体８とを備えている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A resin-sealed power semiconductor device according to an embodiment of the present invention and a method of manufacturing the same will now be described with reference to FIGS. The power semiconductor device shown in FIG. 1 includes a plurality of semiconductor chips 1 composed of transistor chips and IC chips, a plurality of chip supports 2 composed of a metal plate obtained based on a lead frame, and external leads 3. The internal connection conductors 4 and 5, the heat radiator or heat sink 6 composed of the aluminum plate 6a and the alumina layer 6b, the insulating film 7 functioning as an adhesive, and the insulator sealing body or resin sealing body 8 are provided. I have it.
【０００７】図１の半導体装置を製造するには、まず図
２に示すリードフレーム９を用意する。このリードフレ
ーム９は、複数のチップ支持体２と、支持体２の配列方
向に並置した多数の外部リード３と、板状接続導体５
と、細条１０、１１、１２と、連結部１３とを有し、厚
さ約０．５ｍｍの銅板を打抜いて形成される。図２には
リードフレーム９の半導体装置１個分のみが示されてい
るが、実際には複数の半導体装置を得るために図２と同
一のものが複数個長手に連結されている。To manufacture the semiconductor device of FIG. 1, first, the lead frame 9 shown in FIG. 2 is prepared. The lead frame 9 includes a plurality of chip supports 2, a large number of external leads 3 juxtaposed in the arrangement direction of the supports 2, and a plate-shaped connecting conductor 5.
It has strips 10, 11, 12 and a connecting portion 13, and is formed by punching out a copper plate having a thickness of about 0.5 mm. Although only one semiconductor device of the lead frame 9 is shown in FIG. 2, a plurality of the same devices as those in FIG. 2 are actually connected in a longitudinal direction in order to obtain a plurality of semiconductor devices.
【０００８】リードフレーム９のチップ支持体２の一方
の主面（表面）には半導体チップ１を半田（図示せず）
で固着し、この半導体チップ１と外部リード３との間及
び半導体チップ１の相互間及び半導体チップ１と接続導
体５との間をワイヤから成る内部接続導体４によって接
続し、チップ・リードフレーム組立体を形成する。The semiconductor chip 1 is soldered (not shown) on one main surface (front surface) of the chip support 2 of the lead frame 9.
The semiconductor chip 1 and the external leads 3 and the semiconductor chips 1 and the semiconductor chip 1 and the connection conductors 5 are connected to each other by the internal connection conductors 4 made of wires, Form a solid.
【０００９】次に、ヒートシンク（放熱板）６を用意す
る。このヒートシンク６は、厚さ約２ｍｍのアルミニウ
ム板６ａの一方の主面にアルミナ層（アルミニウム酸化
物層）６ｂを形成したものである。なお、アルミナ層６
ｂはアルミニウム板６ａを硫酸浴中に浸漬させて硫酸電
解することによって形成したものであり、約２０μｍの
厚さを有する。このヒートシンク６には図３に示すよう
に２つの貫通孔６ｃが設けられ、また図１に示すように
下面の周縁に段部６ｄが設けられ、周縁の厚みが中央部
よりも薄くなっている。Next, a heat sink (heat sink) 6 is prepared. The heat sink 6 is formed by forming an alumina layer (aluminum oxide layer) 6b on one main surface of an aluminum plate 6a having a thickness of about 2 mm. The alumina layer 6
b is formed by immersing the aluminum plate 6a in a sulfuric acid bath and electrolyzing with sulfuric acid, and has a thickness of about 20 μm. As shown in FIG. 3, the heat sink 6 is provided with two through holes 6c, and as shown in FIG. 1, a step portion 6d is provided on the peripheral edge of the lower surface so that the peripheral edge is thinner than the central portion. .
【００１０】次に、このヒークシンク６のアルミナ層６
ｂ上面全体に高熱伝導性エポキシレジンを約５０μｍの
厚さに印刷する。この高熱伝導性エポキシレジンは液状
エポキシレジンにシリカ等の添加物を比較的多く含有さ
せて熱伝導性を向上させた樹脂材である。次に、図４に
示すように高熱伝導性エポキシレジン７ａの粘着性を利
用してリードフレーム９の支持体２、外部リード３の端
部、内部接続導体５をヒートシンク６のアルミナ層６ｂ
の上に仮付けする。これによって、高熱伝導性エポキシ
レジン７ａの厚さは若干薄くなる。また、このエポキシ
レジン７ａの上面の凹凸はリードフレーム９に押圧され
て平らとなり、リードフレーム９とヒートシンク６との
間隔は均一になる。Next, the alumina layer 6 of the heat sink 6
b Print a high thermal conductivity epoxy resin on the entire top surface to a thickness of about 50 μm. This high thermal conductivity epoxy resin is a resin material in which a liquid epoxy resin contains a relatively large amount of an additive such as silica to improve the thermal conductivity. Next, as shown in FIG. 4, the support 2 of the lead frame 9, the ends of the external leads 3, the internal connection conductors 5 are connected to the alumina layer 6b of the heat sink 6 by utilizing the adhesiveness of the high thermal conductive epoxy resin 7a.
Temporarily attach it on top of. As a result, the thickness of the high thermal conductivity epoxy resin 7a is slightly reduced. Further, the unevenness on the upper surface of the epoxy resin 7a is pressed by the lead frame 9 and becomes flat, so that the interval between the lead frame 9 and the heat sink 6 becomes uniform.
【００１１】続いて、このリードフレーム９とヒートシ
ンク６から成る組立体を樹脂封止体８を形成するための
トランスファモールド金型１６に配置する。金型１６は
上型１６ａと下型１６ｂとから成り、これ等を型締めす
ることによって樹脂封止体８に対応する成形空所１７が
形成される。Subsequently, the assembly consisting of the lead frame 9 and the heat sink 6 is placed in the transfer mold 16 for forming the resin sealing body 8. The mold 16 is composed of an upper mold 16a and a lower mold 16b, and a mold cavity 17 corresponding to the resin sealing body 8 is formed by clamping these molds.
【００１２】トランスファモールド金型１６は１７０℃
程度に加熱されている。したがって、図４のように金型
１６に組立体を配置すると、組立体の高熱伝導性エポキ
シレジン７ａが加熱されて硬化し、硬質の絶縁膜７とな
り、これによりヒートシンク６に対してリードフレーム
９が固着される。なお、工程を簡略化するためにこの実
施例ではエポキシレジン７ａの硬化をトランファモール
ド工程で行っているが、この工程の前に独立の硬化工程
を設けることもできる。次に、図４のようにヒートシン
ク９の下面が成形空所１７の底面に密着するように組立
体を位置決めして、ゲート１８を通して成形空所１７内
にエポキシレジンを押圧注入する。注入されたレジンは
加熱されて数十秒のうちに硬化し、樹脂封止体８が形成
される。The transfer mold die 16 is 170 ° C.
It is heated to a degree. Therefore, when the assembly is placed in the mold 16 as shown in FIG. 4, the high thermal conductive epoxy resin 7a of the assembly is heated and hardened to form a hard insulating film 7, which leads to the heat sink 6 and the lead frame 9. Is fixed. In this embodiment, the epoxy resin 7a is cured by a transfer molding process in order to simplify the process, but an independent curing process may be provided before this process. Next, as shown in FIG. 4, the assembly is positioned so that the lower surface of the heat sink 9 is in close contact with the bottom surface of the molding cavity 17, and epoxy resin is pressed into the molding cavity 17 through the gate 18. The injected resin is heated and cured within a few tens of seconds to form the resin sealing body 8.
【００１３】上述のように、アルミナ層６ｂの上にエポ
キシレジン７ａを塗布すると、アルミナ層６ｂが有して
いる微細な孔にエポキシレジン７ａが充填される。従っ
て、アルミナ板６ａとチップ支持体２及び外部リード３
との間の絶縁耐圧が十分に大きくなる。また、アルミナ
層６ｂを絶縁膜として使用することができるので、エポ
キシレジン７ａに基づく絶縁膜７の耐圧負担を軽くする
ことが可能になり、絶縁膜７を薄く形成して放熱性を向
上させることができる。また、エポキシレジン７ａに基
づく絶縁膜７は接着材としての働きも有するので、これ
以外の接着材を特別に使用することが不要であり、チッ
プ支持体２とアルミニウム板６ａとの間の介在層が少な
くなり、放熱性が良くなる。また、ヒートシンク６に対
してチップ支持体２のみでなく、外部リード３の端部及
び内部接続導体５もエポキシレジン７ａで仮固着される
ので、リードフレーム９による複数個の半導体装置の製
造を安定的に進めることができる。As described above, when the epoxy resin 7a is applied on the alumina layer 6b, the epoxy resin 7a is filled in the fine pores of the alumina layer 6b. Therefore, the alumina plate 6a, the chip support 2 and the external leads 3 are
Withstand voltage between and becomes sufficiently large. Further, since the alumina layer 6b can be used as an insulating film, it is possible to reduce the withstand voltage load of the insulating film 7 based on the epoxy resin 7a, and to form the insulating film 7 thin to improve heat dissipation. You can Further, since the insulating film 7 based on the epoxy resin 7 also has a function as an adhesive, it is not necessary to use an adhesive other than this specially, and an intervening layer between the chip support 2 and the aluminum plate 6a. Less and better heat dissipation. Further, not only the chip support 2 but also the end portions of the external leads 3 and the internal connection conductors 5 are temporarily fixed to the heat sink 6 by the epoxy resin 7a, so that the manufacturing of a plurality of semiconductor devices by the lead frame 9 is stabilized. You can proceed.
【００１４】[0014]
【変形例】本発明は上述の実施例に限定されるものでな
く、変形可能なものである。例えば絶縁膜７をエポキシ
レジン以外の樹脂にすることができる。[Modification] The present invention is not limited to the above-mentioned embodiment, but can be modified. For example, the insulating film 7 can be made of a resin other than epoxy resin.
【図１】実施例の半導体装置を示す断面図である。FIG. 1 is a cross-sectional view showing a semiconductor device of an example.
【図２】図１の半導体装置を構成するための半導体チッ
プとリードフレームとの組立体を示す平面図である。FIG. 2 is a plan view showing an assembly of a semiconductor chip and a lead frame for forming the semiconductor device of FIG.
【図３】図１のヒートシンクの平面図である。FIG. 3 is a plan view of the heat sink of FIG.
【図４】図１の半導体装置を製造するために金型にヒー
トシンクと絶縁体とチップを有するリードフレームとを
装着した状態を示す断面図である。FIG. 4 is a cross-sectional view showing a state in which a heat sink, an insulator and a lead frame having a chip are mounted on a mold for manufacturing the semiconductor device of FIG.
１ 半導体チップ ２ チップ支持体 ６ ヒートシンク ６ａ アルミニウム板 ６ｂ アルミナ層 ７ 絶縁膜 1 Semiconductor Chip 2 Chip Support 6 Heat Sink 6a Aluminum Plate 6b Alumina Layer 7 Insulating Film
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 23/50 Ｙ 9272−4Ｍ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Internal reference number FI technical display location H01L 23/50 Y 9272-4M
Claims (2)
体チップが固着された導電性を有するチップ支持体と、
前記半導体チップを外部回路に接続するための外部リー
ドと、前記半導体チップの熱を放出するために前記チッ
プ支持体の他方の主面に対向配置された放熱体と、前記
チップ支持体と前記放熱体との間に配置された絶縁膜と
を備え、 前記放熱体がアルミニウム板とこのアルミニウム板の一
方の主面上に形成されたアルミナ層とから成り、 前記絶縁膜が前記アルミナ層と前記チップ支持体とを接
着する材料から成ることを特徴とする半導体装置。1. A semiconductor chip, and a conductive chip support having the semiconductor chip fixed to one main surface thereof,
An external lead for connecting the semiconductor chip to an external circuit, a heat radiator arranged opposite to the other main surface of the chip support for radiating heat of the semiconductor chip, the chip support and the heat radiation. An insulating film disposed between the aluminum plate and an alumina layer formed on one main surface of the aluminum plate, wherein the insulating film is the alumina layer and the chip. A semiconductor device comprising a material that adheres to a support.
チップ支持体と外部リードとを有するリードフレームを
用意すると共に、アルミニウム板とこのアルミニウム板
の一方の主面に形成されたアルミナ層とから成る放熱板
を用意し、 前記アルミナ層の主面のほぼ全部に粘着性を有する絶縁
性接着材を塗布し、 前記絶縁性接着材によって前記アルミナ層の上に前記チ
ップ支持体を接着し、 前記絶縁性接着材を硬化して前記アルミナ層に前記チッ
プ支持体を固着すると共に絶縁膜を得ることを特徴とす
る半導体装置の製造方法。2. A lead frame having a chip support having a semiconductor chip fixed to one main surface and external leads is prepared, and an aluminum plate and an alumina layer formed on one main surface of the aluminum plate. Prepare a heat dissipation plate consisting of, apply an insulating adhesive material having adhesiveness to almost all of the main surface of the alumina layer, and bond the chip support on the alumina layer by the insulating adhesive material, A method of manufacturing a semiconductor device, comprising: curing the insulating adhesive to fix the chip support to the alumina layer and obtaining an insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32240492A JPH06151657A (en) | 1992-11-06 | 1992-11-06 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32240492A JPH06151657A (en) | 1992-11-06 | 1992-11-06 | Semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06151657A true JPH06151657A (en) | 1994-05-31 |
Family
ID=18143288
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32240492A Pending JPH06151657A (en) | 1992-11-06 | 1992-11-06 | Semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06151657A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5986336A (en) * | 1996-03-22 | 1999-11-16 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device including a heat radiation plate |
| US6255742B1 (en) | 1997-10-08 | 2001-07-03 | Nec Corporation | Semiconductor package incorporating heat dispersion plate inside resin molding |
| WO2006048836A1 (en) * | 2004-11-03 | 2006-05-11 | Koninklijke Philips Electronics, N.V. | Inner bridges for chip-to-chip interconnections in a multi-chip ic package |
| JP2007081442A (en) * | 1998-10-05 | 2007-03-29 | Fuji Electric Device Technology Co Ltd | Package of semiconductor element and method of manufacturing the same |
| WO2008021220A2 (en) | 2006-08-11 | 2008-02-21 | Vishay General Semiconductor Llc | Semiconductor device and method for manufacturing a semiconductor device having improved heat dissipation capabilities |
| JP2008082596A (en) * | 2006-09-27 | 2008-04-10 | Daikin Ind Ltd | Power module and air conditioner using the same |
| US7645685B2 (en) | 2006-03-17 | 2010-01-12 | Tdk Corporation | Method for producing a thin IC chip using negative pressure |
| JP2013021283A (en) * | 2011-07-08 | 2013-01-31 | Samsung Electro-Mechanics Co Ltd | Power module package and manufacturing method of the same |
| JP2014090104A (en) * | 2012-10-31 | 2014-05-15 | Denso Corp | Semiconductor device, and method of manufacturing the same |
| EP2674973A4 (en) * | 2011-02-09 | 2014-08-13 | Mitsubishi Electric Corp | Power semiconductor module |
| CN113394177A (en) * | 2021-08-18 | 2021-09-14 | 瑞能半导体科技股份有限公司 | Semiconductor package structure and manufacturing method thereof |
-
1992
- 1992-11-06 JP JP32240492A patent/JPH06151657A/en active Pending
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5986336A (en) * | 1996-03-22 | 1999-11-16 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device including a heat radiation plate |
| US6255742B1 (en) | 1997-10-08 | 2001-07-03 | Nec Corporation | Semiconductor package incorporating heat dispersion plate inside resin molding |
| JP2007081442A (en) * | 1998-10-05 | 2007-03-29 | Fuji Electric Device Technology Co Ltd | Package of semiconductor element and method of manufacturing the same |
| WO2006048836A1 (en) * | 2004-11-03 | 2006-05-11 | Koninklijke Philips Electronics, N.V. | Inner bridges for chip-to-chip interconnections in a multi-chip ic package |
| US7645685B2 (en) | 2006-03-17 | 2010-01-12 | Tdk Corporation | Method for producing a thin IC chip using negative pressure |
| WO2008021220A2 (en) | 2006-08-11 | 2008-02-21 | Vishay General Semiconductor Llc | Semiconductor device and method for manufacturing a semiconductor device having improved heat dissipation capabilities |
| EP2057665A4 (en) * | 2006-08-11 | 2016-01-06 | Vishay Gen Semiconductor Llc | Semiconductor device and method for manufacturing a semiconductor device having improved heat dissipation capabilities |
| JP2008082596A (en) * | 2006-09-27 | 2008-04-10 | Daikin Ind Ltd | Power module and air conditioner using the same |
| EP2674973A4 (en) * | 2011-02-09 | 2014-08-13 | Mitsubishi Electric Corp | Power semiconductor module |
| US9129949B2 (en) | 2011-02-09 | 2015-09-08 | Mitsubishi Electric Corporation | Power semiconductor module |
| JP2013021283A (en) * | 2011-07-08 | 2013-01-31 | Samsung Electro-Mechanics Co Ltd | Power module package and manufacturing method of the same |
| US8792239B2 (en) | 2011-07-08 | 2014-07-29 | Samsung Electro-Mechanics Co., Ltd. | Power module package and method for manufacturing the same |
| JP2014090104A (en) * | 2012-10-31 | 2014-05-15 | Denso Corp | Semiconductor device, and method of manufacturing the same |
| CN113394177A (en) * | 2021-08-18 | 2021-09-14 | 瑞能半导体科技股份有限公司 | Semiconductor package structure and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7642640B2 (en) | Semiconductor device and manufacturing process thereof | |
| US7495323B2 (en) | Semiconductor package structure having multiple heat dissipation paths and method of manufacture | |
| KR100478883B1 (en) | Semiconductor device | |
| KR100370231B1 (en) | Power module package having a insulator type heat sink attached a backside of leadframe & manufacturing method thereof | |
| US6867484B2 (en) | Semiconductor device | |
| KR20040080394A (en) | Semiconductor device and method of manufacturing same | |
| JPS63205935A (en) | Resin-sealed type semiconductor device equipped with heat sink | |
| JP2003258166A (en) | Semiconductor device | |
| US9466542B2 (en) | Semiconductor device | |
| JP4545022B2 (en) | Circuit device and manufacturing method thereof | |
| JPH06151657A (en) | Semiconductor device and its manufacture | |
| US20220115283A1 (en) | Semiconductor package, electronic device, and method for manufacturing semiconductor package | |
| JP4549171B2 (en) | Hybrid integrated circuit device | |
| JPH03108744A (en) | Resin-sealed semiconductor device | |
| US6281579B1 (en) | Insert-molded leadframe to optimize interface between powertrain and driver board | |
| JPH1022435A (en) | Semiconductor device and manufacture thereof | |
| US20230170287A1 (en) | Power semiconductor module, method for assembling a power semiconductor module and housing for a power semiconductor module | |
| KR102405276B1 (en) | Semiconductor package and method of fabricating the same | |
| EP3428962B1 (en) | Semiconductor device and method for manufacturing semiconductor device | |
| JP3894749B2 (en) | Semiconductor device | |
| JP2626619B2 (en) | Resin-sealed semiconductor device and method of manufacturing the same | |
| JP2002076259A (en) | Power module | |
| US20230282566A1 (en) | Semiconductor package having negative patterned substrate and method of manufacturing the same | |
| JPH0669384A (en) | Insulator sealing type semiconductor device | |
| JPS60110145A (en) | Resin-sealed type semiconductor device |