JP2746010B2 - Multiple inverter device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplex inverter device used for controlling a synchronous motor and capable of outputting from a DC to an AC power having a predetermined frequency.

[0002]

2. Description of the Related Art When a synchronous motor is driven by an inverter device for converting DC power into AC power, when the capacity is large or when the voltage pulsation becomes a problem, the inverters are multiplexed and the inverters are multiplexed. The AC output waveform is approximated to a sine wave. The multiplexing of the inverters is usually achieved by using a plurality of inverters and an insulating transformer for multiplexing, and adding the output voltage waveforms of the respective inverters with appropriate magnitudes and phase differences.

However, when a synchronous motor is driven, the above-mentioned insulating transformer may be saturated during a start-up operation or a low-frequency operation. No inverter is provided, and another inverter is provided with an isolation transformer on the output side. Then, the secondary winding of each of these insulating transformers and the AC output terminal of the inverter without the transformer are connected in series to form an inverter device, which is connected to the armature winding for one phase of the synchronous motor. From the inverter device to the synchronous motor
Power is supplied to the armature windings for the phases.

FIG. 4 is a diagram showing a configuration of a conventional multiplex inverter device of this kind disclosed in, for example, Japanese Patent Application Laid-Open No. 3-70472. In the figure, 1 is an AC power supply, 2 is a rectifier configured by a diode and converting AC to DC, 3
Is a DC reactor, and capacitors 4 and 5 divide the DC voltage between the DC side terminals P and N of the rectifier 2 into two equal parts and cooperate with the DC reactor 3 to smooth the rectified DC voltage.

[0005] Reference numeral 6 denotes a first inverter.
It is configured as in (1). In the figure, T ₁ ,
T ₂ are GTO is self-extinguishing thyristor as a switching element, D _1, D ₂ is a diode. Rectifier 2
Are connected to the input terminals 601 and 602, respectively, and the potential of the terminal P is output to the output terminal 603 if T ₁ is ON and T ₂ is OFF, and T ₁ is OFF and T ₂
Is ON, the potential of the terminal N is output.

Returning to FIG. 4, reference numerals 7 and 8 denote second inverters, which are configured, for example, as shown in FIG. In the figure, T ₃ through T ₆ are GTO, in D ₃ to D ₆ are diodes,
Since these configurations and operations are generally well known,
The description is omitted. Reference numerals 9 and 10 denote insulating transformers for multiplexing, 11 denotes a synchronous motor having armature windings 11a, 11b and 11c for each phase and a rotor 11d. One armature winding 11a for one phase is used for an inverter device. It is connected to supply terminals U ₁ and U ₂ .

Reference numeral 12 denotes a position detector for detecting the spatial position and the number of rotations of the rotor 11d, 13 a shunt connected in series with the armature winding 11a, and 14 a current detector for detecting the armature current. Convert to control signal. Reference numeral 15 denotes a current reference wave generator which generates a sinusoidal current reference waveform corresponding to the position detection signal from the position detector 12. A subtractor 16 subtracts the control signal from the current detector 14 from the sine wave current reference waveform from the current reference wave generator 15 and outputs a deviation signal.
Reference numeral 17 denotes a current control element that amplifies the deviation signal from the subtractor 16 to create a bias signal that serves as a voltage command for the inverter device. Reference numeral 18 denotes a carrier signal generator that generates a so-called carrier signal having a frequency of about several hundred hertz. Reference numeral 19 denotes a gate signal generator. Gating signals to GTO of 6, 7, 8 are created.

Next, the operation will be described with reference to the waveform diagram of FIG. In this example, since the inverter configuration shown in FIG. 5 is adopted, the second inverters 7 and 8 can generate twice the output voltage as compared with the first inverter 6. Therefore, the carrier signals 103 and 105 of the second inverters 7 and 8 are equal to the carrier signals 1 and 2 of the first inverter 6.
01, and the second inverter is 2
The first inverter 6
The carrier signal 101 of the second inverter 7 and the carrier signal 103 of the second inverter 7 have a phase difference of 45 °, and the carrier signal 103 of the second inverter 7 and the carrier signal 105 of the second inverter 8 have a phase difference of 90 °. It has a phase difference.

FIG. 6 shows a case where the bias signal, which is a voltage command from the current control element 17, is almost zero, and the output voltage 107 of the first inverter 6 alone has a carrier signal frequency ripple, but the second inverter 6 has a ripple. By adding the respective output voltages 108 and 109 of FIG.
As shown in (g), the ripple is reduced. Note that the bias signal 1 of the second inverters 7 and 8 is
04, 106, as shown in FIGS. 6B and 6C,
Signal 101 and bias signal 1 of inverter 6
02 is a rectangular wave whose pulse width is determined from the comparison with the second inverter, the magnitude of which is obtained by subtracting the bias signal value 102 at that time from the bias signal value corresponding to the maximum output voltage of the first inverter 6. Number (here 2)
Divided by

[0010]

Since the conventional multiplex inverter device is constructed as described above, as shown in FIG. 7, the bias signal as the voltage command from the current control element 17 is not zero but rather large. When the value becomes larger, there is a problem that the effect of suppressing the ripple by the multiplexing is weakened. That is, as described above, when the synchronous motor starts from its stationary state, a DC input is required, but this power is exclusively output by the first inverter 6. FIG.
Reference numeral 202 in (a) denotes a bias signal at that time.

Accordingly, as shown in FIGS. 7B and 7C, the bias signals 204 and 206 of the second inverters 7 and 8 are narrower pulses than those in FIG. However, as a result, the pulse widths of the output voltages 208 and 209 of the second inverters 7 and 8 are shortened, and the effect of suppressing the ripple by adding the output voltages of the second inverters 7 and 8 is greatly reduced. Will decrease.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and realizes a multiplex inverter device which can sufficiently expect an effect of suppressing a voltage ripple even when a bias signal as a voltage command becomes large. It is something you want to do.

[0013]

A multiplex inverter apparatus according to the present invention uses a bias signal V ₁ ^* to a first inverter, which is a voltage command, and a carrier signal C ₁ to the first inverter, by the following equation. And a bias signal generator for generating a bias signal V ₂ ^* to a second inverter based on the bias signal V ₂ ^* and a carrier signal frequency component in the composite output voltage so as to be always small irrespective of the bias signal V ₁ ^*. Bias signal V from signal generator
₂ ^* is provided with a bias signal correction circuit that corrects the insulation value of the bias signal V ₁ ^* so as to increase as the insulation value increases. _{(1) C 1> | V} 1 * | V 2 * = time ^{_{(V 1m * - | V 1}} * |) / N (2) | V 1 * |> C 1> - | V 1 * | when ^{_{V 2 * = 0 (3)}} - | V 1 * |> C 1 when ^{_{V 2 * = (| V 1}} * | -V 1m *) / N where, V _{1 m} ^* is a first inverter can generate The bias signal value corresponding to the maximum voltage, N, is the number of the second inverters.

[0014]

According to the present invention, as the bias signal V ₁ ^* of the first inverter increases, the bias signal V ₂ ^* of the second inverter also increases from the conventional value, so that the output voltage of the second inverter increases. Is reduced, and the effect of suppressing ripple is ensured.

[0015]

[Embodiment 1] Hereinafter, a multiplex inverter device according to a first embodiment of the present invention will be described with reference to the drawings. However, since the overall configuration of the device is the same as that shown in FIG. 4, the re-recording is omitted, and in particular, the internal configuration of the gate signal generator, which is a main part of the present invention, is shown in FIG. The details will be described below based on this.

In FIG. 1, reference numeral 19 denotes a gate signal generator, which receives a bias signal from a current control element 17 and a carrier signal from a carrier signal generator 18, respectively.
The gate signal to the inverter 6 and the second inverters 7 and 8 is created. Reference numerals 19a, 19b and 19c denote phase shifters for adjusting the carrier signal from the carrier signal generator 18 to an appropriate size and phase. The carrier signals from the phase shifters 19a and 19b are twice as large as the carrier signal from the same 19c. Make it big. The carrier signal from the phase shifter 19a is 45 times smaller than the carrier signal from the phase shifter 19c.
The carrier signal from 19b has a 90 ° phase delay with respect to the carrier signal from 19a.

Reference numerals 19d, 19e and 19f denote each phase shifter 19
Comparator for comparing the carrier signals from a, 19b, and 19c with a bias signal from a current control element 17 and a bias signal correction circuit 19h to be described later to generate gate signals to the second inverter and the first inverter. It is. Reference numeral 19g denotes a bias signal generator for generating a bias signal to the second inverter from a bias signal as a voltage command from the current control element 17 and a carrier signal of the first inverter from the phase shifter 19c. This is a bias signal correction circuit for correcting the output value of the bias signal generator 19g.

First, the bias signal generator 19g performs an operation according to the following equation. _{(1) C 1> | V} 1 * | V 2 * = when ^{_{(V 1m * - | V 1}} * |) / 2 (2) | V 1 * |> C 1> - | V 1 * | when the ^{_{V 2 * = 0 (3)}} - | V 1 * |> V 2 * = when ^{_{C 1 (| V 1 * |}} -V 1m *) / 2 where, C ₁ is the carrier signal to the first inverter 6 (The output of the phase shifter 19c), V ₁ ^* is a bias signal (output of the current control element 17) to the first inverter 6, and V _1m ^* is the first
The bias signal value V ₂ ^* corresponding to the maximum voltage that can be generated by the inverter 6 is a bias signal to the second inverters 7 and 8, which is an output signal of the bias signal generator 19g. Note that the divisor 2 on the right side of the above equations (1) and (3) corresponds to the number of second inverters = 2.

The output from the bias signal generator 19g as described above is used as a bias signal to the second inverters 7 and 8 as described with reference to FIGS. 6 and 7 in the related art. In order to solve the problem, a bias signal correction circuit 19h is provided to correct the bias signal, and the procedure will be described below. That is, the bias signal correction circuit 19h performs the calculation of the following equation (4). ^{_{(4) V 2 ** = V}} 2 * / f (V 1 *) where, V ₂ ^** This signal bias signal corrected with a bias signal correction circuit 19h second inverter 7,
8 are sent to the comparators 19d and 19e. V ₂ ^* is a bias signal output from the bias signal generator 19g. F (V ₁ ^* ) is a correction function, an example of which is shown in FIG.

That is, the correction function f (V ₁ ^* ) is a function of the bias signal V ₁ ^* of the first inverter 6 and takes 1 when V ₁ ^* = 0 (therefore, V ₂ ^** = V _2). ^* ), Monotonically decreases as | V ₁ ^* | increases. Therefore, the corrected bias signal V ₂ ^** tends to increase monotonically (V ₂ ^** > V ₂ ^* ).

FIG. 3 shows input / output waveforms when driven based on the bias signal V ₂ ^** output from the bias signal correction circuit 19h. As shown in FIG. 3A, the bias signal value input to the device as a voltage command is
Is the same as Therefore, the output waveform of the first inverter 6 shown in FIG. 3D is the same as that of the conventional case. However, in the embodiment of the present invention, the correction processing by the correction function f (V ₁ ^* ) is performed, and in this example, V ₁ ^* ≒ V
Since it is set to _1m ^* / 2, according to FIG. 2, V ₂ ^** ≒ 2
× V ₂ ^* , and the bias signals 304 and 306 (FIGS. 3B and 3C) to the second inverters 7 and 8 are approximately twice as large as the bias signals 204 and 206 in the conventional case of FIG. Has become.

As a result, the pulse widths of the output voltages 308 and 309 of the second inverters 7 and 8 are also reduced by about 2
As a result, the ripple of the combined voltage 310 is greatly reduced. In other words, the effect of suppressing the ripple due to the multiplexing is surely exhibited without being weakened by the increase in the bias signal.

Embodiment 2 FIG. In the above embodiment, the case where the number of the second inverters is two has been described. However, the present invention can be similarly applied to the case where the number of the second inverters is one or three or more, and the same effect is obtained. Further, the correction function f (V ₁ ^* ) is not limited to the one shown in FIG. 2 and may have an optimum characteristic according to the condition of each inverter device. Furthermore, in the above-described embodiment, the function of generating the bias signal to the second inverter is shared between the bias signal generator 19g and the bias signal correction circuit 19h. It is not necessary, and the data may be directly output by a single arithmetic processing. The present invention can be applied not only to the DC output at the time of starting the synchronous motor but also to the operation region of extremely low frequency thereafter. Also, the load is not necessarily limited to the synchronous motor.

[0024]

As described above, according to the present invention, the bias signal correction circuit is provided to apply a predetermined correction process to the conventional bias signal to the second inverter. Even if the bias signal of
The effect of suppressing ripples due to multiplexing is reliably exhibited.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a gate signal generator 19 of a multiplex inverter device according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating characteristics of a correction function adopted in a bias signal correction circuit 19h of FIG. 1;

FIG. 3 is a characteristic diagram illustrating an operation example of the present invention.

FIG. 4 is a diagram showing a configuration of a conventional multiplex inverter device.

FIG. 5 is a diagram showing an element configuration of a first inverter 6 and second inverters 7 and 8 of FIG.

FIG. 6 is a characteristic diagram illustrating an operation example in a conventional case.

FIG. 7 is a characteristic diagram illustrating an operation example under different conditions from FIG.

[Explanation of symbols]

Reference Signs List 6 First inverter 7, 8 Second inverter 9, 10 Isolation transformer 11 Synchronous motor 17 Current control element 18 Carrier signal generator 19 Gate signal generator 19a-19c Phase shifter 19d-19f Comparator 19g Bias signal generation 19h Bias signal correction circuit f (V ₁ ^* ) Correction function V ₁ ^* Bias signal of first inverter C ₁ Carrier signal of first inverter V ₂ ^* , V ₂ ^** Bias signal of second inverter

Claims (1)

(57) [Claims] A first inverter connected to an output side of the first inverter via an insulation transformer connected to the output side, the first inverter having no output connected to the insulation transformer, and a first inverter connected to the output side of the first inverter via an insulation transformer connected to the output side; One or more second inverters for supplying a combined output voltage with one inverter, and a pulse width determined from a comparison between an input carrier signal and a bias signal of a voltage command, and a gate to a switching element of each inverter. A multiplex inverter device having a gate signal generator for generating a signal, wherein when the bias signal of the voltage command is a DC value (V ^* ), the bias signal V ^* is converted to the first signal.
With a bias signal V ₁ ^* to the inverter from the bias signal V ₁ ^* and the carrier signal C ₁ Tokyo to said first inverter, based on the following equation, the bias signal V ₂ to said second inverter ^* , A bias signal generator, and the bias signal V ₂ ^* from the bias signal generator so that the carrier signal frequency component in the composite output voltage is always small regardless of the bias signal V ₁ ^* . A multiplex inverter device including a bias signal correction circuit that corrects the insulation value of the bias signal V ₁ ^* so as to increase as the insulation value increases. _{(1) C 1> | V} 1 * | V 2 * = time _{^{(V 1m * - | V 1}} * |) / N (2) | V 1 * |> C 1> - | V 1 * | when ^{_{V 2 * = 0 (3)}} - | V 1 * |> C 1 when _{^{V 2 * = (| V 1}} * | -V 1m *) / N where, V _{1 m} ^* is a first inverter can generate The bias signal value corresponding to the maximum voltage, N, is the number of the second inverters.