JP2022050739A - Bidirectional isolation dc/dc converter and control method thereof - Google Patents

Abstract

To suppress the DC components of an excitation current and an inductor current during transients in a DAB type bidirectional isolation DC/DC converter.SOLUTION: A phase shift amount calculation unit 1 calculates phase shift amounts d_u, d_v, d_x, and d_y on the basis of a first pulse width command value W1*, a second pulse width command value W2*, and a phase difference command value θ*. A DC deviation suppression unit 3 changes on-times Ton_u, Ton_v, Ton_x, and Ton_y of respective inverter legs of first and second inverters on the basis of the change amounts ΔW1 and ΔW2 of the first and second pulse width command values W1* and W2*, and a gate signal generation unit 2 generates a gate signal on the basis of the phase shift amounts d_u, d_v, d_x, and d_y, the carrier, and the on-times Ton_u, Ton_v, Ton_x, and Ton_y.SELECTED DRAWING: Figure 4

Description

The present invention is for suppressing the generation of DC components of exciting current and inductor current during transient in a DC power supply device (bidirectional isolated DC-DC converter) that transmits power in both directions while insulating the input and output. Regarding technology.

The DAB (Dual Active Bridge) method, which is one of the bidirectional isolated DC / DC converters, is composed of two full bridge inverters, a transformer (excited inductor) and an inductor (or only the leakage inductance of the transformer). Each inverter output voltage is a square wave, and the transmission power is controlled by the phase difference.

Japanese Patent Publication No. 2015-056053

Tatsuya Yamagishi, Hirofumi Akagi, Shinichi Kinouchi, Yuji Miyazaki, Masato Koyama, "750V, 100kW, 20kHz bidirectional isolated DC / DC converter using SiC- MOSFET / SBD module", IEEJ Journal D, Vol. 134, No. 5, pp. 544-553 (2014) Kazuto Takagi, Hideaki Fujita, "Improvement of Transient Characteristics of Insulated DC-DC Converter Using Dual Active Bridge", IEEJ Journal D, Vol. 136, No. No. 9, pp. 622-628 (2016)

Non-Patent Document 1 discloses that a soft switching technique is applied in a control in which each inverter output voltage is a square wave to reduce a switching loss. However, if there is a difference in the DC voltage between the primary side and the secondary side, there is a problem that the soft switching range is limited and the effective inductor current value is increased, resulting in a decrease in efficiency.

As a solution to this problem, there is a pulse width control method for controlling the pulse width by providing a zero voltage period for each inverter output voltage shown in Patent Document 1. However, the inverter output voltage does not become a complete alternating current when the pulse width is changed, the phase difference is changed, and the initial drive is performed, and the DC component is superimposed on the current flowing through the transformer or the inductor.

As a result, the magnetic flux density increases, and when the saturation magnetic flux density is reached, the transformer undergoes magnetic saturation, inrush current flows, and the equipment may be damaged. In order to prevent magnetic saturation due to the DC component, the size of the magnetic component must be increased.

Non-Patent Document 2 discloses a method of suppressing transient DC superimposition that occurs when a steep phase difference command value changes. This is a method of dividing the update timing of the phase difference command value of each arm. However, suppression of DC superimposition when pulse width control is applied has not been studied.

From the above, it is a problem to suppress the DC components of the exciting current and the inductor current at the time of transition in the DAB type bidirectional isolated DC / DC converter.

The present invention has been devised in view of the above-mentioned conventional problem, and one aspect thereof is connected to the primary side DC voltage, the secondary side DC voltage, and the primary side DC voltage, and the primary side DC voltage is connected to the primary side DC voltage. A first inverter that converts a side DC voltage into an AC voltage, a second inverter that is connected to the secondary side DC voltage and converts the secondary side DC voltage into an AC voltage, and an AC of the first and second inverters. The transformer that couples the outputs, the inductor connected in series between the first and second inverters and the transformer, the leakage voltage of the transformer, or both, and the gate signal of the first and second inverters. A DAB type bidirectional isolated DC / DC converter including a control unit for generating, wherein the control unit has a first pulse width command value for determining a pulse width of the output voltage of the first inverter. Phase based on the second pulse width command value that determines the pulse width of the output voltage of the second inverter and the phase difference command value that determines the phase difference of the output voltage of the first and second pulse width command values. A phase shift amount calculation unit that calculates the shift amount, and a DC deviation suppression unit that changes the on-time of each inverter leg of the first and second inverters based on the change amount of the first and second pulse width command values. It is characterized by including a gate signal generation unit that generates the gate signal based on the phase shift amount, the carrier, and the on-time.

Further, as one aspect thereof, the first and second pulse width command values used in the phase shift amount calculation unit and the DC deviation suppression unit are characterized by being moving average processed values.

Further, as one aspect thereof, the control unit sets the phase difference command value to zero and the first and second pulse width command values to π when the first and second inverters are stopped. 2 Assuming that the inverter is driven, the inverter output voltage is set to be a square wave, the drive start signal is output, and the first and second inverters are assumed to be driven. Initial value processing in which the first and second inverters are driven from the time point of the midpoint of the positive period or the midpoint of the negative period, and the phase difference command value and the first and second pulse width command values are set as normal values. It is characterized by having a part.

As another aspect, when the first and second inverters are stopped, the control unit sets the phase difference command value to zero and the first and second pulse width command values to the primary side DC voltage. Depending on the magnitude relationship of the secondary side DC voltage, if it is assumed that one of them is π and the inverter is driven, the inverter output voltage is set to be a square wave, and the other is set to the output voltage of the first and second inverters. The midpoint of the positive period of the square wave when it is assumed that the inverter set to match the fundamental wave amplitudes of the above, the drive start signal is output, and the pulse width command value is set to π is driven. Alternatively, the first and second inverters are driven from the time of the midpoint of the negative period, and an initial value processing unit having the phase difference command value and the first and second pulse width command values as normal values is provided. It is characterized by.

Further, as one aspect thereof, the initial value processing unit sets the first and second pulse width command values to the following equations (8) and (9) when the first and second inverters are stopped. It is characterized by that.

Vdc1: 1st DC voltage Vdc2: 2nd DC voltage N: Transformer turns ratio W1 ^* : 1st pulse width command value W2 ^* : 2nd pulse width command value.

Further, as one aspect thereof, the gate signal generation unit compares the flip-flop that unifies the update timing of the phase shift amount and updates at the timing of the peak of the carrier, and the output of the flip-flop and the carrier. The comparator, the monoflop that outputs High during the on-time from the time when the output of the flip-flop becomes smaller than the carrier, the NOT element that inverts the output of the monoflop, and the monoflop. The logical product of the dead time generation unit that adds the dead time to the output and the output of the NOT element, the output of the dead time generation unit, and the gate enable signal is obtained, and the gate signal of the switching device of the first and second inverters is obtained. It is characterized by having an AND element that outputs.

According to the present invention, in the DAB type bidirectional isolated DC / DC converter, it is possible to suppress the DC components of the exciting current and the inductor current at the time of transition.

The figure which shows an example of the main circuit composition of the bidirectional insulation type DC / DC converter of the DAB system. The figure which shows the operation waveform of a pulse width control method. The block diagram which shows the outline of the control part in the prior art. The block diagram which shows the outline of the control part in Embodiments 1-4. The block diagram which shows the phase shift amount calculation part. The block diagram which shows the gate signal generation part. The block diagram which shows the DC deviation suppression part. The figure which shows the operation waveform from the input of a comparator to the monoflop. The figure which shows the gate signal and the inverter output voltage waveform at the time of a pulse width command value change. The block diagram which shows the initial value processing part and the initial drive processing part in Embodiment 3. The block diagram which shows the initial value processing part in Embodiment 4. The figure which shows the simulation result of the conventional method and Embodiment 1 at the time of changing a pulse width. The figure which shows the operation waveform of Embodiment 1 and Embodiment 2. The figure which shows the operation waveform of Embodiment 3 at the time of initial drive. The figure which shows the simulation result of Embodiments 3 and 4 at the time of initial drive.

Hereinafter, the bidirectional isolated DC / DC converter in the present invention will be described in detail with reference to FIGS. 1 to 15.

First, an example of the main circuit configuration of the bidirectionally isolated DC / DC converter will be described with reference to FIG.

The first and second switching devices T11 and T12 are connected in series between the positive electrode and the negative electrode of the primary side DC voltage Vdc1. In addition, the third and fourth switching devices T13 and T14 are also connected in series between the positive electrode and the negative electrode of the primary side DC voltage Vdc1.

One end of the inductor L1 is connected to the connection points of the first and second switching devices T11 and T12. The primary winding of the transformer Tr is connected between the other end of the inductor L1 and the connection points of the third and fourth switching devices T13 and T14.

The fifth and sixth switching devices T21 and T22 are connected in series between the positive electrode and the negative electrode of the secondary side DC voltage Vdc2. In addition, the seventh and eighth switching devices T23 and T24 are also connected in series between the positive electrode and the negative electrode of the secondary side DC voltage Vdc2.

One end of the inductor L2 is connected to the connection points of the fifth and sixth switching devices T21 and T22. The secondary winding of the transformer Tr is connected between the other end of the inductor L2 and the connection points of the seventh and eighth switching devices T23 and T24.

The number of turns of the primary winding of the transformer Tr is n _pr , the number of turns of the secondary winding is n _se , and the turns ratio is N (= n _pr / n _se ). Further, the first to fourth switching devices T11 to T14 are referred to as a primary side inverter (first inverter), and the fifth to eighth switching devices T21 to T24 are referred to as a secondary side inverter (second inverter).

Further, the first and second switching devices T11 and T12 are connected in series, the third and fourth switching devices T13 and T14 are connected in series, the fifth and sixth switching devices T21 and T22 are connected in series, and the seventh and eighth switching are performed. The series connection of the devices T23 and T24 is defined as each inverter leg.

In FIG. 1, iL is an inductor current, and iLm is an exciting current of a transformer Tr. Further, the voltage between the connection points of the first and second switching devices T11 and T12 and the connection points of the third and fourth switching devices T13 and T14 is set as the inverter output voltage V1, and the fifth and sixth switching devices T21. , The voltage between the connection point of T22 and the connection point of the 7th and 8th switching devices T23 and T24 is defined as the inverter output voltage V2.

In FIG. 1, the inductors L1 and L2 are connected in series between the primary side and secondary side inverters and the transformer Tr, but instead of the inductors L1 and L2, the leakage inductance of the transformer Tr may be used. Further, both the inductors L1 and L2 and the leakage inductance of the transformer Tr may be used.

FIG. 2 shows the operation waveform of the pulse width control method. A period during which the output voltage becomes zero when the two switching devices (T11, T13, T21, T23) on the upper arm side or the two switching devices (T12, T14, T22, T24) on the lower arm side of each inverter are turned on at the same time. Is set.

Patent Document 1 discloses a method of expanding the soft switching range even when the difference between the DC voltage on the primary side and the secondary side is large by adjusting the pulse width only on the inverter side where the DC voltage is large. The control of the embodiment is a control in which the inverter output voltage is a square wave (that is, a control in which the first and second pulse width command values W1 ^* and W2 ^* are set to π and no zero voltage period is provided), and the primary side, It can be applied when controlling the pulse width of both or either of the secondary inverters.

FIG. 3 shows a schematic diagram of the control unit in the prior art. The phase shift amount calculation unit 1 inputs the phase difference command value θ ^* , the first pulse width command value W1 ^* , and the second pulse width command value W2 ^* . The first pulse width command value W1 ^* is a value that determines the pulse width of the output voltage of the primary side inverter, and the second pulse width command value W2 ^* is a value that determines the pulse width of the output voltage of the secondary side inverter. Yes, the phase difference command value θ ^* is a value that determines the phase difference of the output voltages of the first and second pulse width command values W1 ^* and W2 ^* .

The phase difference command value θ ^* , the first pulse width command value W1 ^* , and the second pulse width command value W2 ^* are values determined by power, current, voltage control, primary side, secondary side DC voltage ratio, etc. Yes, the calculation method is disclosed in Patent Document 1 and the like. Since the method for determining the phase difference command value θ ^* , the first pulse width command value W1 ^* , and the second pulse width command value W2 ^* is not directly related to the feature portion of the present invention, detailed description thereof will be omitted here. The phase difference command value θ ^* is −π / 2 ≦ θ ^* ≦ π / 2, the first pulse width command value W1 ^* is 0 ≦ W1 ^* ≦ π, and the second pulse width command value W2 ^* is 0 ≦ W2 ^*. The range is ≤π.

The phase shift amount calculation unit 1 calculates the phase shift amount of each inverter leg from the first pulse width command value W1 ^* , the second pulse width command value W2 ^* , and the phase difference command value θ ^* .

The gate signal generation unit 2 inputs a phase shift amount of each inverter leg, a carrier (sawtooth wave or triangular wave), and a drive start signal. Carriers are generated by up / down counting. The gate signal generation unit 2 compares the phase shift amount of each inverter leg with the carrier, and generates a gate signal having a desired phase and a duty ratio of 50%. The gate signal is output at the timing when the drive start signal becomes 1. In addition, a dead time is added to prevent a short circuit between the upper and lower arms.

FIG. 4 shows a schematic diagram of the control unit according to the first to fourth embodiments. As shown in FIG. 4, in the first embodiment, the DC deviation suppressing unit 3 is added to the control unit of the prior art. In the second embodiment, the moving average units 4 and 5 are added to the control unit of the first embodiment. In the third and fourth embodiments, the initial value processing unit 6 and the initial drive processing unit 7 are added to the control unit of the second embodiment. Hereinafter, each embodiment will be described.

[Embodiment 1]
As shown in FIG. 4, the control unit of the first embodiment includes a phase shift amount calculation unit 1, a gate signal generation unit 2, and a DC deviation suppression unit 3. In the first embodiment, in the DC deviation suppressing unit 3, the on-time Ton_u, Ton_v, Ton_x, Ton_y of each inverter leg is increased or decreased according to the amount of change of the first and second pulse width command values W1 ^* and W2 ^* . Therefore, the suppression of the DC components of the inductor current and the exciting current when the pulse width is changed is achieved.

FIG. 5 is a block diagram of the phase shift amount calculation unit 1. First, the phase shift amount calculation unit 1 will be described with reference to FIG.

The gain multiplication unit 8a multiplies the phase difference command value θ ^* by the gain 1 / 4π, and converts the change range of the phase difference command value θ ^* from −π / 2 to π / 2 to −0.125 to 0.125. do. The gain multiplication units 8b and 8c multiply the first and second pulse width command values W1 ^* and W2 ^* by the gain 1 / 4π, and set the change range of the first and second pulse width command values W1 ^* and W2 ^* to 0. Convert from ~ π to 0 to 0.25.

The adder 9a adds the output of the gain multiplication unit 8a and the output of the gain multiplication unit 8b. The adder 9b adds a value obtained by inverting the sign of the output of the gain multiplication unit 8b to the output of the gain multiplication unit 8a. The adder 9c adds the output of the gain multiplication unit 8c to the value obtained by inverting the sign of the output of the gain multiplication unit 8a. The addition unit 8d adds the value obtained by inverting the sign of the output of the gain multiplication unit 8c to the value obtained by inverting the sign of the output of the gain multiplication unit 8a.

The adder 10a adds a reference phase of 0.5 to the output of the adder 9a to achieve bidirectional operation. The adder 10b adds the reference phase 0.5 to the output of the adder 9b. The adder 10c adds the reference phase 0.5 to the output of the adder 9c. The adder 10d adds the reference phase 0.5 to the output of the adder 9d. The outputs of the adders 10a to 10d are the phase shift amounts d_u, d_v, d_x. It becomes d_y.

Next, the gate signal generation unit 2 will be described. FIG. 6 shows a block diagram of the gate signal generation unit 2.

The flip-flops 11a to 11d have phase shift amounts d_u, d_v, d_x. The update timing of d_y is unified, and it is updated at the timing of the peak of the carrier (sawtooth wave).

The comparators 12a to 12d have phase shift amounts d_u, d_v, d_x. The carriers are compared with d_y (outputs of flip-flops 11a to 11d), and when the phase shift amounts d_u, d_v, d_x, d_y are larger, high is output, and the phase shift amounts d_u, d_v, d_x, d_y are larger. When it is small, it outputs low. In the monoflops 13a to 13d, from the falling timing of the output of the comparators 12a to 12d (that is, the timing when the output of the flip-flops 11a to 11d becomes smaller than the carrier), the on-time of each inverter leg Ton_u, Ton_y, Ton_x, Outputs High for Ton_y minutes.

The NOT elements 14a to 14d invert the outputs of the monoflops 13a to 13d in order to generate a gate signal for the lower arm. The dead time generation units 15a to 15h add a dead time to the outputs of the monoflops 13a to 13d and the NOT elements 14a to 14d. The AND elements 16a to 16h obtain the logical product of the gate enable signal (or drive signal) and the output of the dead time generation units 15a to 15h, and output the gate signals T11 to T24.

Next, the DC deviation suppressing unit 3 will be described. FIG. 7 shows a block diagram of the DC deviation suppressing unit 3. The first embodiment is characterized in that the on-time of each inverter leg is changed according to the amount of change in the pulse width.

The gain multiplication units 17a and 17b multiply the first and second pulse width command values W1 ^* and W2 ^* by 1 / 4π, and change the range of the first and second pulse width command values W1 ^* and W2 ^* from 0 to 0. Convert from π to 0 to 0.25.

The buffers 18a and 18b output the previous values of the first and second pulse width command values W1 ^* and W2 ^* (outputs of the gain multiplication units 17a and 17b). The delay time is an integral multiple of the switching cycle. The peak values of the inductor current and the exciting current when the pulse width command value is changed can be suppressed in proportion to the period of the moving average units 4 and 5 described later.

The subtractors 19a and 19b subtract the outputs of the buffers 18a and 18b from the outputs of the gain multiplication units 17a and 17b, and are the differences between the previous values and the current values of the first and second pulse width command values W1 ^* and W2 ^* . The amount of change ΔW1 and ΔW2 are calculated.

The gain multiplication units 20a and 20b multiply the gains for converting the changes ΔW1 and ΔW2 of the first and second pulse width command values W1 ^* and W2 ^* into the on-time. This gain is 1/2 / fsw, which is half the switching period 1 / fsw. The on-time obtained from the changes ΔW1 and ΔW2 is defined as ΔTon_uv and ΔTon_xy.

The adder 21a adds the on-time command Ton ^* (= 1/2 / fsw) and the on-time ΔTon_uv obtained from the pulse width change amount ΔW1 to output the on-time Ton_u of the inverter leg. The adder 21b adds the value obtained by inverting the sign of the on-time ΔTon_uv obtained from the on-time command Ton ^* and the change amount ΔW1 of the pulse width, and outputs the on-time Ton_v of the inverter leg. The adder 21c adds the on-time command Ton ^* and the on-time ΔTon_xy obtained from the amount of change in the pulse width ΔW2, and outputs the on-time Ton_x of the inverter leg. The adder 21d adds the value obtained by inverting the sign of the on-time ΔTon_xy obtained from the on-time command Ton ^* and the amount of change in the pulse width ΔW2, and outputs the on-time Ton_y of the inverter leg.

In the first embodiment, a gate signal having an on time and a phase specified from each control output, the detected values of the primary side and secondary side voltages, the phase difference command value calculated from the turns ratio, and each pulse width command value is generated. The dual active bridge type bidirectional isolated DC / DC converter is driven so as to always achieve the desired pulse width and phase difference.

First, the phase shift amount calculation unit 1 shown in FIG. 5 will be described. The phase shift amount calculation unit 1 has a phase shift command value θ ^* and a phase shift amount d_u, d_v, d_x of each inverter leg of the primary side and secondary side inverters from the first and second pulse width command values W1 ^* and W2 ^* . , D_y are calculated using the following equations (1) to (4).

FIG. 5 shows the equations (1) to (4) in a block diagram.

Next, the gate signal generation unit 2 of FIG. 6 will be described. First, the update timings of the phase shift amounts d_u, d_v, d_x, and d_y are synchronized with the peaks of the carriers. This is to keep the number of switchings in one switching cycle constant regardless of the phase difference or the amount of change in the pulse width.

FIG. 8 shows the operation waveform from the input of the comparator 12a to the output of the monoflop 13a. FIG. 8 describes the operation waveform of the u phase, but the same applies to the other phases. First, the phase shift amount d_u and the carrier are compared by the comparator 12a, and the comparator 12a outputs High only during the period when the phase shift amount d_u is larger than the carrier. Further, the monoflop 13a outputs the on-time Ton_u minutes High specified from the falling timing of the output of the comparator 12a.

Finally, the NOT element 14a and the dead time generation units 15a and 15b output the gate signals T11 and T12 of the upper and lower arms.

However, when only the method of FIG. 3 is used, when the pulse width is changed as shown in FIG. 9, the off time of the inverter leg whose phase changes in the advancing direction is shortened according to the amount of the change, and the phase is changed. The off time of the inverter leg that changes in the lagging direction becomes longer (Toff_1 in FIG. 9).

Therefore, the time product of the voltage applied to the transformer Tr and the inductors L1 and L2 increases. Since the on time and the off time match in the next switching cycle, a DC component is generated in the exciting current iLm and the inductor current iL.

In the first embodiment, the on-time of each inverter leg is added or subtracted by adding or subtracting the change amount (difference between the previous value and the current value) of the first and second pulse width command values W1 ^* and W2 ^* to the on-time command Ton ^* . By setting the command value, the inverter output voltage is generated in the direction of canceling the time product of the voltage increased / decreased due to the change of the first and second pulse width command values W1 ^* and W2 ^* . As a result, the DC components of the inductor current iL and the exciting current iLm can be suppressed.

As shown above, according to the first embodiment, it is possible to suppress the DC components of the inductor current and the exciting current generated when the pulse width is changed. Even when the frequency of load fluctuations is high, copper loss of transformers and inductors and conduction loss of dual active bridge type bidirectional isolated DC / DC converters can be reduced.

For an apparatus known to have a small fluctuation in pulse width, magnetic saturation of the transformer can be prevented only by the first embodiment, the block configuration can be simplified as compared with the following embodiment, and the CPU. And FPGA performance can be suppressed and cost can be reduced.

[Embodiment 2]
In the first embodiment, the on-time command of each inverter leg is commanded by adding or subtracting the change amount (difference between the previous value and the current value) of the first and second pulse width command values W1 ^* and W2 ^* to the on-time command Ton ^* . By setting the value, the inverter output voltage is generated in the direction of canceling the time product of the voltage increased / decreased due to the change of the first and second pulse width command values W1 ^* and W2 ^* . As a result, the DC components of the inductor current iL and the exciting current iLm can be suppressed.

However, immediately after the changes in the first and second pulse width command values W1 ^* and W2 ^* , the off time of each inverter leg changes according to the amount of change in the pulse width, so the peak current generated within one switching cycle is suppressed. Can not. Therefore, under the condition that the first and second pulse width command values W1 ^* and W2 ^* change sharply, a peak current larger than that in the steady state is generated in the inductor current iL and the excitation current iLm.

In the second embodiment, as shown in FIG. 4, the moving average units 4 and 5 are added to the first embodiment. In the second embodiment, the inductor current when the first and second pulse width command values W1 ^* and W2 ^* change sharply by ramping up the first and second pulse width command values W1 ^* and W2 ^*. The peak values of iL and the exciting current iLm are suppressed.

As shown above, according to the second embodiment, it is possible to suppress the peak current generated when the pulse width is changed sharply. Therefore, it is possible to suppress the magnetic saturation of the transformer Tr even when the load or voltage fluctuation is large. In addition, it is possible to reduce the cross-sectional area of the transformer core, reduce the size, generate an inrush current, and prevent equipment damage.

[Embodiment 3]
In the third embodiment, as shown in FIG. 4, an initial value processing unit 6 and an initial drive processing unit 7 are added to the first embodiment or the second embodiment. In the third embodiment, the initial values of the first and second pulse width command values W1 ^* and W2 ^* and the phase difference command value θ ^* are set, and the phase difference command value θ ^* and the first and second pulse values are set by the gate enable signal. The pulse width command values W1 ^* and W2 ^* are switched to suppress the DC deviation of the inductor current and excitation current during initial drive.

FIG. 10A shows a control block diagram of the initial value processing unit 6, and FIG. 10B shows a control block of the initial drive processing unit 7. The third embodiment is characterized in the setting of the phase difference command value θ ^* at the time of initial driving and the synchronization method of the output timing of the gate enable signal.

First, the initial drive processing unit 7 will be described. As shown in FIG. 10B, the initial drive processing unit 7 includes a comparator 22 and a flip-flop 23. The comparator 22 inputs the carrier and the carrier midpoint (0.5), and outputs the comparison result. The flip-flop 23 inputs the drive start signal and the output of the comparator 22, and outputs a gate enable signal (drive or stop). The gate enable signal synchronizes with the timing of the carrier midpoint.

Next, the initial value processing unit 6 will be described. As shown in FIG. 10A, the initial value processing unit 6 includes a selector 24a, a selector 24b, and a selector 24c.

The selector 24a inputs the phase difference command values θ ^* and 0, outputs the phase difference command value θ * when the gate enable signal is driven, and outputs the phase difference command value θ ^* as the initial value phase difference command value when the gate enable signal is stopped. Output 0.

The selector 24b inputs the first pulse width command values W1 ^* and π, outputs the first pulse width command value W1 * when the gate enable signal is driven, and outputs the first pulse width command value W1 ^* when the gate enable signal is stopped. 1 Outputs π as the pulse width command value.

The selector 24c inputs the second pulse width command values W2 ^* and π, outputs the second pulse width command value W2 ^* when the gate enable signal is driven, and outputs the initial value W2 * when the gate enable signal is stopped. 2 Outputs π as the pulse width command value.

In the third embodiment, the output of the phase difference command value θ ^* , the first pulse width command value W1 ^* , the second pulse width command value W2 ^* , and the gate signal is started at the same timing as the gate enable signal.

During driving, the dual active bridge type bidirectional isolated DC / DC converter is driven so as to always achieve the phase difference command value θ ^* , the first pulse width command value W1 ^* , and the second pulse width command value W2 ^* . In the third embodiment, the flip-flop 23 is used to synchronize the timing of the gate enable signal with the midpoint or peak of the carrier.

In the Dual Active Bridge method, when the output voltage of each inverter is a square wave, the exciting current is a triangular wave. Therefore, when the rising timing of the square wave is t = 0s, the exciting current iLm can be calculated by the equation (5).

However, Tsw is the switching cycle, fsw is the switching frequency, and Lm is the excitation inductance. From the equation (5), the phase at which the exciting current iLm becomes zero is t = Tsw / 4,3Tsw / 4. This is the midpoint between the positive and negative voltage periods of the square wave inverter output voltage. Further, regardless of the first and second pulse width command values W1 ^* and W2 ^* , when the phase difference command value θ ^* is zero, it is synchronized with the midpoint or the peak of the sawtooth wave carrier.

That is, in the initial value processing unit 6, when the primary side and secondary side inverters are stopped, the phase difference command value is set to zero as the initial value, and the first and second pulse width command values are set as π as the initial value. Assuming that the secondary inverter is driven, the inverter output voltages V1 and V2 are set to be square waves. Assuming that the drive start signal is output and the primary and secondary inverters are driven, the primary and secondary inverters from the time of the midpoint of the positive period or the midpoint of the negative period of the square wave. To drive. Then, the phase difference command value θ ^* and the first and second pulse width command values W1 ^* and W2 ^* are set as normal values.

As shown above, according to the third embodiment, it is possible to suppress the DC components of the inductor current and the exciting current at the time of initial driving. Therefore, it is possible to prevent the magnetic saturation of the transformer even when the initial drive is taken into consideration, and it is possible to reduce the cross-sectional area of the transformer core and reduce the size.

[Embodiment 4]
In the third embodiment, the gate enable signal is synchronized with the midpoint of the sawtooth carrier. However, when there is a difference between the DC voltage Vdc1 on the primary side and the DC voltage Vdc2 on the secondary side, the first and second pulse width command values W1 ^* and W2 ^* differ greatly before and after the initial drive, so the moving average unit 4 When the period of, 5 is shortened, the peak values of the inductor current iL and the exciting current iLm increase due to a steep change in the pulse width.

In the fourth embodiment, the initial value processing unit 6 of the third embodiment is replaced with the block of FIG. In the fourth embodiment, the peak current at the time of initial driving is suppressed under the condition that there is a difference between the DC voltage Vdc1 on the primary side and the DC voltage Vdc2 on the secondary side. The first and second pulse width command values W1 ^* and W2 ^* at the time of initial drive are changed by the DC voltage Vdc1 on the primary side and the DC voltage Vdc2 on the secondary side. The phase difference command value θ ^* and the first and second pulse width command values W1 ^* and W2 ^* are switched by the gate enable signal.

FIG. 11 shows a control block diagram of the initial value processing unit 6 of the fourth embodiment. In the initial value processing unit 6 of the present embodiment 4, selectors 25a and 25b are added to the initial value processing unit 6 of the third embodiment. The selectors 25a and 25b change the first and second pulse width command values at the time of stop depending on the magnitude relationship between the DC voltage Vdc1 on the primary side and the DC voltage Vdc2 on the secondary side. The pulse width is calculated so that the amplitudes of the fundamental wave components of each inverter output voltage match.

In the fourth embodiment, the phase difference command value at the time of initial drive is set to zero, and the first and second pulse width command values at the time of initial drive are set so as to match the fundamental wave amplitude of each inverter output voltage. The fundamental wave amplitudes V1rms and V2rms of each inverter output voltage considering the turns ratio N (= n _pr / n _se ) shown in FIG. 1 can be calculated by the following equations (6) and (7).

The output voltage of the secondary side inverter is converted to the primary side. In the fourth embodiment, one inverter is controlled by the pulse width and the other inverter is controlled by a square wave according to the magnitude relationship of the DC voltages Vdc1 and Vdc2 on the primary side and the secondary side in consideration of the turns ratio N. Switch to. The first and second pulse width command values W1 ^* and W2 ^* of the inverter under each DC voltage condition are set as in the following equations (8) and (9).

That is, when the primary side and secondary side inverters are stopped, the initial value processing unit 6 sets the phase difference command value to zero, sets the first and second pulse width command values to the primary side DC voltage Vdc1 and the secondary side DC. Depending on the magnitude relationship of the voltage Vdc2, if it is assumed that one of them is π and the inverter is driven, the inverter output voltage is set to be a square wave, and the other is the fundamental wave of the output voltage of the primary side and secondary side inverters. Set so that the amplitudes match. Assuming that the drive start signal is output and the inverter with the pulse width command value set to π is driven, the primary side from the time of the midpoint of the positive period or the midpoint of the negative period of the square wave, Drives the secondary inverter. Even if there is a difference between the DC voltage Vdc1 on the primary side and the DC voltage Vdc2 on the secondary side, where the phase difference command value and the first and second pulse width command values are normal values, before and after the initial drive. Since the changes in the first and second pulse width command values W1 ^* and W2 ^* are small, the peak values of the inductor current iL and the excitation current iLm can be suppressed even if the cycles of the moving average portions 4 and 5 are shortened.

As shown above, according to the fourth embodiment, the peak values of the inductor current and the exciting current at the time of initial driving are suppressed even under the condition that the difference between the DC voltage Vdc1 on the primary side and the DC voltage Vdc2 on the secondary side is large. can. Therefore, the period of the moving average units 4 and 5 can be shortened as compared with the third embodiment. Therefore, the response speed of the dual active bridge type bidirectional isolated DC / DC converter can be increased, and the performance can be improved.

FIG. 12 shows the simulation results of the conventional method and the first embodiment when the pulse width is changed. The first pulse width command value W1 ^* of the primary side inverter is changed in steps. It can be seen that by applying the first embodiment, the DC components of the inductor current iL and the exciting current iLm at the time of changing the pulse width are reduced. However, immediately after the change of the first pulse width command value W1 ^* , the peak values of the inductor current iL and the exciting current iLm increase from the steady state.

FIG. 13 shows the operation waveforms of the first and second embodiments. In the second embodiment, the peak values of the inductor current iL and the exciting current iLm are suppressed by multiplying the first and second pulse width command values W1 ^* and W2 ^* by a moving average.

FIG. 14 shows the operation waveform of the third embodiment at the time of initial driving. Even after the initial drive, each inverter is driven by a square wave. From FIG. 14, the timing of the gate enable signal is synchronized with the midpoint of the carrier, and the DC components of the exciting current iLm and the inductor current iL are suppressed.

FIG. 15 shows the simulation results of the third and fourth embodiments at the time of initial driving. FIG. 15A is an operation waveform of the third embodiment, and FIG. 15B is an operation waveform of the fourth embodiment. Since there is a difference between the DC voltage Vdc1 on the primary side and the DC voltage Vdc2 on the secondary side, the first and second pulse width command values W1 ^* and W2 ^* after the initial drive are changed. Comparing FIGS. 15 (a) and 15 (b), the peak values of the inductor current iL and the excitation current iLm generated after the initial drive are suppressed by matching the fundamental wave amplitudes of the inverter output voltages during the initial drive. ing.

Although the above description has been made in detail only for the specific examples described in the present invention, it is obvious to those skilled in the art that various modifications and modifications are possible within the scope of the technical idea of the present invention. It goes without saying that such modifications and modifications fall within the scope of the claims.

1 ... Phase shift amount calculation unit 2 ... Gate signal generation unit 3 ... DC deviation suppression unit 4, 5 ... Moving average unit 6 ... Initial value processing unit 7 ... Initial drive processing unit 8a, 8b, 8c, 17a, 17b, 20a, 20b ... Gain multiplication unit 9a, 9b, 10a, 10b, 21a to 21d ... Adder 11a, 11b, 23 ... Flip-flop 12a to 12d, 22 ... Comparator 13a to 13d ... Monoflop 14a to 14d ... NOT element 15a to 15h ... Dead time generator 16a to 16h ... AND element 18a, 18b ... Buffer 19a, 19b ... Subtractor 24a, 24b, 24c, 25a, 25b ... Selector

Claims (7)

Primary side DC voltage and
Secondary side DC voltage and
A first inverter connected to the primary side DC voltage and converting the primary side DC voltage into an AC voltage,
A second inverter connected to the secondary side DC voltage and converting the secondary side DC voltage into an AC voltage,
A transformer that combines the AC outputs of the first and second inverters,
An inductor connected in series between the first and second inverters and the transformer, and / or both of the leakage inductance of the transformer.
The control unit that generates the gate signal of the first and second inverters,
It is a DAB type bidirectional isolated DC / DC converter equipped with
The control unit
The first pulse width command value that determines the pulse width of the output voltage of the first inverter, the second pulse width command value that determines the pulse width of the output voltage of the second inverter, and the first and second pulse widths. A phase shift amount calculation unit that calculates the phase shift amount based on the phase difference command value that determines the phase difference of the output voltage of the command value, and
A DC deviation suppression unit that changes the on-time of each inverter leg of the first and second inverters based on the amount of change in the first and second pulse width command values.
A gate signal generation unit that generates the gate signal based on the phase shift amount, the carrier, and the on-time.
A bidirectional isolated DC / DC converter characterized by being equipped with. The bidirectional isolated DC according to claim 1, wherein the first and second pulse width command values used in the phase shift amount calculation unit and the DC deviation suppression unit are moving average processed values. / DC converter. The control unit
When the first and second inverters are stopped, it is assumed that the first and second inverters are driven with the phase difference command value set to zero and the first and second pulse width command values set to π. Is set to be a square wave, a drive start signal is output, and it is assumed that the first and second inverters are driven, the midpoint of the positive period or the midpoint of the negative period of the square wave. Claim 1 is characterized in that the first and second inverters are driven from a time point, and an initial value processing unit having the phase difference command value and the first and second pulse width command values as normal values is provided. Or the bidirectional isolated DC / DC converter according to 2. The control unit
When the first and second inverters are stopped, the phase difference command value is set to zero, and the first and second pulse width command values are set according to the magnitude relationship between the primary side DC voltage and the secondary side DC voltage. Assuming that one of them is π and the inverter is driven, the inverter output voltage is set to be a square wave, and the other is set so that the fundamental wave amplitudes of the output voltages of the first and second inverters match. The first from the time of the midpoint of the positive period or the midpoint of the negative period of the square wave when it is assumed that the drive start signal is output and the inverter whose pulse width command value is set to π is driven. , Both of claims 1 and 2, wherein the second inverter is driven and the initial value processing unit is provided with the phase difference command value and the first and second pulse width command values as normal values. Insulated DC / DC converter. The initial value processing unit
The bidirectional insulation type according to claim 4, wherein when the first and second inverters are stopped, the first and second pulse width command values are set to the following equations (8) and (9). DC / DC converter.

Vdc1: 1st DC voltage Vdc2: 2nd DC voltage N: Transformer turns ratio W1 ^* : 1st pulse width command value W2 ^* : 2nd pulse width command value The gate signal generation unit is
A flip-flop that unifies the update timing of the phase shift amount and updates at the timing of the peak of the carrier,
A comparator that compares the output of the flip-flop with the carrier,
A monoflop that outputs High during the on-time from the time when the output of the flip-flop becomes smaller than that of the carrier.
A NOT element that inverts the output of the monoflop and
A dead time generation unit that adds a dead time to the output of the monoflop and the output of the NOT element, and
An AND element that obtains the logical product of the output of the dead time generator and the gate enable signal and outputs the gate signal of the switching device of the first and second inverters.
The bidirectionally isolated DC / DC converter according to any one of claims 1 to 5, wherein the bidirectional isolated DC / DC converter is provided. Primary side DC voltage and
Secondary side DC voltage and
A first inverter connected to the primary side DC voltage and converting the primary side DC voltage into an AC voltage,
A second inverter connected to the secondary side DC voltage and converting the secondary side DC voltage into an AC voltage,
A transformer that combines the AC outputs of the first and second inverters,
An inductor connected in series between the first and second inverters and the transformer, and / or both of the leakage inductance of the transformer.
The control unit that generates the gate signal of the first and second inverters,
It is a control method of a DAB type bidirectional isolated DC / DC converter equipped with.
The control unit
The phase shift amount calculation unit determines the pulse width of the output voltage of the first inverter, the first pulse width command value, the second pulse width command value of determining the pulse width of the output voltage of the second inverter, and the above. The phase shift amount is calculated based on the phase difference command value that determines the phase difference of the output voltage of the first and second pulse width command values.
The DC deviation suppressing unit changes the on-time of each inverter leg of the first and second inverters based on the amount of change of the first and second pulse width command values.
A method for controlling a bidirectional isolated DC / DC converter, wherein the gate signal generation unit generates the gate signal based on the phase shift amount, the carrier, and the on-time.

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