JP7298448B2 - Isolated DC/DC converter - Google Patents

Description

The present invention relates to a precharging method for an isolated DC/DC converter using a high frequency transformer.

In the conventional isolated DC/DC converter, in the case of the circuit configuration as shown in FIG. 11 and FIG. This adjustment suppresses the inrush current during pre-charging.

In Patent Document 1, an overcurrent protection circuit 14 is provided as shown in FIG. 13 as a countermeasure against inrush current when the potential difference between the primary side and the secondary side is large.

Patent Literature 2 discloses a technique for preventing rush current from flowing into a power storage device by controlling voltages of the power storage device and a capacitor connected to the power storage device to match.

JP 2017-118806 A JP 2017-123739 A JP 2018-26961 A JP 2016-208630 A

In the conventional insulated DC/DC converter, a control circuit dedicated to precharging and a current detection sensor are provided to control the current, thereby suppressing the rush current during precharging. However, since the current detection sensor is required, there is a problem that the cost of the entire device increases.

Next, in Patent Document 1, an overcurrent protection circuit 14 is provided as shown in FIG. 13 as a countermeasure against inrush current when the potential difference between the primary side and the secondary side is large. In the case of this configuration, although the inrush current can be suppressed, there is a problem that it leads to an increase in cost and size of the device.

Japanese Patent Laid-Open No. 2002-200003 does not describe the details of charging the capacitor in order to match the voltage of the capacitor with that of the power storage device before connecting the power storage device and the capacitor.

As described above, in the insulated DC/DC converter, it is possible to safely charge the voltage of the capacitor while suppressing the inrush current during precharging without providing a current detection sensor or an overcurrent protection circuit. It becomes an issue.

The present invention has been devised in view of the conventional problems described above, and one aspect thereof includes a first capacitor, first and second semiconductor elements connected in series between the positive and negative electrodes of the first capacitor, third and fourth semiconductor elements connected in series between the positive and negative electrodes of the first capacitor; a second capacitor; fifth and sixth semiconductor elements connected in series between the positive and negative electrodes of the second capacitor; seventh and eighth semiconductor elements connected in series between the positive and negative electrodes of a second capacitor; a first reactor having one end connected to a connection point of the third and fourth semiconductor elements; and the seventh and eighth semiconductors a second reactor having one end connected to a connection point of an element; a primary winding connected between the other end of the first reactor and a connection point of the first and second semiconductor elements; and a transformer having a secondary winding connected between the other end of and a connection point of the fifth and sixth semiconductor elements, wherein the first capacitor voltage and the second It is characterized by comprising a control circuit that performs voltage control according to the deviation of the voltages of the two capacitors and generates a gate signal based on the result of the voltage control.

Further, as one aspect thereof, the control circuit performs voltage control according to a deviation between the first capacitor voltage and the second capacitor voltage, and phase command for generating a primary side phase command value and a secondary side phase command value. a value generator, based on a carrier signal, the primary side phase command value, and the secondary side phase command value, gate signals for the first and second semiconductor elements and gate signals for the third and fourth semiconductor elements; and a gate generator for generating gate signals for the fifth and sixth semiconductor elements and gate signals for the seventh and eighth semiconductor elements.

Further, as one aspect thereof, the gate generation section includes a rectangular wave generation section that generates a first rectangular wave synchronized with the carrier signal, and a first A first multiplier that multiplies rectangular waves to output a second rectangular wave on the primary side and a second rectangular wave on the secondary side, and compares the second rectangular wave on the primary side with the carrier signal, generating gate signals for the first and second semiconductor elements and gate signals for the third and fourth semiconductor elements; and a first comparator for generating a gate signal for the sixth semiconductor element and a gate signal for the seventh and eighth semiconductor elements.

In another aspect, the control circuit includes a power control unit that generates a primary-side third rectangular wave and a secondary-side third rectangular wave having a desired phase difference and controls output power; A phase command value is generated by voltage control according to a deviation between the first capacitor voltage and the second capacitor voltage, and based on the third rectangular wave on the primary side, the third rectangular wave on the secondary side, and the phase command value , the gate signals of the first and second semiconductor elements, the gate signals of the third and fourth semiconductor elements, the gate signals of the fifth and sixth semiconductor elements, and the gates of the seventh and eighth semiconductor elements and an output voltage control unit that generates a signal.

Further, as one aspect thereof, the power control unit includes a rectangular wave generation unit that generates a first rectangular wave synchronized with a carrier signal, and a primary side phase command value and a secondary side phase command value that generate the first rectangular wave. A first multiplier for multiplying and outputting a second rectangular wave on the primary side and a second rectangular wave on the secondary side, and comparing the second rectangular wave on the primary side and the carrier signal to determine the output of the primary side. a first comparator that generates a third rectangular wave and compares the second rectangular wave on the secondary side with the carrier signal to generate the third rectangular wave on the secondary side; The control unit includes a triangular wave generator that generates a triangular wave for primary side phase control and a triangular wave for secondary side phase control based on the third rectangular wave on the primary side and the third rectangular wave on the secondary side; a voltage control unit that generates a phase command value according to the deviation between the capacitor voltage and the second capacitor voltage; and a phase command for the first and second semiconductor elements based on the third rectangular wave on the primary side and the phase command value. and phase command values for the third and fourth semiconductor elements, and based on the third rectangular wave on the secondary side and the phase command value, the phase command values for the fifth and sixth semiconductor elements and the phase command values for the seventh and fourth semiconductor elements are output. A second multiplier for outputting a phase command value for an eighth semiconductor element compares the phase command values for the first and second semiconductor elements with the triangular wave for primary side phase control to and comparing the phase command values of the third and fourth semiconductor elements with the triangular wave for primary side phase control to generate the gate signals of the third and fourth semiconductor elements; , the phase command value of the sixth semiconductor element and the triangular wave for secondary side phase control are compared to generate the gate signals of the fifth and sixth semiconductor elements, and the phase command values of the seventh and eighth semiconductor elements are generated. and a second comparator for comparing the triangular wave for secondary side phase control with the triangular wave for secondary side phase control to generate gate signals for the seventh and eighth semiconductor elements.

In one aspect, the control circuit makes the frequency of the carrier signal higher during preliminary charging than during normal operation.

According to the present invention, in an insulated DC/DC converter, it is possible to safely charge the voltage of the capacitor while suppressing the inrush current during precharging without providing a current detection sensor or an overcurrent protection circuit. Become.

FIG. 2 is a circuit configuration diagram showing an insulated DC/DC converter according to Embodiments 1 to 3; 4 is a time chart showing examples of operation waveforms of voltages Va, Vb, and current i1; FIG. 2 is a circuit configuration diagram showing a representative example of an insulated DC/DC converter provided with a precharging circuit; 2 is a block diagram showing a control circuit according to the first embodiment; FIG. 4 is a time chart showing various waveforms before the first embodiment is applied; 4 is a time chart showing various waveforms after application of the first embodiment; 6 is a block diagram showing a control circuit according to the second embodiment; FIG. 6 is a time chart showing an example of generated waveforms in the second embodiment; FIG. 4 is a diagram showing an example of switching patterns; FIG. 11 is a block diagram showing a control circuit in Embodiment 3; FIG. 2 is a circuit configuration diagram showing an isolated DC/DC converter in the prior art; FIG. 2 is a block diagram showing a control circuit of an isolated DC/DC converter in the prior art; FIG. 2 is a circuit configuration diagram showing an insulated DC/DC converter in Patent Document 1;

Embodiments 1 to 3 of the insulated DC/DC converter according to the present invention will be described in detail below with reference to FIGS. 1 to 10. FIG.

[Embodiment 1]
FIG. 1 shows an example of a main circuit configuration of an insulated DC/DC converter according to the first embodiment. As shown in FIG. 1, the isolated DC/DC converter has a first capacitor C1 and a second capacitor C2. The first and second semiconductor elements U1 and V1 are connected in series between the positive and negative terminals of the first capacitor C1. Also, the third and fourth semiconductor elements X1 and Y1 are connected in series between the positive and negative terminals of the first capacitor C1. The first to fourth semiconductor devices U1, V1, X1 and Y1 constitute a first power converter.

Fifth and sixth semiconductor elements U2 and V2 are connected in series between the positive and negative terminals of the second capacitor C2. Seventh and eighth semiconductor elements X2 and Y2 are connected in series between the positive and negative terminals of the second capacitor C2. The fifth to eighth semiconductor devices U2, V2, X2 and Y2 constitute a second power converter.

One end of the first reactor L1 is connected to the connection point between the third and fourth semiconductor elements X1 and Y1. One end of the second reactor L2 is connected to the connection point between the seventh and eighth semiconductor elements X2 and Y2.

The transformer Tr has a primary winding connected between the other end of the first reactor L1 and the connection point of the first and second semiconductor elements U1 and V1, and the other end of the second reactor L2 and the fifth and sixth semiconductor elements U1 and V1. A secondary winding is connected between the connection point of the semiconductor elements U2 and V2.

Here, the first and second capacitor voltages (DC voltages) are E1 and E2, the voltage of the primary winding of the transformer Tr is Va, and the voltage of the secondary winding of the transformer Tr is Vb. The current at the connection point between the third and fourth semiconductor elements X1 and Y1 is i1, and the current at the connection point between the fifth and sixth semiconductor elements U2 and V2 is i2.

FIG. 1 uses two full-bridge first and second power converters, and adjusts the phase difference δ between the voltages Va and Vb output by the two first and second power converters (that is, the first 1. Power is transmitted by adjusting the gate signal (on/off command signal) of the semiconductor element in the second power converter.

The magnitude of the output power P is defined by the following equation (1). is the switching frequency, E1 and E2 are the first and second capacitor voltages (DC voltages), L is the inductance value (L1+L2) of the first and second reactors, and .delta. is the phase difference between the voltages Va and Vb.

As can be seen from the equation (1), by making the phase difference δ variable, the currents flowing through the first and second reactors L1 and L2 can be controlled, so the output power P can be controlled. The output power P that can be output becomes maximum when the phase difference δ=90°. Note that the formula (1) is a theoretical formula that does not consider the loss of the transformer Tr.

FIG. 2 shows examples of operating waveforms of voltages Va, Vb and current i1 in the circuit of FIG. When the voltage Va is positive, the gate signal turns on the second and third semiconductor elements V1 and X1. When the voltage Va is negative, the gate signal turns on the first and fourth semiconductor elements U1 and Y1. When the voltage Vb is positive, the gate signal turns on the sixth and seventh semiconductor elements V2 and X2. When the voltage Vb is negative, the gate signal turns on the fifth and eighth semiconductor elements U2 and Y2. Also, the switching cycle Ts is Ts=2π/ω.

In an application where the circuit in FIG. 1 is connected to a DC bus, a circuit configuration as shown in FIG. 3 is conceivable for precharging. In the first embodiment, a preliminary charging method for connecting an insulated DC/DC converter to a DC bus with established voltage will be described. As shown in FIG. 3, a switch SW1 is connected between the DC bus 21 and the first capacitor C1. A preliminary charging circuit 20 is connected in parallel to the switch SW1. The pre-charging circuit 20 includes a pre-charging resistor R and a switch SW2 connected in series with the pre-charging resistor R.

In this case, the first capacitor C1 and the second capacitor C2 are simultaneously charged by starting the operation of the first and second power converters at the same time that the preliminary charging circuit 20 (switch SW2) shown in FIG. 3 is turned on. and the charging current can be suppressed.

However, when the capacitance of the second capacitor C2 is larger than that of the first capacitor C1, the time constants are different, so the first capacitor voltage E1 transiently becomes higher than the second capacitor voltage E2. As a result, there are cases where a large charging current is generated.

Excessive charging current may shorten the life of the capacitor and burn out the transformer and converter, so it is necessary to prevent it. As an example of a solution to this problem, an overcurrent prevention circuit such as that disclosed in Patent Document 1 is effective in suppressing the current, but it is not desirable because it requires additional parts, which leads to an increase in cost and an increase in volume. The first embodiment is a control method for solving the above problem.

Embodiment 1 will explain a technique for preventing a rush current during precharging without using a current detection sensor and an overcurrent prevention circuit as in the prior art.

In the first embodiment, in the configuration shown in FIG. 3, the inrush current is suppressed by reducing the deviation between the first capacitor voltage E1 and the second capacitor voltage E2 that occurs transiently during precharging. FIG. 4 shows the configuration of a specific control circuit.

The circuit of FIG. 4 controls transmission power by controlling the phase difference .delta. When the deviation between the first capacitor voltage E1 and the second capacitor voltage E2 is large, the transmission power is increased by increasing the phase difference δ, and the deviation between the first capacitor voltage E1 and the second capacitor voltage E2 is decreased. , to suppress the inrush current.

As shown in FIG. 4 , the control circuit of the first embodiment includes a phase command value generator 1 and a gate generator 2 .

In the subtractor 3, the phase command value generator 1 calculates the deviation between the first capacitor voltage E1 and the second capacitor voltage E2. The PI control unit 4 performs voltage control based on the magnitude of the deviation and generates a primary side phase command value and a secondary side phase command value.

The gate generator 2 first inputs a carrier signal to the rectangular wave generator 5 to generate a first rectangular wave synchronized with the carrier signal. The first multipliers 6a and 6b multiply the primary side phase command value, the secondary side phase command value, and the amplitude of the first rectangular wave to adjust the amplitudes of the second rectangular wave on the primary side and the second rectangular wave on the secondary side. Generate a square wave. The first comparator 7a compares the second square wave on the primary side with the carrier signal to generate gate signals for the third and fourth semiconductor elements X1 and Y1 and gate signals for the first and second semiconductor elements U1 and V1. to generate The first comparator 7b compares the second square wave on the secondary side with the carrier signal to generate gate signals for the seventh and eighth semiconductor elements X2 and Y2 and gate signals for the fifth and sixth semiconductor elements U2 and V2. Generate a gate signal. Thereby, a gate signal having a necessary phase difference δ between the primary side and the secondary side can be generated.

FIG. 5 shows an example of operating waveforms before applying the first embodiment, and FIG. 6 shows an example of operating waveforms after applying the first embodiment. As can be seen by comparing FIG. 5 and FIG. 6, the currents i1 and i2 can be suppressed as compared with the case where no control is performed.

As described above, according to the first embodiment, during preliminary charging, it is possible to safely charge the voltage of the capacitor while suppressing the inrush current without providing a current detection sensor or an overcurrent prevention circuit. .

[Embodiment 2]
In the second embodiment, when the difference between the first capacitor voltage E1 and the second capacitor voltage E2 is large, the output voltage of the power converter having the larger voltage is reduced to suppress the inrush current.

FIG. 7 shows the control circuit in the second embodiment, and FIG. 8 shows an example of generated waveforms. The control circuit of FIG. 7 according to Embodiment 2 includes a power control section 8 and an output voltage control section 9 . The power control unit 8 generates primary-side and secondary-side output voltages having a phase difference δ according to the primary-side phase command value and the secondary-side phase command value. The output voltage control section 9 adjusts the output voltage according to the magnitude of the deviation between the first capacitor voltage E1 and the second capacitor voltage E2.

The power controller 8 first inputs a carrier signal to the rectangular wave generator 5 to generate a first rectangular wave synchronized with the carrier signal. After that, the first multipliers 6a and 6b multiply the primary side phase command value, the secondary side phase command value, and the amplitude of the first rectangular wave to adjust the amplitude of the second rectangular wave on the primary side and the amplitude on the secondary side. Generate a second square wave. The first comparators 7a and 7b compare the second rectangular wave with the carrier signal to generate a third rectangular wave on the primary side and a third rectangular wave on the secondary side with a desired phase difference δ. Thereby, a gate signal having a required phase difference δ between the primary side and the secondary side can be generated.

The output voltage control unit 9 inputs the primary-side third rectangular wave and the secondary-side third rectangular wave generated by the power control unit 8 . The triangular wave generators 10a and 10b generate a triangular wave for phase control on the primary side and a triangular wave for phase control on the secondary side synchronized with the third rectangular wave on the primary side and the third rectangular wave on the secondary side.

Also, the phase command value that determines the magnitude of the output voltage is generated according to the magnitude of the deviation between the first capacitor voltage E1 and the second capacitor voltage E2. That is, the subtractor 3 calculates the deviation between the first capacitor voltage E1 and the second capacitor voltage E2. The PI control unit 4 performs voltage control based on the deviation and generates a phase command value.

In the second multipliers 11a to 11d, the third rectangular wave on the primary side and the third rectangular wave on the secondary side are multiplied by the phase command value to obtain the third rectangular wave on the primary side and the third rectangular wave on the secondary side. The phase command values for the third and fourth semiconductor elements X1 and Y1, the phase command values for the first and second semiconductor elements U1 and V1, the phase command values for the seventh and eighth semiconductor elements X2 and Y2, and the fifth , the phase command values of the sixth semiconductor devices U2 and V2.

Then, the second comparator 12a compares the triangular wave for phase control on the primary side with the phase command values of the third and fourth semiconductor elements X1 and Y1 to generate gate signals for the third and fourth semiconductor elements X1 and Y1. do. The second comparator 12b compares the triangular wave for primary side phase control with the phase command values for the first and second semiconductor elements U1 and V1 to generate gate signals for the first and second semiconductor elements U1 and V1. The second comparator 12c compares the triangular wave for secondary side phase control with the phase command values of the seventh and eighth semiconductor elements X2 and Y2 to generate gate signals for the seventh and eighth semiconductor elements X2 and Y2. . The second comparator 12d compares the triangular wave for secondary side phase control with the phase command values of the fifth and sixth semiconductor elements U2 and V2 to generate gate signals for the fifth and sixth semiconductor elements U2 and V2. . This makes it possible to generate a gate signal that has a required phase difference δ between the primary side and the secondary side and that can output a desired output voltage value.

FIG. 9 shows the difference in operating waveforms between the conventional method and the second embodiment. FIG. 9 shows operation waveforms on the primary side, and operation waveforms on the secondary side are omitted. U1, X1, V1, and Y1 in FIG. 9 represent the conduction state (gate signal) of each semiconductor element. As shown in FIG. 9B, the second embodiment has phase command values for the first and second semiconductor elements U1 and V1 and phase command values for the third and fourth semiconductor elements X1 and Y1. The phase command values for the first and second semiconductor elements U1 and V1 and the phase command values for the third and fourth semiconductor elements X1 and Y1 are rectangular waves synchronized with the carrier frequency and have a phase difference.

As shown in FIG. 9(b), by comparing the triangular wave for primary side phase control and the phase command values of the first and second semiconductor elements U1 and V1, the conducting state ( gate signal). Also, by comparing the triangular wave for primary side phase control and the phase command values of the third and fourth semiconductor elements X1 and Y1, the conductive states (gate signals) of the third and fourth semiconductor elements X1 and Y1 are controlled.

For example, when the phase command values of the first and second semiconductor elements U1 and V1 are larger than the triangular wave for primary side phase control, the first semiconductor element U1 is turned off, the second semiconductor element V1 is turned on, and the primary side phase When the phase command values of the third and fourth semiconductor elements X1 and Y1 are larger than the control triangular wave, the third semiconductor element X1 is turned on and the fourth semiconductor element Y1 is turned off.

Further, by controlling the amplitude of the phase command values of the first and second semiconductor elements U1 and V1 and the phase command values of the third and fourth semiconductor elements X1 and Y1, the gates of the first and second semiconductor elements U1 and V1 are controlled. The phase difference between the signal and the gate signal of the third and fourth semiconductor elements X1 and Y1 can be controlled. When the amplitudes of the phase command values of the first and second semiconductor elements U1 and V1 and the phase command values of the third and fourth semiconductor elements X1 and Y1 are 0, the first and second semiconductor elements U1 and V1 and the third , the fourth semiconductor elements X1 and Y1 have a phase difference of 0°.

In the case of the conventional method, the phase difference between the gate signals of the first and second semiconductor elements U1 and V1 and the gate signals of the third and fourth semiconductor elements X1 and Y1 is 0°. becomes a square wave.

In contrast, in the second embodiment, the phase difference between the gate signals of the first and second semiconductor elements U1 and V1 and the gate signals of the third and fourth semiconductor elements X1 and Y1 is made larger than 0°. , the voltage applied to the transformer Tr has a three-step waveform. As a result, the effective value of the applied voltage can be reduced, so that the excitation current can be reduced.

Further, when the phase command value is 0, a square-wave output voltage is output, so an output voltage corresponding to the DC voltage is output. On the other hand, when the phase command value is 0 or more, the output voltage has a three-step waveform including a period of 0, so the output voltage can be lowered. Since the flowing current is proportional to the output voltage value, the inrush current can be suppressed.

As described above, according to the second embodiment, during preliminary charging, it is possible to safely charge the voltage of the capacitor while suppressing the inrush current without providing a current detection sensor or an overcurrent prevention circuit. .

[Embodiment 3]
In the third embodiment, by increasing the frequency of the carrier signal, the inrush current that occurs during preliminary charging is suppressed. Since the inrush current has a characteristic that is inversely proportional to the carrier frequency, the inrush current can be changed by changing the carrier frequency. The control circuit of Embodiment 1 or Embodiment 2 is applied.

FIG. 10 shows a control circuit in the third embodiment. The circuit of FIG. 10 is characterized in that a selection circuit 13 is added to the circuit of FIG. A selection circuit 13 inputs a normal carrier signal and a pre-charging carrier signal. Here, it is assumed that the pre-charging carrier signal has a higher carrier frequency than the normal carrier signal.

The selection circuit 13 outputs a normal carrier signal during normal operation, and outputs a preliminary charging carrier signal during preliminary charging. As a result, the carrier frequency becomes higher during pre-charging than during normal operation, making it possible to suppress rush current.

Although the method of applying the third embodiment to the first embodiment has been described here, the third embodiment may be applied to the second embodiment.

As described above, according to the third embodiment, in addition to the effects of the first and second embodiments, it is possible to suppress the inrush current by setting the carrier frequency high during preliminary charging.

Although the present invention has been described in detail only with respect to the specific examples described above, it is obvious to those skilled in the art that various modifications and modifications are possible within the scope of the technical idea of the present invention. Such variations and modifications are, of course, covered by the claims.

U1, V1, X1, Y1, U2, V2, X2, Y2... First to eighth semiconductor elements L1, L2... First and second reactors C1, C2... First and second capacitors Tr... Transformer 1... Phase command DESCRIPTION OF SYMBOLS Value generation part 2... Gate generation part 3... Subtractor 4... PI control part 5... Rectangular wave generation part 6a, 6b... First multiplier 7a, 7b... First comparator 8... Power control part 9... Output voltage control part 10a, 10b... triangular wave generator 11a to 11d... second multiplier 12a to 12d... second comparator 13... selection circuit

Claims (4)

a first capacitor;
first and second semiconductor elements connected in series between the positive and negative electrodes of the first capacitor;
third and fourth semiconductor elements connected in series between the positive and negative electrodes of the first capacitor;
a second capacitor;
fifth and sixth semiconductor elements connected in series between the positive and negative electrodes of the second capacitor;
seventh and eighth semiconductor elements connected in series between the positive and negative electrodes of the second capacitor;
a first reactor having one end connected to a connection point of the third and fourth semiconductor elements;
a second reactor having one end connected to a connection point of the seventh and eighth semiconductor elements;
A primary winding is connected between the other end of the first reactor and a connection point between the first and second semiconductor elements, and a connection point between the other end of the second reactor and the fifth and sixth semiconductor elements. a transformer having a secondary winding connected between
a control circuit;
An isolated DC/DC converter comprising:
The control circuit is
a phase command value generation unit that performs voltage control according to a deviation between the first capacitor voltage and the second capacitor voltage to generate a primary side phase command value and a secondary side phase command value;
a gate generator;
with
The gate generation unit
a rectangular wave generator that generates a first rectangular wave synchronized with a carrier signal;
a first multiplier that multiplies the primary-side phase command value and the secondary-side phase command value by the first rectangular wave, respectively, and outputs a second rectangular wave on the primary side and a second rectangular wave on the secondary side;
The second square wave on the primary side and the carrier signal are compared to generate gate signals for the first and second semiconductor elements and gate signals for the third and fourth semiconductor elements, and a first comparator that compares the second rectangular wave with the carrier signal to generate gate signals for the fifth and sixth semiconductor elements and gate signals for the seventh and eighth semiconductor elements;
with
The control circuit is
An isolated DC/DC converter that generates a gate signal that reduces a deviation between the first capacitor voltage and the second capacitor voltage during precharging based on the result of the voltage control. a first capacitor;
first and second semiconductor elements connected in series between the positive and negative electrodes of the first capacitor;
third and fourth semiconductor elements connected in series between the positive and negative electrodes of the first capacitor;
a second capacitor;
fifth and sixth semiconductor elements connected in series between the positive and negative electrodes of the second capacitor;
seventh and eighth semiconductor elements connected in series between the positive and negative electrodes of the second capacitor;
a first reactor having one end connected to a connection point of the third and fourth semiconductor elements;
a second reactor having one end connected to a connection point of the seventh and eighth semiconductor elements;
A primary winding is connected between the other end of the first reactor and a connection point between the first and second semiconductor elements, and a connection point between the other end of the second reactor and the fifth and sixth semiconductor elements. a transformer having a secondary winding connected between
a control circuit;
An isolated DC/DC converter comprising:
The control circuit is
a power control unit that generates a primary-side third rectangular wave and a secondary-side third rectangular wave having a desired phase difference and controls output power;
A phase command value is generated by voltage control according to the deviation between the first capacitor voltage and the second capacitor voltage, and based on the third rectangular wave on the primary side, the third rectangular wave on the secondary side, and the phase command value , the gate signals of the first and second semiconductor elements, the gate signals of the third and fourth semiconductor elements, the gate signals of the fifth and sixth semiconductor elements, and the gates of the seventh and eighth semiconductor elements an output voltage controller that generates a signal;
with
The control circuit is
The voltage control is performed according to the deviation between the first capacitor voltage and the second capacitor voltage, and the deviation between the first capacitor voltage and the second capacitor voltage is reduced during precharging based on the result of the voltage control. An isolated DC/DC converter that generates a gate signal . The power control unit
a rectangular wave generator that generates a first rectangular wave synchronized with a carrier signal;
a first multiplier that multiplies the primary-side phase command value and the secondary-side phase command value by the first rectangular wave, respectively, and outputs a primary-side second rectangular wave and a secondary-side second rectangular wave;
The second rectangular wave on the primary side and the carrier signal are compared to generate a third rectangular wave on the primary side, and the second rectangular wave on the secondary side and the carrier signal are compared to generate the secondary wave. a first comparator that generates a third rectangular wave on the side of
The output voltage control unit
a triangular wave generator that generates a triangular wave for primary side phase control and a triangular wave for secondary side phase control based on the third rectangular wave on the primary side and the third rectangular wave on the secondary side;
a voltage control unit that generates the phase command value according to the deviation between the first capacitor voltage and the second capacitor voltage;
Based on the third rectangular wave on the primary side and the phase command value, phase command values for the first and second semiconductor elements and phase command values for the third and fourth semiconductor elements are output, and the third rectangular wave on the secondary side is output. a second multiplier that outputs phase command values for fifth and sixth semiconductor elements and phase command values for seventh and eighth semiconductor elements based on the rectangular wave and the phase command value;
Phase command values for the first and second semiconductor elements are compared with the triangular wave for primary side phase control to generate gate signals for the first and second semiconductor elements, and phases for the third and fourth semiconductor elements are generated. A command value is compared with the triangular wave for primary side phase control to generate a gate signal for the third and fourth semiconductor elements, and a phase command value for the fifth and sixth semiconductor elements and the secondary side phase control The triangular wave is compared with the fifth and sixth semiconductor elements to generate gate signals for the fifth and sixth semiconductor elements, and the phase command values of the seventh and eighth semiconductor elements are compared with the triangular wave for secondary side phase control to generate the seventh semiconductor element. , and a second comparator for generating a gate signal for the eighth semiconductor device. The control circuit is
4. The insulated DC/DC converter according to claim 1 , wherein the frequency of said carrier signal is set higher during pre-charging than during normal operation.

Images