JP2021078274A - Insulated dc/dc converter - Google Patents

Abstract

To charge the voltage of a capacitor safely, while suppressing the inrush current during pre-charging without installing a sensor for current detection or an overcurrent prevention circuit, in the insulated DC/DC converter.SOLUTION: In a control circuit of the insulated DC/DC converter, voltage control is performed according to the deviation between a first capacitor voltage E1 and a second capacitor voltage E2. Then gate signals g of semiconductor devices U1, V1, X1, Y1, U2, V2, X2, Y2 in the isolated DC/DC capacitor, are generated based on the result of the voltage control.SELECTED DRAWING: Figure 4

Description

The present invention relates to a precharging method for an insulated DC / DC converter using a high frequency transformer.

In the isolated DC / DC converter in the prior art, in the case of the circuit configuration shown in FIGS. 11 and 12, in order to precharge the secondary side, the output voltage value on the primary side is set based on the detected current value. By adjusting, the inrush current at the time of pre-charging is suppressed.

In Patent Document 1, an overcurrent prevention circuit 14 is provided as shown in FIG. 13 as a countermeasure against an inrush current when the potential difference between the primary side and the secondary side is large.

Patent Document 2 discloses a technique for preventing an inrush current flowing through a power storage device by controlling the voltage of the power storage device and a capacitor connected to the power storage device to match.

Japanese Unexamined Patent Publication No. 2017-118806 JP-A-2017-123739 Japanese Unexamined Patent Publication No. 2018-26961 Japanese Unexamined Patent Publication No. 2016-208630

In the isolated DC / DC converter in the prior art, a control circuit dedicated to precharging and a current detection sensor are provided, and the inrush current at the time of precharging is suppressed by controlling the current. However, since a sensor for current detection is required, there is a problem that the cost of the entire device is increased.

Next, in Patent Document 1, an overcurrent prevention circuit 14 is provided as shown in FIG. 13 as a countermeasure against an inrush current when the potential difference between the primary side and the secondary side is large. In the case of this configuration, the inrush current can be suppressed, but there is a problem that it leads to an increase in cost and an increase in size of the device.

Patent Document 2 requires charging in order to match the voltage of the capacitor with the power storage device before connecting the power storage device and the capacitor, but the details thereof are not described.

From the above, it is possible to safely charge the capacitor voltage while suppressing the inrush current during precharging without providing a current detection sensor or overcurrent prevention circuit in the isolated DC / DC converter. It becomes an issue.

The present invention has been devised in view of the above-mentioned conventional problems, and one embodiment thereof includes a first capacitor, first and second semiconductor elements connected in series between the positive and negative electrodes of the first capacitor, and the like. The third and fourth semiconductor elements connected in series between the positive and negative electrodes of the first capacitor, the second capacitor, the fifth and sixth semiconductor elements connected in series between the positive and negative electrodes of the second capacitor, and the above. The 7th and 8th semiconductor elements connected in series between the positive and negative sides of the 2nd capacitor, the 1st reactor having one end connected to the connection point of the 3rd and 4th semiconductor elements, and the 7th and 8th semiconductors. The first winding is connected between the second reactor whose one end is connected to the connection point of the element, the other end of the first reactor, and the connection point of the first and second semiconductor elements, and the second reactor. An isolated DC / DC converter comprising a transformer in which a secondary winding is connected between the other end of the device and the connection point of the fifth and sixth semiconductor elements, the first capacitor voltage and the first capacitor. (2) It is characterized in that it is provided with a control circuit that performs voltage control according to the deviation of the capacitor voltage and generates a gate signal based on the result of the voltage control.

Further, as one aspect thereof, the control circuit performs voltage control according to the deviation between the first capacitor voltage and the second capacitor voltage, and generates a primary side phase command value and a secondary side phase command value. Based on the value generator, the carrier signal, the primary side phase command value, and the secondary side phase command value, the gate signal of the first and second semiconductor elements and the gate signal of the third and fourth semiconductor elements. It is characterized by including a gate signal of the 5th and 6th semiconductor elements and a gate generation unit for generating a gate signal of the 7th and 8th semiconductor elements.

Further, as one aspect thereof, the gate generation unit includes a square wave generation unit that generates a first square wave synchronized with the carrier signal, the primary side phase command value, and the secondary side phase command value. A first multiplier that multiplies a square wave and outputs a second square wave on the primary side and a second square wave on the secondary side, and the second square wave on the primary side and the carrier signal are compared. The gate signal of the first and second semiconductor elements and the gate signal of the third and fourth semiconductor elements are generated, and the second square wave on the secondary side and the carrier signal are compared with each other to compare the fifth and fifth. It is characterized by including a gate signal of the sixth semiconductor element and a first comparator that generates a gate signal of the seventh and eighth semiconductor elements.

As another aspect, the control circuit includes a power control unit that controls output power by generating a third rectangular wave on the primary side and a third rectangular wave on the secondary side having a desired phase difference, and the first. A phase command value is generated by voltage control according to the deviation between the voltage of one capacitor and the voltage of the second capacitor, and based on the third rectangular wave on the primary side, the third rectangular wave on the secondary side, and the phase command value. , The gate signal of the first and second semiconductor elements, the gate signal of the third and fourth semiconductor elements, the gate signal of the fifth and sixth semiconductor elements, and the gate of the seventh and eighth semiconductor elements. It is characterized by including a signal and an output voltage control unit that generates a signal.

Further, as one aspect thereof, the power control unit uses a square wave generation unit that generates a first square wave synchronized with a carrier signal, and the first square wave for the primary side phase command value and the secondary side phase command value. The first multiplier that outputs the second square wave on the primary side and the second square wave on the secondary side by multiplying each of them, and the second square wave on the primary side and the carrier signal are compared with each other on the primary side. The output voltage includes a first comparator that generates a third square wave and compares the second square wave on the secondary side with the carrier signal to generate the third square wave on the secondary side. The control unit includes a triangular wave generation unit that generates a primary side phase control triangular wave and a secondary side phase control triangular wave based on the primary side third square wave and the secondary side third square wave, and the first A voltage control unit that generates a phase command value according to the deviation between the capacitor voltage and the second capacitor voltage, and a phase command of the first and second semiconductor elements based on the first square wave and the phase command value on the primary side. The value and the phase command value of the third and fourth semiconductor elements are output, and based on the third square wave on the secondary side and the phase command value, the phase command value of the fifth and sixth semiconductor elements and the seventh, The first and second semiconductor elements are compared with the second multiplier that outputs the phase command value of the eighth semiconductor element, the phase command values of the first and second semiconductor elements, and the primary side phase control triangular wave. The gate signal of the third and fourth semiconductor elements is generated, and the phase command value of the third and fourth semiconductor elements is compared with the triangular wave for primary side phase control to generate the gate signal of the third and fourth semiconductor elements. , The phase command value of the 6th semiconductor element is compared with the triangular wave for secondary side phase control to generate the gate signal of the 5th and 6th semiconductor elements, and the phase command value of the 7th and 8th semiconductor elements. It is characterized in that it is provided with a second comparator that compares the square wave for secondary side phase control with the square wave for generating the gate signal of the seventh and eighth semiconductor elements.

Further, as one aspect thereof, the control circuit is characterized in that the frequency of the carrier signal is set higher than that of the carrier signal during normal operation at the time of precharging.

According to the present invention, in an insulated DC / DC converter, it is possible to safely charge the voltage of a capacitor while suppressing an inrush current during precharging without providing a current detection sensor or an overcurrent prevention circuit. Become.

The circuit block diagram which shows the insulation type DC / DC converter in Embodiments 1-3. A time chart showing an example of operating waveforms of voltages Va, Vb, and current i1. The circuit block diagram which shows the typical example of the insulation type DC / DC converter provided with the precharging circuit. The block diagram which shows the control circuit in Embodiment 1. FIG. Embodiment 1 A time chart showing various waveforms before application. Embodiment 1 A time chart showing various waveforms after application. The block diagram which shows the control circuit in Embodiment 2. A time chart showing an example of a generated waveform in the second embodiment. The figure which shows the example of a switching pattern. The block diagram which shows the control circuit in Embodiment 3. The circuit block diagram which shows the insulation type DC / DC converter in the prior art. The block diagram which shows the control circuit of the insulation type DC / DC converter in the prior art. The circuit block diagram which shows the insulation type DC / DC converter in Patent Document 1. FIG.

Hereinafter, embodiments 1 to 3 of the insulated DC / DC converter according to the present invention will be described in detail with reference to FIGS. 1 to 10.

[Embodiment 1]
FIG. 1 shows an example of a main circuit configuration of the insulated DC / DC converter according to the first embodiment. As shown in FIG. 1, the isolated DC / DC converter has a first capacitor C1 and a second capacitor C2. The first and second semiconductor elements U1 and V1 are connected in series between the positive and negative electrodes of the first capacitor C1. Further, the third and fourth semiconductor elements X1 and Y1 are connected in series between the positive and negative electrodes of the first capacitor C1. The first power converter is composed of the first to fourth semiconductor elements U1, V1, X1, Y1.

The fifth and sixth semiconductor elements U2 and V2 are connected in series between the positive and negative electrodes of the second capacitor C2. The seventh and eighth semiconductor elements X2 and Y2 are connected in series between the positive and negative electrodes of the second capacitor C2. The fifth and eighth semiconductor elements U2, V2, X2, and Y2 constitute a second power converter.

One end of the first reactor L1 is connected to the connection points of the third and fourth semiconductor elements X1 and Y1. One end of the second reactor L2 is connected to the connection points of the seventh and eighth semiconductor elements X2 and Y2.

In the transformer Tr, the primary winding is connected between the other end of the first reactor L1 and the connection points of the first and second semiconductor elements U1 and V1, and the other end of the second reactor L2 and the fifth and sixth transformers Tr. A secondary winding is connected between the connection points of the semiconductor elements U2 and V2.

Here, the first and second capacitor voltages (DC voltage) are E1 and E2, the voltage of the primary winding of the transformer Tr is Va, and the voltage of the secondary winding of the transformer Tr is Vb. Further, the current at the connection points of the third and fourth semiconductor elements X1 and Y1 is defined as i1, and the current at the connection points of the fifth and sixth semiconductor elements U2 and V2 is defined as i2.

In FIG. 1, two full-bridge first and second power converters are used, and the phase difference δ of the voltages Va and Vb output by the two first and second power converters is adjusted (that is, the first). Electric power is transmitted by (1) adjusting the gate signal (on / off command signal) of the semiconductor element in the second power converter).

The magnitude of the output power P is defined by the following equation (1). ω represents the switching frequency, E1 and E2 represent the first and second capacitor voltages (DC voltage), L represents the inductance values of the first and second reactors (L1 + L2), and δ represents the phase difference between the voltages Va and Vb.

As can be seen from the equation (1), the output power P can be controlled because the current flowing through the first and second reactors L1 and L2 can be controlled by making the phase difference δ variable. The output power P that can be output when the phase difference δ = 90 ° is maximum. The formula (1) is a theoretical formula that does not consider the loss of the transformer Tr.

FIG. 2 is an example of operating waveforms of voltages Va, Vb, and current i1 in the circuit of FIG. When the voltage Va is positive, the second and third semiconductor elements V1 and X1 are turned on by the gate signal. When the voltage Va is negative, the first and fourth semiconductor elements U1 and Y1 are turned on by the gate signal. When the voltage Vb is positive, the sixth and seventh semiconductor elements V2 and X2 are turned on by the gate signal. When the voltage Vb is negative, the fifth and eighth semiconductor elements U2 and Y2 are turned on by the gate signal. The switching period Ts is Ts = 2π / ω.

In an application in which the circuit of FIG. 1 is connected to a DC bus, a circuit configuration as shown in FIG. 3 can be considered when precharging is performed. In the first embodiment, a precharging method when an isolated DC / DC converter is connected to a DC bus having an established voltage will be described. As shown in FIG. 3, a switch SW1 is connected between the DC bus 21 and the first capacitor C1. Further, a preliminary charging circuit 20 is connected in parallel to the switch SW1. The pre-charging circuit 20 includes a pre-charging resistor R and a switch SW2 connected in series to the pre-charging resistor R.

In this case, the first capacitor C1 and the second capacitor C2 are charged at the same time by starting the operation of the first and second power converters at the same time when the preliminary charging circuit 20 (switch SW2) shown in FIG. 3 is turned on. However, the charging current can be suppressed.

However, when the capacitance of the second capacitor C2 is larger than that of the first capacitor C1, the time constant is different, so that the first capacitor voltage E1 is transiently larger than the second capacitor voltage E2. As a result, a large charging current may be generated in some cases.

Excessive charging current may shorten the life of the capacitor and burn out the transformer and converter, so it is necessary to prevent it. As an example of the solution, an overcurrent prevention circuit as in Patent Document 1 is effective for current suppression, but it is not desirable because it leads to cost increase and volume increase because additional parts are required. The first embodiment is a control method for solving the above-mentioned problems.

The first embodiment describes a method capable of preventing an inrush current at the time of precharging without using a current detection sensor and an overcurrent prevention circuit as in the prior art.

In the first embodiment, in the configuration as shown in FIG. 3, the inrush current is suppressed by reducing the deviation between the first capacitor voltage E1 and the second capacitor voltage E2 that are transiently generated during precharging. A specific configuration of the control circuit is shown in FIG.

The circuit of FIG. 4 controls the transmission power by controlling the phase difference δ of the output voltages on the primary side and the secondary side according to the magnitude of the deviation between the first capacitor voltage E1 and the second capacitor voltage E2. When the deviation between the first capacitor voltage E1 and the second capacitor voltage E2 is large, the transmission power is increased by increasing the phase difference δ, and the deviation between the first capacitor voltage E1 and the second capacitor voltage E2 is decreased. , Suppress the inrush current.

As shown in FIG. 4, the control circuit of the first embodiment includes a phase command value generation unit 1 and a gate generation unit 2.

The phase command value generation unit 1 calculates the deviation between the first capacitor voltage E1 and the second capacitor voltage E2 in the subtractor 3. The PI control unit 4 performs voltage control based on the magnitude of the deviation, and generates a primary side phase command value and a secondary side phase command value.

The gate generation unit 2 first inputs a carrier signal to the square wave generation unit 5 to generate a first rectangular wave synchronized with the carrier signal. The first multipliers 6a and 6b adjust the amplitude by multiplying the primary side phase command value, the secondary side phase command value and the amplitude of the first square wave, and adjust the amplitude by multiplying the primary side phase command value and the secondary side phase command value with the amplitude of the first square wave. Generate a square wave. The first comparator 7a compares the second square wave on the primary side with the carrier signal to obtain the gate signal of the third and fourth semiconductor elements X1 and Y1, and the gate signal of the first and second semiconductor elements U1 and V1. To generate. The first comparator 7b compares the second square wave on the secondary side with the carrier signal to obtain the gate signals of the seventh and eighth semiconductor elements X2 and Y2, and the fifth and sixth semiconductor elements U2 and V2. Generate a gate signal. As a result, a gate signal having a necessary phase difference δ between the primary side and the secondary side can be generated.

FIG. 5 shows an example of an operation waveform before the application of the first embodiment, and FIG. 6 shows an example of an operation waveform after the application of the first embodiment. As can be seen by comparing FIGS. 5 and 6, it can be seen that the currents i1 and i2 can be suppressed as compared with the case where the control is not performed.

As shown above, according to the first embodiment, it is possible to safely charge the voltage of the capacitor while suppressing the inrush current without providing a current detection sensor or an overcurrent prevention circuit during precharging. ..

[Embodiment 2]
In the second embodiment, when the deviation between the first capacitor voltage E1 and the second capacitor voltage E2 is large, the inrush current is suppressed by reducing the output voltage of the power converter having the larger voltage.

The control circuit in the second embodiment is shown in FIG. 7, and an example of the generated waveform is shown in FIG. The control circuit of FIG. 7 according to the second embodiment includes a power control unit 8 and an output voltage control unit 9. The power control unit 8 generates output voltages on the primary side and the secondary side having a phase difference δ according to the primary side phase command value and the secondary side phase command value. The output voltage control unit 9 adjusts the output voltage according to the magnitude of the deviation between the first capacitor voltage E1 and the second capacitor voltage E2.

The power control unit 8 first inputs a carrier signal to the square wave generation unit 5 to generate a first rectangular wave synchronized with the carrier signal. After that, the first multipliers 6a and 6b are adjusted by multiplying the primary side phase command value, the secondary side phase command value and the amplitude of the first square wave to adjust the amplitudes of the primary side second square wave and the secondary side. Generate a second square wave. The first comparators 7a and 7b generate a third square wave on the primary side and a third square wave on the secondary side having a desired phase difference δ by comparing the second square wave with the carrier signal. As a result, a gate signal having a required phase difference δ between the primary side and the secondary side can be generated.

The output voltage control unit 9 inputs the third rectangular wave on the primary side and the third rectangular wave on the secondary side generated by the power control unit 8. The triangular wave generation units 10a and 10b generate a third rectangular wave on the primary side, a triangular wave for primary side phase control synchronized with the third rectangular wave on the secondary side, and a triangular wave for secondary side phase control.

Further, the phase command value that determines the magnitude of the output voltage is generated according to the magnitude of the deviation between the first capacitor voltage E1 and the second capacitor voltage E2. That is, in the subtractor 3, the deviation between the first capacitor voltage E1 and the second capacitor voltage E2 is calculated. The PI control unit 4 performs voltage control based on the deviation and generates a phase command value.

In the second multipliers 11a to 11d, the third square wave on the primary side and the third square wave on the secondary side are multiplied by the phase command value, and the third square wave on the primary side and the third square wave on the secondary side are combined. Adjusted, the phase command value of the third and fourth semiconductor elements X1 and Y1, the phase command value of the first and second semiconductor elements U1 and V1, the phase command value of the seventh and eighth semiconductor elements X2 and Y2, the fifth. , The phase command value of the sixth semiconductor elements U2 and V2 is output.

Then, in the second comparator 12a, the triangular wave for primary side phase control is compared with the phase command values of the third and fourth semiconductor elements X1 and Y1, and the gate signals of the third and fourth semiconductor elements X1 and Y1 are generated. To do. In the second comparator 12b, the primary side phase control triangular wave is compared with the phase command values of the first and second semiconductor elements U1 and V1, and the gate signals of the first and second semiconductor elements U1 and V1 are generated. In the second comparator 12c, the triangular wave for secondary side phase control is compared with the phase command values of the seventh and eighth semiconductor elements X2 and Y2, and the gate signals of the seventh and eighth semiconductor elements X2 and Y2 are generated. .. In the second comparator 12d, the triangular wave for secondary side phase control is compared with the phase command value of the fifth and sixth semiconductor elements U2 and V2, and the gate signal of the fifth and sixth semiconductor elements U2 and V2 is generated. .. As a result, it is possible to generate a gate signal having a required phase difference δ on the primary side and the secondary side and capable of outputting a desired output voltage value.

FIG. 9 shows the difference between the operation waveforms of the conventional method and the second embodiment. FIG. 9 shows the operation waveform on the primary side, and the operation waveform on the secondary side is omitted. U1, X1, V1, Y1 in FIG. 9 represent the conduction state (gate signal) of each semiconductor element. As shown in FIG. 9B, the second embodiment has a phase command value of the first and second semiconductor elements U1 and V1 and a phase command value of the third and fourth semiconductor elements X1 and Y1. The phase command values of the first and second semiconductor elements U1 and V1 and the phase command values of the third and fourth semiconductor elements X1 and Y1 are rectangular waves synchronized with the carrier frequency and have a phase difference.

As shown in FIG. 9B, by comparing the phase command values of the primary side phase control triangular wave and the first and second semiconductor elements U1 and V1, the conduction state of the first and second semiconductor elements U1 and V1 ( Gate signal) is controlled. Further, the conduction state (gate signal) of the third and fourth semiconductor elements X1 and Y1 is controlled by comparing the phase command values of the primary side phase control triangular wave and the third and fourth semiconductor elements X1 and Y1.

For example, when the phase command values of the first and second semiconductor elements U1 and V1 are larger than the primary side phase control triangular wave, the first semiconductor element U1 is turned OFF, the second semiconductor element V1 is turned ON, and the primary side phase is set. When the phase command values of the third and fourth semiconductor elements X1 and Y1 are larger than the control triangular wave, the third semiconductor element X1 is turned ON and the fourth semiconductor element Y1 is turned OFF.

Further, by controlling the amplitude of the phase command value of the first and second semiconductor elements U1 and V1 and the phase command value of the third and fourth semiconductor elements X1 and Y1, the gates of the first and second semiconductor elements U1 and V1 are controlled. The phase difference between the signal and the gate signal of the third and fourth semiconductor elements X1 and Y1 can be controlled. When the amplitude of the phase command value of the first and second semiconductor elements U1 and V1 and the phase command value of the third and fourth semiconductor elements X1 and Y1 is 0, the first and second semiconductor elements U1 and V1 and the third , The phase difference between the fourth semiconductor elements X1 and Y1 is 0 °.

In the case of the conventional method, since the phase difference between the gate signals of the first and second semiconductor elements U1 and V1 and the gate signals of the third and fourth semiconductor elements X1 and Y1 is 0 °, the voltage Va applied to the transformer Tr. Becomes a square wave.

On the other hand, in the second embodiment, the phase difference between the gate signals of the first and second semiconductor elements U1 and V1 and the gate signals of the third and fourth semiconductor elements X1 and Y1 is made larger than 0 °. , The voltage applied to the transformer Tr has a three-stage waveform. As a result, the effective value of the applied voltage can be reduced, so that the exciting current can be reduced.

Further, when the phase command value is 0, the output voltage of the rectangular wave is output, so that the output voltage corresponding to the DC voltage is output. On the other hand, when the phase command value is 0 or more, the output voltage can be lowered because the waveform has three stages including the period when the output voltage is 0. Since the flowing current is proportional to the output voltage value, the inrush current can be suppressed.

As shown above, according to the second embodiment, it is possible to safely charge the voltage of the capacitor while suppressing the inrush current without providing a current detection sensor or an overcurrent prevention circuit during precharging. ..

[Embodiment 3]
In the third embodiment, the inrush current generated during precharging is suppressed by increasing the frequency of the carrier signal. Since the inrush current has a characteristic that is inversely proportional to the carrier frequency, the inrush current can also be changed by changing the carrier frequency. As the control circuit, the one of the first embodiment or the second embodiment is applied.

FIG. 10 shows the control circuit according to the third embodiment. The circuit of FIG. 10 is characterized in that the selection circuit 13 is added to the circuit of FIG. The selection circuit 13 inputs a normal carrier signal and a carrier signal for precharging. Here, it is assumed that the carrier signal for precharging has a higher carrier frequency than the normal carrier signal.

The selection circuit 13 outputs a normal carrier signal during normal operation and outputs a precharge carrier signal during precharging. As a result, the carrier frequency becomes higher during precharging than during normal operation, and the inrush current can be suppressed.

Although the method of applying the third embodiment to the first embodiment has been described here, the third embodiment may be applied to the second embodiment.

As described above, according to the third embodiment, in addition to the effects of the first and second embodiments, it is possible to suppress the inrush current by setting the carrier frequency high at the time of precharging.

Although the above description has been made in detail only with respect to the specific examples described in the present invention, it is clear to those skilled in the art that various modifications and modifications can be made within the scope of the technical idea of the present invention. It goes without saying that such modifications and modifications fall within the scope of the claims.

U1, V1, X1, Y1, U2, V2, X2, Y2 ... 1st to 8th semiconductor elements L1, L2 ... 1st and 2nd reactors C1, C2 ... 1st and 2nd capacitors Tr ... Transformer 1 ... Phase command Value generator 2 ... Gate generator 3 ... Subtractor 4 ... PI control 5 ... Square wave generator 6a, 6b ... First multiplier 7a, 7b ... First comparator 8 ... Power control 9 ... Output voltage control 10a, 10b ... Triangular wave generator 11a to 11d ... Second multiplier 12a to 12d ... Second comparator 13 ... Selection circuit

Claims (6)

With the first capacitor
The first and second semiconductor elements connected in series between the positive and negative electrodes of the first capacitor,
The third and fourth semiconductor elements connected in series between the positive and negative electrodes of the first capacitor,
With the second capacitor
The fifth and sixth semiconductor elements connected in series between the positive and negative electrodes of the second capacitor, and
The seventh and eighth semiconductor elements connected in series between the positive and negative electrodes of the second capacitor,
The first reactor, one end of which is connected to the connection point of the third and fourth semiconductor elements,
A second reactor whose one end is connected to the connection points of the 7th and 8th semiconductor elements, and
The primary winding is connected between the other end of the first reactor and the connection point of the first and second semiconductor elements, and the connection point between the other end of the second reactor and the fifth and sixth semiconductor elements. A transformer with a secondary winding connected between and
It is an isolated DC / DC converter equipped with
An isolated DC / DC converter including a control circuit that controls voltage according to the deviation between the voltage of the first capacitor and the voltage of the second capacitor and generates a gate signal based on the result of the voltage control. .. The control circuit
A phase command value generator that performs voltage control according to the deviation between the first capacitor voltage and the second capacitor voltage and generates a primary side phase command value and a secondary side phase command value.
Based on the carrier signal, the primary side phase command value, and the secondary side phase command value, the gate signal of the first and second semiconductor elements, the gate signal of the third and fourth semiconductor elements, and the fifth , The gate signal of the 6th semiconductor element, the gate generator that generates the gate signal of the 7th and 8th semiconductor elements, and
The insulated DC / DC converter according to claim 1, wherein the isolated DC / DC converter is provided. The gate generator
A square wave generator that generates a first square wave synchronized with the carrier signal,
A first multiplier that outputs the second square wave on the primary side and the second square wave on the secondary side by multiplying the primary side phase command value and the secondary side phase command value by the first square wave, respectively.
By comparing the second square wave on the primary side with the carrier signal, the gate signal of the first and second semiconductor elements and the gate signal of the third and fourth semiconductor elements are generated, and the gate signal of the secondary side is generated. A first comparator that compares the second square wave with the carrier signal to generate the gate signal of the fifth and sixth semiconductor elements and the gate signal of the seventh and eighth semiconductor elements.
The insulated DC / DC converter according to claim 2, wherein the isolated DC / DC converter is provided. The control circuit
A power control unit that controls the output power by generating a third square wave on the primary side and a third square wave on the secondary side having a desired phase difference.
A phase command value is generated by voltage control according to the deviation between the first capacitor voltage and the second capacitor voltage, and the phase command value is set to the third square wave on the primary side, the third square wave on the secondary side, and the phase command value. Based on this, the gate signal of the first and second semiconductor elements, the gate signal of the third and fourth semiconductor elements, the gate signal of the fifth and sixth semiconductor elements, and the seventh and eighth semiconductor elements. Gate signal, and output voltage control unit to generate
The insulated DC / DC converter according to claim 1, wherein the isolated DC / DC converter is provided. The power control unit
A square wave generator that generates a first square wave synchronized with a carrier signal,
A first multiplier that multiplies the primary side phase command value and the secondary side phase command value by the first square wave to output the second square wave on the primary side and the second square wave on the secondary side, respectively.
The second square wave on the primary side is compared with the carrier signal to generate the third square wave on the primary side, and the second square wave on the secondary side is compared with the carrier signal to generate the secondary. A first comparator that generates a third square wave on the side, and
The output voltage control unit
A triangular wave generator that generates a primary side phase control triangular wave and a secondary side phase control triangular wave based on the primary side third square wave and the secondary side third rectangular wave.
A voltage control unit that generates a phase command value according to the deviation between the first capacitor voltage and the second capacitor voltage.
Based on the third rectangular wave on the primary side and the phase command value, the phase command value of the first and second semiconductor elements and the phase command value of the third and fourth semiconductor elements are output, and the third on the secondary side. A second multiplier that outputs the phase command value of the fifth and sixth semiconductor elements and the phase command value of the seventh and eighth semiconductor elements based on the rectangular wave and the phase command value.
The phase command value of the first and second semiconductor elements is compared with the triangular wave for primary side phase control to generate a gate signal of the first and second semiconductor elements, and the phase of the third and fourth semiconductor elements is generated. The command value is compared with the triangular wave for primary side phase control to generate a gate signal of the third and fourth semiconductor elements, and the phase command value of the fifth and sixth semiconductor elements and the secondary side phase control are used. The gate signal of the 5th and 6th semiconductor elements is generated by comparing with the triangular wave, and the phase command value of the 7th and 8th semiconductor elements is compared with the triangular wave for secondary side phase control. The isolated DC / DC converter according to claim 4, further comprising a second comparator that generates a gate signal of the eighth semiconductor element. The control circuit
The isolated DC / DC converter according to any one of claims 1 to 5, wherein the frequency of the carrier signal is set higher than that of the carrier signal during normal operation during precharging.

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