JP2738840B2 - Ceramic-metal composite substrate - Google Patents
Ceramic-metal composite substrateInfo
- Publication number
- JP2738840B2 JP2738840B2 JP63184033A JP18403388A JP2738840B2 JP 2738840 B2 JP2738840 B2 JP 2738840B2 JP 63184033 A JP63184033 A JP 63184033A JP 18403388 A JP18403388 A JP 18403388A JP 2738840 B2 JP2738840 B2 JP 2738840B2
- Authority
- JP
- Japan
- Prior art keywords
- copper
- semiconductor
- thickness
- ceramic
- molybdenum
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Ceramic Products (AREA)
- Die Bonding (AREA)
Description
【発明の詳細な説明】 [産業上の利用分野] この発明は、例えば半導体の実装に用いられるセラミ
ックと金属を接合することにより製造されるセラミック
−金属複合基板に関し、特に半導体やセラミックの破壊
を防止する基板構造に関するものである。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ceramic-metal composite substrate manufactured by bonding a ceramic and a metal used for mounting a semiconductor, for example, and more particularly to a semiconductor-ceramic composite substrate. It relates to a substrate structure to be prevented.
[従来の技術] 第5図は例えば特開昭60−155580号公報に示された従
来のセラミック絶縁基材と金属部材が直接接合された半
導体実装用の複合基板を示す断面図であり、図におい
て、(1)はセラミック絶縁基材のアルミナ部材、(2
A)、(2B)はアルミナ部材(1)に形成された金属部
材で、電気回路を形成するためなどの例えばタフピッチ
電解銅板、(7A)(7B)はアルミナ部材(1)と銅板
(2A)、(2B)を直接接合した接合面である。[Prior Art] FIG. 5 is a cross-sectional view showing a conventional composite board for mounting a semiconductor in which a ceramic insulating base and a metal member are directly joined, for example, as disclosed in Japanese Patent Application Laid-Open No. 60-155580. In (1), an alumina member of a ceramic insulating base material, (2)
A) and (2B) are metal members formed on the alumina member (1), for example, a tough pitch electrolytic copper plate for forming an electric circuit, and (7A) and (7B) are alumina members (1) and a copper plate (2A). , (2B) are directly joined.
第6図は従来の半導体実装用基板を用いた一実施態様
を示す斜視図であり、半導体を実装したモジュール構造
の一例を示す。図において、(4)は半導体、(5)は
半導体(4)を銅板(2b)に実装するためのはんだ、
(6a)(6b)はそれぞれ半導体(4)を動作させるため
に銅板(2b)とは電気的に絶縁された別の銅板(2a)
(2c)に接続した、例えばアルミニウム製のボンディン
グワイヤである。FIG. 6 is a perspective view showing an embodiment using a conventional semiconductor mounting substrate, and shows an example of a module structure on which a semiconductor is mounted. In the figure, (4) is a semiconductor, (5) is a solder for mounting the semiconductor (4) on the copper plate (2b),
(6a) (6b) is another copper plate (2a) electrically insulated from the copper plate (2b) to operate the semiconductor (4) respectively
This is a bonding wire made of, for example, aluminum connected to (2c).
上記のように構成されたモジュールの半導体、特に大
電力半導体を動作させると、半導体(4)は大量の熱を
発生する。また、当然のことながら上記モジュールは繰
り返し使用される。従って、半導体実装用基板としては
以下のことが要求される。半導体(4)から発生する熱
を十分逃がすことができること、半導体(4)の動作・
非動作に伴うヒートサイクルによって発生する基板の熱
膨張・収縮により半導体(4)を破壊しないこと、さら
に、このヒートサイクルによりアルミナ部材自体が破壊
しないことである。When the semiconductor of the module configured as described above, particularly a high-power semiconductor, is operated, the semiconductor (4) generates a large amount of heat. Of course, the above modules are used repeatedly. Therefore, the following is required for the semiconductor mounting substrate. The heat generated from the semiconductor (4) can be sufficiently released, and the operation of the semiconductor (4)
The semiconductor (4) should not be destroyed by the thermal expansion and contraction of the substrate caused by the heat cycle accompanying the non-operation, and the alumina member itself should not be destroyed by this heat cycle.
[発明が解決しようとする課題] しかるに、上記のような基板構造では、セラミック絶
縁基材(1)は一般的に熱膨張係数が小さく、上記実施
例のアルミナセラミックでは7×10-6であるため、熱膨
張係数が17×10-6の銅板(2A)(2B)と直接接合した場
合、熱膨張係数差により接合面(7A)(7B)の近傍に応
力を発生した。このような接合体がヒートサイクルを受
けると上記接合面(7A)(7B)近傍には大きな応力が繰
り返し発生し、硬いが脆いアルミナ部材(1)はその応
力に耐えられず割れが発生し、ついには分離してしまう
という問題点があった。第7図は断面図に典型的に割れ
形状を示す。(8A)(8B)(8C)(8D)が割れである。
このように割れ(8A)〜(8D)は応力が集中するセラミ
ック絶縁基材(1)と銅板(2A)(2B)の角部から発生
した。[Problems to be Solved by the Invention] However, in the above substrate structure, the ceramic insulating base material (1) generally has a small coefficient of thermal expansion, and is 7 × 10 −6 in the alumina ceramic of the above embodiment. Therefore, when directly joined to a copper plate (2A) (2B) having a thermal expansion coefficient of 17 × 10 −6 , stress was generated near the joint surfaces (7A) and (7B) due to the difference in thermal expansion coefficient. When such a bonded body is subjected to a heat cycle, large stress is repeatedly generated in the vicinity of the bonded surfaces (7A) and (7B), and the hard but brittle alumina member (1) cannot withstand the stress and cracks. At last there was a problem of separation. FIG. 7 typically shows a crack shape in a cross-sectional view. (8A) (8B) (8C) (8D) are cracks.
Thus, the cracks (8A) to (8D) occurred from the corners of the ceramic insulating substrate (1) and the copper plates (2A) (2B) where stress was concentrated.
また、銅板(2A)(2B)はアルミナ部(1)に強固に
接合されているため、その熱膨張係数は銅単体の場合に
比べ小さくなってはいるものの、熱膨張係数が5×10-6
と小さいシリコン半導体(4)を例えばはんだ付により
実装すると、半導体(4)にも割れが発生するという問
題点があった。これらの問題点は、半導体(4)の動作
電流を上げるために、銅板(2A)(2B)を厚くしたとき
や、大面積の半導体(4)を実装したときに顕著に現わ
れた。Further, since the copper plates (2A) and (2B) are firmly joined to the alumina part (1), their thermal expansion coefficients are smaller than those of copper alone, but the thermal expansion coefficients are 5 × 10 − 6
When the small silicon semiconductor (4) is mounted by, for example, soldering, there is a problem that the semiconductor (4) is also cracked. These problems became remarkable when the thickness of the copper plates (2A) and (2B) was increased in order to increase the operating current of the semiconductor (4) or when the semiconductor (4) having a large area was mounted.
上記割れの発生は、アルミナ部材(1)を厚くするこ
とにより若干の改善は図れるものの、半導体(4)から
の放熱特性は、アルミナ部材(1)の熱抵抗が高いため
劣化してしまう。例えば、0.4mmの板厚のアルミナ部材
(1)を0.63mmに増加させることにより−40℃〜150℃
の耐ヒートサイクル特性は1.2倍程度向上するが、逆に
熱の逃げを妨げる熱抵抗値は約1.6倍高くなり、半導体
(4)の機能やセラミック絶縁基材(1)のコスト等を
考慮した場合有効な方法ではない。Although the above cracks can be slightly improved by increasing the thickness of the alumina member (1), the heat radiation characteristics from the semiconductor (4) are deteriorated due to the high thermal resistance of the alumina member (1). For example, by increasing an alumina member (1) having a thickness of 0.4 mm to 0.63 mm, the temperature becomes -40 ° C to 150 ° C.
Although the heat cycle resistance of this material is improved by about 1.2 times, the thermal resistance value that prevents heat from escaping is about 1.6 times higher, and the functions of the semiconductor (4) and the cost of the ceramic insulating substrate (1) are taken into consideration. If not a valid way.
従って、これらの問題を避けるためには、半導体
(4)のパワーや形状を制限する、銅板(2A)、(2B)
を薄く、幅広くして実装密度を下げるなどの対策が必要
であり、モジュールの高機能化、高密度化にとって大き
な障害となっていた。Therefore, in order to avoid these problems, the copper plate (2A), (2B)
It is necessary to take measures such as reducing the mounting density by making it thinner and wider, and this has been a major obstacle to higher functionality and higher density of the module.
この発明は上記のような問題点を解消するためになさ
れたもので、過酷な使用環境下においても、例えば半導
体から発生する熱を逃がし、かつセラミック絶縁基材に
破壊が生じない信頼性の高いセラミック−金属複合基板
を得ることを目的とする。The present invention has been made in order to solve the above-described problems, and even under a severe use environment, for example, releases heat generated from a semiconductor, and has high reliability in which a ceramic insulating substrate is not broken. It is intended to obtain a ceramic-metal composite substrate.
[課題を解決するための手段] この発明のセラミック−金属複合基板は、セラミック
絶縁基材に銅または銅合金部材を接合して形成する半導
体実装用の複合基板において、モリブデン、タングステ
ン及びその合金のいずれかからなり、上記銅又は銅合金
部材の厚さの1/20〜1/3の厚さの拘束部材を上記銅また
は銅合金部材に接続して設けたものである。[Means for Solving the Problems] A ceramic-metal composite substrate of the present invention is a composite substrate for mounting a semiconductor formed by bonding a copper or copper alloy member to a ceramic insulating base material. A restraining member made of any one of them and having a thickness of 1/20 to 1/3 of the thickness of the copper or copper alloy member is provided so as to be connected to the copper or copper alloy member.
[作用] この発明においては、銅または銅合金部材の厚さの1/
20〜1/3の厚さの拘束部材を設けることにより、基板の
熱伝導や電気伝導特性を確保するとともに、セラミック
絶縁基材や例えば実装される半導体に加わる応力を低減
させ、セラミック絶縁基材や半導体が破壊するのを防止
する。[Action] In the present invention, 1 / th of the thickness of the copper or copper alloy member is used.
By providing a restraining member with a thickness of 20 to 1/3, the thermal conduction and electric conduction characteristics of the substrate are ensured, and the stress applied to the ceramic insulating substrate and the semiconductor to be mounted, for example, is reduced. And destruction of semiconductors.
[実施例] 以下、この発明の一実施例を図について説明する。第
1図はこの発明の一実施例のセラミック−金属複合基板
を示す断面図で、図において、(1)はセラミック絶縁
基材で、この場合は平板状のアルミナ部材、(2A)はア
ルミナ部材(1)の一面に直接接合された第1銅部材、
(2B)はアルミナ部材(1)の他面に直接接合された第
2銅部材で、(2C)は半導体の大容量化のために、アラ
ミナ部材(1)の一面側に追加した第3銅部材で、半導
体(図示せず)は上記従来基板と同様、この第3銅部材
(2C)上に実装される。(3)は拘束部材で、この場合
は第1、第3銅部材(2A)(2C)間に接合された、第
1、第3銅部材(2A)(2C)の総厚さの1/20〜1/3の厚
さのモリブデン部材である。Embodiment An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view showing a ceramic-metal composite substrate according to one embodiment of the present invention. In the figure, (1) is a ceramic insulating base material, in this case, a plate-like alumina member, and (2A) is an alumina member. (1) a first copper member directly joined to one surface,
(2B) is a second copper member directly bonded to the other surface of the alumina member (1), and (2C) is a third copper member added to one surface side of the alumina member (1) to increase the capacity of the semiconductor. As a member, a semiconductor (not shown) is mounted on the third copper member (2C) similarly to the conventional substrate. (3) is a restraining member. In this case, 1 / th of the total thickness of the first and third copper members (2A) and (2C) joined between the first and third copper members (2A) and (2C). It is a molybdenum member having a thickness of 20 to 1/3.
上記のように構成された基板が、温度環境の変化や半
導体の動作により、ヒートサイクルを受けると、従来基
板と同様熱膨張係数の差により、熱膨張係数の大きな銅
部材(2A)(2B)(2C)はアルミナ部材(1)よりも膨
張・収縮しようとする。しかし、この実施例では膨張係
数が低く、高強度で、熱抵抗が低く、かつ他の部材と一
体化できる部材である薄いモリブデン部材を(3)拘束
部材として追加した構造をとっている。モリブデンは熱
膨張係数が約5×10-6(/℃)であり、銅の約17×10-6
(/℃)との差は大きく、加熱冷却中には両者の接合界
面には大きな応力が発生するが、モリブデンの耐力、特
に薄い圧延材の耐力は50Kg/mm2以上もあるため、銅(耐
力約10Kg/mm2)の方がすぐに塑性変形し、モリブデンが
拘束部材(3)として働き、アルミナ部材(1)へ大き
な応力が加わるのを防止できる。なお、モリブデンと銅
の接合界面に加わる応力は従来例以上となるが、両者が
延在材料の金属材料であることから、割れは発生しな
い。When a substrate configured as described above undergoes a heat cycle due to a change in temperature environment or operation of a semiconductor, a copper member having a large coefficient of thermal expansion (2A) (2B) due to a difference in coefficient of thermal expansion like a conventional substrate (2C) tends to expand and contract more than the alumina member (1). However, this embodiment employs a structure in which a thin molybdenum member which is a member having a low expansion coefficient, high strength, low thermal resistance, and which can be integrated with other members is added as (3) a restraining member. Molybdenum has a coefficient of thermal expansion of about 5 × 10 −6 (/ ° C.) and about 17 × 10 −6 of copper.
(/ ° C), and a large stress is generated at the joint interface between the two during heating and cooling. However, since the yield strength of molybdenum, especially that of a thin rolled material is 50 kg / mm 2 or more, copper ( A proof stress of about 10 kg / mm 2 ) is immediately plastically deformed, and molybdenum acts as a restraining member (3) to prevent a large stress from being applied to the alumina member (1). Although the stress applied to the bonding interface between molybdenum and copper is higher than that of the conventional example, no cracking occurs because both are metal materials of the extending material.
モリブデン部材(3)を基板構成材料として強固に一
体化するためには、例えば、予めモリブデン部材(3)
と第1、第3銅部材(2A)(2C)を爆発圧接等の方法を
用いて接合した後、上記複合材料をアルミナ部材(1)
に特開昭60−155580号公報に示された例えばDBC法等を
用いて接合する方法がとられる。In order to firmly integrate the molybdenum member (3) as a substrate constituent material, for example, the molybdenum member (3)
After joining the first and third copper members (2A) and (2C) with a method such as explosion welding, the composite material is converted to an alumina member (1).
For example, a joining method using a DBC method or the like disclosed in Japanese Patent Application Laid-Open No. 60-155580 is adopted.
また、基板構造は従来例のようにセラミック絶縁基材
(1)を中心とする対称構造にしても、セラミック絶縁
基材(1)等の割れに対する効果は現われる。ところ
が、新たに拘束部材を設けることによる部品点数の増
加、材料コストの増加、及び熱抵抗の増加等の問題が生
じてくる。一方、半導体の大容量化に応じて体積を増加
させる必要があるのは、半導体側の銅部材である。半導
体側の銅部材の厚さとしてはトータルで0.3mm以上必要
とされ、5mm以下が適当で、0.3mm〜1mmの範囲が望まし
い。Further, even if the substrate structure is a symmetrical structure centering on the ceramic insulating base material (1) as in the conventional example, the effect on cracking of the ceramic insulating base material (1) and the like appears. However, problems such as an increase in the number of components, an increase in material cost, and an increase in thermal resistance due to the provision of a new restraint member arise. On the other hand, it is the copper member on the semiconductor side that needs to be increased in volume as the capacity of the semiconductor increases. The thickness of the copper member on the semiconductor side is required to be 0.3 mm or more in total, 5 mm or less is appropriate, and the range of 0.3 mm to 1 mm is desirable.
従って、この実施例では半導体を実装する側のみ第
1、第3銅部材(2A)(2C)及びモリブデン部材(3)
を積層した構造とし、反対側は第1図に示すように、第
2銅部材(2B)単体の構造としている。その結果、性能
がよく、かつ簡単で安価な構造となっている。なお、第
2銅部材(2B)は後工程の半田付けのため、また第2銅
部材(2B)がない場合、バランスをとるためモリブデン
部材(3)を少し厚めにしなければならないために設け
ている。厚さはアルミナ部材(1)の割れ発生防止のた
め0.3mm以下が適当で、モリブデン部材(3)の厚さ等
の兼ね合いで選定する必要がある。例えば、半導体側の
第1、第3銅部材(2A)、(2C)の厚さを0.3mm、モリ
ブデン部材(3)の厚さを0.1mmにした場合、反対側の
第2銅部材(2B)は0.1mmの厚さが適当である。このよ
うな構造の複合基板にすることにより、基板の加熱、冷
却中においても反りが生じない基板が得られる。以上の
ように、この実施例によれば、簡単な構造で、過酷な使
用環境下においても、半導体から発生する熱を逃がし、
アルミナ部材(1)などに破壊を生じさせない信頼性の
高い、大容量パワートランジスタモジュール用基板を適
用できるセラミック−金属複合基板が得られる。Therefore, in this embodiment, the first and third copper members (2A) and (2C) and the molybdenum member (3) only on the side on which the semiconductor is mounted.
Are laminated, and the other side is a structure of the second copper member (2B) alone, as shown in FIG. The result is a simple, inexpensive structure with good performance. The second copper member (2B) is provided for soldering in a later process, and when the second copper member (2B) is not provided, the molybdenum member (3) must be slightly thicker for balancing. I have. The thickness is suitably 0.3 mm or less to prevent cracking of the alumina member (1), and it is necessary to select the thickness in consideration of the thickness of the molybdenum member (3). For example, when the thickness of the first and third copper members (2A) and (2C) on the semiconductor side is 0.3 mm and the thickness of the molybdenum member (3) is 0.1 mm, the second copper member (2B) on the opposite side is formed. ) Is suitably 0.1 mm thick. By using a composite substrate having such a structure, a substrate that does not warp during heating and cooling of the substrate can be obtained. As described above, according to this embodiment, with a simple structure, even under a severe use environment, heat generated from a semiconductor is released,
A highly reliable ceramic-metal composite substrate that can be used as a large-capacity power transistor module substrate that does not cause damage to the alumina member (1) or the like can be obtained.
第2図は、この発明に係わるモリブデン部材(3)の
厚さと耐ヒートサイクル回数との関係の一例を示す特性
図である。横軸にモリブデン部材(3)の厚さを、縦軸
に耐ヒートサイクル回数(アルミナ部材(1)が割れる
までのヒートサイクルの回数)をとった。対称構造のセ
ラミック−金属複合基板のヒートサイクル試験の結果を
示すもので、モリブデン部材(3)が介在される2層か
らなる銅部材の総厚さは1.0mm、アルミナ部材(1)の
厚さは0.63mm、ヒートサイクルの条件は−40℃〜150℃
である。第2図からモリブデン部材(3)の厚さを0.05
mm以上にすることにより、耐ヒートサイクル特性が急激
に改善されていることがわかる。FIG. 2 is a characteristic diagram showing an example of the relationship between the thickness of the molybdenum member (3) according to the present invention and the number of heat cycles. The abscissa indicates the thickness of the molybdenum member (3), and the ordinate indicates the number of heat cycles (the number of heat cycles until the alumina member (1) cracks). This figure shows the results of a heat cycle test of a ceramic-metal composite substrate having a symmetrical structure. The total thickness of a copper member composed of two layers with a molybdenum member (3) interposed is 1.0 mm and the thickness of an alumina member (1) Is 0.63mm, heat cycle condition is -40 ℃ ~ 150 ℃
It is. From FIG. 2, the thickness of the molybdenum member (3) was set to 0.05.
It can be seen that the heat cycle resistance was sharply improved by setting the thickness to at least mm.
このように、モリブデン・銅間で発生する応力を銅の
変形により吸収させることにより、銅・アルミナ間の応
力を低下させ、銅部材の厚さの1/10程度の薄いモリブデ
ン部材(3)を追加するだけで、耐ヒートサイクル特性
を10倍以上向上できることが実証できた。この効果は、
銅部材の厚さが1.0mmの時のみに成立するものではない
ことはいうまでもない。Thus, by absorbing the stress generated between molybdenum and copper by the deformation of copper, the stress between copper and alumina is reduced, and the molybdenum member (3) having a thickness of about 1/10 of the thickness of the copper member can be reduced. It has been proved that the heat cycle resistance can be improved by more than 10 times only by adding. This effect
Needless to say, this is not true only when the thickness of the copper member is 1.0 mm.
モリブデン部材(3)の厚さとしては、銅部材のトー
タルの厚さの1/20〜1/3が適当であり、この範囲内でモ
リブデン厚さを変化させることにより、耐ヒートサイク
ル特性、熱抵抗、基板コストを変化させることができ
る。1/20以下の厚さのモリブデン部材(3)では、耐ヒ
ートサイクル特性の改善が十分図れず、1/3以上の厚さ
のモリブデン部材(3)では熱抵抗が高くなる結果、半
導体からの熱放散が不十分となるので、高機能化にとっ
て不都合であり、また基板のコストも高くなるため工業
的利用価値が低下する。また、反対側に配置する第2銅
部材(2B)の厚さは0.3mm以上では反りが発生するので
問題である。The thickness of the molybdenum member (3) is suitably 1/20 to 1/3 of the total thickness of the copper member. By changing the molybdenum thickness within this range, the heat cycle resistance and heat Resistance and substrate cost can be changed. With a molybdenum member (3) having a thickness of 1/20 or less, the heat cycle resistance cannot be sufficiently improved, and with a molybdenum member (3) having a thickness of 1/3 or more, the thermal resistance becomes high. Insufficient heat dissipation is inconvenient for higher functionality, and the cost of the substrate is higher, which lowers its industrial value. Further, if the thickness of the second copper member (2B) disposed on the opposite side is 0.3 mm or more, warpage occurs, which is a problem.
なお、セラミックと鋼を接合した構造材において、熱
膨張差により内部応力を緩和させる方法として、、両者
の接合面の間に、例えばアルミニウム、銅などの比較的
柔らかい金属層、ニオブ、あるいはニオブ/モリブデ
ン、ニオブ/タングステンの積層中間層を数mm設ける方
法が提案されている。(雑誌:金属1986年5月号45〜50
頁)ところが、半導体実装用の基板としては上述したよ
うに、数mmもの中間層を設けることは熱放散性が非常に
悪くなり、大容量、高機能化できないために問題であ
る。As a method of relieving internal stress due to a difference in thermal expansion in a structural material in which ceramic and steel are joined, a relatively soft metal layer such as aluminum or copper, niobium, or niobium / niobium may be provided between both joining surfaces. A method of providing a laminated intermediate layer of molybdenum and niobium / tungsten by several mm has been proposed. (Magazine: Metal, May 1986, 45-50
However, as described above, providing an intermediate layer of several mm as a substrate for mounting a semiconductor is a problem because heat dissipation becomes extremely poor, and a large capacity and high functionality cannot be achieved.
なお、上記実施例ではモリブデン部材(3)を同一厚
さの第1、第2銅部材(2A)(2C)の間に設けている
が、第1、第2銅部材(2A)(2C)の厚さが異なってい
ても同様の効果を期待できる。また第1、第2銅部材
(2A)(2C)を一体化して、モリブデン部材(3)を単
一の銅部材の表面あるいは銅部材とアルミナ部材の間に
配置しても同様の効果を期待できる。Although the molybdenum member (3) is provided between the first and second copper members (2A) and (2C) having the same thickness in the above embodiment, the first and second copper members (2A) and (2C) are provided. The same effect can be expected even if the thicknesses are different. Similar effects can be expected by integrating the first and second copper members (2A) and (2C) and disposing the molybdenum member (3) on the surface of a single copper member or between the copper member and the alumina member. it can.
第3図はモリブデン部材(3)を第4の銅部材(2D)
の表面に配置した場合のこの発明の他の実施例を示す断
面図である。この実施例においては、熱膨張係数の小さ
いモリブデン部材(3)が表面にあるため、この上に実
装する半導体(図示せず)との熱膨張のマッチングがよ
り良好となる。Fig. 3 shows a molybdenum member (3) replaced with a fourth copper member (2D)
FIG. 11 is a cross-sectional view showing another embodiment of the present invention when arranged on the surface of the present invention. In this embodiment, since the molybdenum member (3) having a small thermal expansion coefficient is on the surface, the thermal expansion matching with the semiconductor (not shown) mounted thereon becomes better.
第4図はモリブデン部材(3)を第4の銅部材(2D)
とアルミナ部材(1)の間に配置した場合のこの発明の
さらに他の実施例を示す断面図である。この実施例にお
いては、モリブデン部材(3)がアルミナ部材(1)と
接しているため、アルミナ部材(1)の割れがより防止
できるようになる。Fig. 4 shows the molybdenum member (3) being replaced with a fourth copper member (2D)
FIG. 10 is a cross-sectional view showing still another embodiment of the present invention in which the present invention is disposed between a member and an alumina member (1). In this embodiment, since the molybdenum member (3) is in contact with the alumina member (1), cracking of the alumina member (1) can be further prevented.
また、モリブデン部材は一層である必要はなく、要は
その総厚さが銅部材の1/20〜1/3となるように、半導体
の特性、セラミック絶縁基材の特性に応じて配置すれば
よい。In addition, the molybdenum member does not need to be a single layer, in other words, if the total thickness is 1/20 to 1/3 of the copper member, if it is arranged according to the characteristics of the semiconductor and the characteristics of the ceramic insulating base material. Good.
さらに、セラミック−金属複合基板の接合方法は、上
述したように、例えば爆発圧接、DBC法等の従来の方法
が利用できるが、この発明における基板はそれぞれが強
固に接合され、拘束しあうことが必要であるため、融点
が低く、柔らかい、例えば共晶はんだのような軟ろうに
よる接合方法は避けた方がよい。Further, as described above, for the joining method of the ceramic-metal composite substrate, conventional methods such as explosive pressure welding and DBC method can be used. However, the substrates in the present invention may be firmly joined and restrained. Since it is necessary, it is better to avoid a joining method using a soft solder having a low melting point and a soft solder such as eutectic solder.
さらにまた、上記実事例では、セラミック絶縁基材
(1)としてアルミナ部材、拘束部材(3)としてモリ
ブデン部材を利用する場合について述べたが、アルミナ
部材の代わりに窒化アルミニウム部材やシリコンカーバ
イト部材などの熱膨張係数が小さく、かつ脆性な絶縁基
板材料においても、銅部材の1/20〜1/3の範囲内の薄い
拘束部材で同様の効果が期待できる。また、モリブデン
部材の代わりに、ほぼ同程度の熱膨張係数、耐力、熱伝
導率を有するタングステン部材を利用することもでき
る。また、セラミック部材、銅部材、拘束部材はそれぞ
れ100%同一の材料から作られている必要もなく、特に
銅部材、拘束部材は熱膨張係数、電気伝導度、耐力など
の物性値が大幅に変化しない限り上記成分を主成分とす
る合成物質、例えば銅合金、モリブデン合金、タングス
テン合金であってもよい。Furthermore, in the above-mentioned actual example, the case where an alumina member is used as the ceramic insulating base material (1) and a molybdenum member is used as the restraining member (3) has been described. A similar effect can be expected with a thin restraining member in the range of 1/20 to 1/3 of the copper member even in a brittle insulating substrate material having a small coefficient of thermal expansion. Further, instead of the molybdenum member, a tungsten member having substantially the same coefficient of thermal expansion, proof stress, and thermal conductivity can be used. In addition, the ceramic member, copper member, and restraint member do not need to be made of the same material, and the copper member and restraint member, in particular, have significant changes in physical properties such as thermal expansion coefficient, electrical conductivity, and proof stress. Unless otherwise, a synthetic substance containing the above components as a main component, for example, a copper alloy, a molybdenum alloy, or a tungsten alloy may be used.
[発明の効果] 以上のように、この発明によれば、セラミック絶縁基
材に銅または銅合金部材を接合して形成する半導体実装
用の複合基板において、モリブデン、タングステン及び
その合金のいずれかからなり、上記銅又は銅合金部材の
厚さの1/20〜1/3の厚さの拘束部材を上記銅または銅合
金部材に接続して設けたことにより、脆性材料であるセ
ラミック絶縁基材に発生する熱応力を低下させ、過酷な
使用環境下においてもセラミック絶縁基材や実装される
半導体の破壊を防止できるセラミック−金属複合基板が
得られる効果がある。[Effects of the Invention] As described above, according to the present invention, in a composite substrate for semiconductor mounting formed by joining a copper or copper alloy member to a ceramic insulating base material, a composite substrate for molybdenum, tungsten, or an alloy thereof is used. By providing a restraining member having a thickness of 1/20 to 1/3 of the thickness of the copper or copper alloy member connected to the copper or copper alloy member, the ceramic insulating base material which is a brittle material is provided. This has the effect of lowering the generated thermal stress and obtaining a ceramic-metal composite substrate capable of preventing the destruction of the ceramic insulating base material and the mounted semiconductor even under a severe use environment.
第1図はこの発明の一実施例のセラミック−金属複合基
板を示す断面図、第2図はこの発明に係わる基板の耐ヒ
ートサイクルと拘束部材の厚さとの関係の一例を示す特
性図、第3図はこの発明の他の実施例を示す断面図、第
4図はこの発明のさらに他の実施例を示す断面図、第5
図は従来のセラミック−金属複合基板を示す断面図、第
6図は一般的なセラミック−金属複合基板の一実施態様
を示す斜視図、第7図は従来のセラミック−金属複合基
板に発生した割れを示す断面図である。 図において、(1)はセラミック絶縁基材、(2A)、
(2C)(2D)は銅または銅合金部材、(3)は拘束部材
である。 なお、図中、同一符号は同一または相当部分を示す。FIG. 1 is a sectional view showing a ceramic-metal composite substrate according to one embodiment of the present invention, FIG. 2 is a characteristic diagram showing an example of a relationship between a heat cycle of the substrate according to the present invention and a thickness of a restraining member, FIG. 3 is a sectional view showing another embodiment of the present invention, FIG. 4 is a sectional view showing still another embodiment of the present invention, and FIG.
FIG. 6 is a sectional view showing a conventional ceramic-metal composite substrate, FIG. 6 is a perspective view showing one embodiment of a general ceramic-metal composite substrate, and FIG. 7 is a crack generated in the conventional ceramic-metal composite substrate. FIG. In the figure, (1) is a ceramic insulating substrate, (2A),
(2C) and (2D) are copper or copper alloy members, and (3) is a restraining member. In the drawings, the same reference numerals indicate the same or corresponding parts.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭62−72575(JP,A) 特開 昭63−179733(JP,A) 特開 昭63−206365(JP,A) 特開 昭60−177634(JP,A) 特開 昭63−42152(JP,A) 実開 昭59−2150(JP,U) ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-62-72575 (JP, A) JP-A-63-179733 (JP, A) JP-A-63-206365 (JP, A) JP-A-60-1985 177634 (JP, A) JP-A-63-42152 (JP, A) JP-A-59-2150 (JP, U)
Claims (1)
を接合して形成する半導体実装用の複合基板において、
モリブデン、タングステン及びその合金のいずれかから
なり、上記銅又は銅合金部材の厚さの1/20〜1/3の厚さ
の拘束部材を上記銅または銅合金部材に接続して設けた
ことを特徴とするセラミック−金属複合基板。1. A composite substrate for mounting a semiconductor formed by joining a copper or copper alloy member to a ceramic insulating base material,
Molybdenum, made of any of tungsten and its alloys, that a restraining member having a thickness of 1/20 to 1/3 of the thickness of the copper or copper alloy member is provided connected to the copper or copper alloy member. Characteristic ceramic-metal composite substrate.
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63184033A JP2738840B2 (en) | 1988-07-22 | 1988-07-22 | Ceramic-metal composite substrate |
KR1019890010225A KR920007021B1 (en) | 1988-07-22 | 1989-07-19 | Ceramic-metal composite |
DE3924225A DE3924225C2 (en) | 1988-07-22 | 1989-07-21 | Method for producing a ceramic-metal composite substrate and ceramic-metal composite substrate |
DE3943683A DE3943683C2 (en) | 1988-07-22 | 1989-07-21 | Ceramic metal composite substrate |
US07/675,063 US5153077A (en) | 1988-07-22 | 1991-03-26 | Ceramic-metal composite substrate |
US07/789,074 US5251803A (en) | 1988-07-22 | 1991-11-07 | Ceramic-metal composite substrate and method for producing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63184033A JP2738840B2 (en) | 1988-07-22 | 1988-07-22 | Ceramic-metal composite substrate |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0234577A JPH0234577A (en) | 1990-02-05 |
JP2738840B2 true JP2738840B2 (en) | 1998-04-08 |
Family
ID=16146185
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63184033A Expired - Lifetime JP2738840B2 (en) | 1988-07-22 | 1988-07-22 | Ceramic-metal composite substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2738840B2 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH078142A (en) * | 1993-06-21 | 1995-01-13 | Haruo Hasegawa | Fish catching tool |
AUPQ605800A0 (en) | 2000-03-06 | 2000-03-30 | Silverbrook Research Pty Ltd | Printehead assembly |
JP4180980B2 (en) | 2003-06-10 | 2008-11-12 | 本田技研工業株式会社 | Semiconductor device |
JP2012253125A (en) * | 2011-06-01 | 2012-12-20 | Sumitomo Electric Ind Ltd | Semiconductor device and wiring board |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6272575A (en) * | 1985-09-26 | 1987-04-03 | 株式会社東芝 | Manufacture of ceramic-metal bonded body |
JPH07115440B2 (en) * | 1987-01-21 | 1995-12-13 | 住友大阪セメント株式会社 | Ceramic-metal bonded structure and method for manufacturing the same |
JPS63206365A (en) * | 1987-02-23 | 1988-08-25 | 京セラ株式会社 | Joined body of ceramic and metal |
-
1988
- 1988-07-22 JP JP63184033A patent/JP2738840B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH0234577A (en) | 1990-02-05 |
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