JP2737599B2 - Electroless plating method on copper circuit pattern of printed wiring board - Google Patents
Electroless plating method on copper circuit pattern of printed wiring boardInfo
- Publication number
- JP2737599B2 JP2737599B2 JP5123580A JP12358093A JP2737599B2 JP 2737599 B2 JP2737599 B2 JP 2737599B2 JP 5123580 A JP5123580 A JP 5123580A JP 12358093 A JP12358093 A JP 12358093A JP 2737599 B2 JP2737599 B2 JP 2737599B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit pattern
- tin
- copper circuit
- copper
- electroless plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Chemically Coating (AREA)
- Manufacturing Of Printed Wiring (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、プリント配線板の錫又
は錫合金剥離法による銅回路パターンに無電解めっき法
によりニッケル、パラジウム、ニッケル・パラジウム合
金等のめっき皮膜を形成する場合に、銅回路が形成され
ていない非導電性基板部分へのめっき皮膜の析出を確実
に防止して、基板の銅回路パターン上のみに無電解めっ
き皮膜を形成することができるプリント配線板の銅回路
パターン上への無電解めっき方法に関する。BACKGROUND OF THE INVENTION The present invention relates to a method for forming a plating film of nickel, palladium, nickel-palladium alloy or the like on a copper circuit pattern of a printed wiring board by a tin or tin alloy peeling method by an electroless plating method. On the copper circuit pattern of the printed wiring board, which can reliably prevent the plating film from depositing on the non-conductive substrate part where the circuit is not formed, and can form the electroless plating film only on the copper circuit pattern of the substrate The present invention relates to a method for electroless plating.
【０００２】[0002]
【従来の技術】従来、プリント配線板の製造法として、
基板上に銅箔を積層した銅張積層板の銅箔上に錫又は錫
合金皮膜をエッチングレジストとして回路パターン状に
形成し、この錫又は錫合金めっき皮膜形成部分を残して
銅をエッチング除去することにより基板上に回路パター
ンを形成した後、該回路パターン上の錫又は錫合金皮膜
を溶解除去し、次いでこのように形成されたプリント配
線板の銅回路パターン上に耐熱性に優れるニッケル、パ
ラジウム又はニッケル・パラジウム合金皮膜を無電解め
っき法により形成すること、更に場合によっては、この
無電解ニッケル、パラジウム又はこれらの合金めっき皮
膜の上に無電解金めっき皮膜を形成する方法が知られて
いる。2. Description of the Related Art Conventionally, as a method for manufacturing a printed wiring board,
A tin or tin alloy film is formed on a copper foil of a copper-clad laminate obtained by laminating a copper foil on a substrate in a circuit pattern as an etching resist, and copper is removed by etching while leaving the tin or tin alloy plating film forming portion. After forming a circuit pattern on the substrate by dissolving and removing the tin or tin alloy film on the circuit pattern, nickel and palladium having excellent heat resistance are then formed on the copper circuit pattern of the printed wiring board thus formed. Or, a method of forming a nickel-palladium alloy film by an electroless plating method, and in some cases, a method of forming an electroless gold plating film on this electroless nickel, palladium or an alloy plating film thereof is known. .
【０００３】この場合、錫皮膜や錫合金皮膜を除去した
銅回路パターン上に無電解ニッケルめっきを施す場合、
通常無電解ニッケルめっきを行う前に銅回路パターン上
にパラジウム触媒核を形成するアクチベータ処理を施す
ことが行われ、この場合このアクチベータ処理は、塩化
パラジウムの塩酸酸性水溶液にプリント配線板を浸漬す
ることにより行われる。In this case, when performing electroless nickel plating on a copper circuit pattern from which a tin film or a tin alloy film has been removed,
Usually, before performing electroless nickel plating, an activator process for forming a palladium catalyst nucleus on a copper circuit pattern is performed, in which case the activator process is to immerse the printed wiring board in a hydrochloric acid aqueous solution of palladium chloride. It is performed by
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、上記の
ように銅回路パターンの形成工程で錫又は錫合金をエッ
チングレジストとして使用し、不要銅層をエッチングに
より除去した後、錫又は錫合金を剥離する方法で作製さ
れたプリント配線板に対し上記アクチベータ処理を行
い、次いで無電解ニッケルめっきを施した際、基板の銅
回路パターン以外の不部にもめっき皮膜が析出してしま
うという不都合がしばしば発生する場合がある。However, as described above, tin or a tin alloy is used as an etching resist in the step of forming a copper circuit pattern, an unnecessary copper layer is removed by etching, and then the tin or tin alloy is peeled off. When the above-described activator treatment is performed on the printed wiring board manufactured by the method and then subjected to electroless nickel plating, a problem often occurs in that a plating film is deposited also on a portion other than the copper circuit pattern of the substrate. There are cases.
【０００５】本発明は、上記事情に鑑みなされたもの
で、錫又は錫合金皮膜をエッチングレジストとして回路
パターンの形成を行ったプリント配線板の銅回路パター
ン上に、回路パターン以外の非導電性基板上へめっき皮
膜が析出することを確実に防止して、銅回路パターン上
のみにめっき皮膜を形成することができるプリント配線
板の銅回路パターン上への無電解めっき方法を提供する
ことを目的とする。The present invention has been made in view of the above circumstances, and a non-conductive substrate other than a circuit pattern is formed on a copper circuit pattern of a printed wiring board on which a circuit pattern is formed using a tin or tin alloy film as an etching resist. An object of the present invention is to provide a method for electroless plating on a copper circuit pattern of a printed wiring board, which can surely prevent a plating film from depositing on a copper circuit pattern and can form a plating film only on a copper circuit pattern. I do.
【０００６】[0006]
【課題を解決するための手段】本発明者は、上記目的を
達成するため鋭意検討を行った結果、回路パターン以外
の非導電性基板上へめっき皮膜が析出する異常析出の発
生は、銅回路パターン上からエッチングレジストの錫又
は錫合金皮膜を剥離する際、剥離液中に溶解した錫がＳ
ｎ4+として銅回路パターン以外の基板上に吸着し、塩化
パラジウム−塩酸溶液によるアクチベータ処理時にこの
Ｓｎ4+にパラジウムイオンが吸着され、無電解めっき中
にこのパラジウムが金属に還元され、このパラジウム金
属を核にして無電解めっき反応が進行してめっき皮膜が
析出することにより生じるものであることを知見した。
そこで、この点を解決するため更に検討を行った結果、
アクチベータ処理に硫酸パラジウムの硫酸酸性水溶液を
使用することにより、意外にも塩化パラジウムの塩酸酸
性水溶液を用いる場合に比べ、上記異常析出を顕著に減
少させることができることを知見した。しかし、それで
もなお異常析出が生じる場合があり、このため更に検討
を重ねた結果、上記硫酸パラジウムの硫酸酸性溶液でア
クチベータ処理した後、酸洗浄を行うことにより、無電
解めっき処理時に銅回路パターン以外の非導電性基板部
分への異常析出を確実に防止して、銅回路パターン上の
みに確実にめっき皮膜を形成することができることを見
出し、本発明を完成したものである。Means for Solving the Problems As a result of extensive studies to achieve the above object, the present inventor has found that the occurrence of abnormal deposition in which a plating film is deposited on a non-conductive substrate other than a circuit pattern is caused by a copper circuit. When the tin or tin alloy film of the etching resist is stripped from the pattern, tin dissolved in the stripping solution is
Adsorbed on the substrate other than the copper circuit pattern as n 4+ , palladium ions were adsorbed on this Sn 4+ during the activator treatment with palladium chloride-hydrochloric acid solution, and this palladium was reduced to metal during electroless plating, It has been found that the electroless plating reaction proceeds with the metal as a nucleus and the plating film is deposited to cause the electroless plating reaction.
Therefore, as a result of further study to solve this point,
By using a sulfuric acid acidic aqueous solution of palladium sulfate for the activator treatment, it was surprisingly found that the abnormal precipitation can be significantly reduced as compared with the case of using a palladium chloride acidic aqueous solution. However, abnormal precipitation may still occur.Therefore, as a result of further study, after performing the activator treatment with the above-mentioned sulfuric acid acidic solution of palladium sulfate, acid cleaning is performed, so that other than the copper circuit pattern during the electroless plating treatment. It has been found that abnormal deposition on a non-conductive substrate portion can be reliably prevented and a plating film can be reliably formed only on a copper circuit pattern, and the present invention has been completed.
【０００７】従って、本発明は、非導電性基板の銅層上
に錫又は錫合金皮膜をエッチングレジストとして回路パ
ターン状に形成し、該錫又は錫合金めっき皮膜形成部分
を残して銅層をエッチング除去し、基板上に回路パター
ンを形成した後、該回路パターン表面の錫又は錫合金皮
膜を溶解除去することにより得られた銅回路パターン上
に無電解めっきを施す際、上記銅回路パターンを有する
基板を硫酸パラジウムの硫酸酸性水溶液に浸漬して銅回
路パターン上にパラジウムを触媒核として置換析出さ
せ、次いで該基板を酸洗浄した後、無電解めっきを施す
ことを特徴とするプリント配線板の銅回路パターン上へ
の無電解めっき方法を提供する。Accordingly, the present invention provides a method for forming a tin or tin alloy film as an etching resist on a copper layer of a non-conductive substrate in the form of a circuit pattern, and etching the copper layer while leaving the tin or tin alloy plating film formed portion. After removing and forming a circuit pattern on the substrate, when performing electroless plating on the copper circuit pattern obtained by dissolving and removing the tin or tin alloy film on the surface of the circuit pattern, it has the copper circuit pattern The substrate is immersed in an aqueous sulfuric acid solution of palladium sulfate to precipitate and displace the palladium as a catalyst nucleus on the copper circuit pattern. Provided is a method for electroless plating on a circuit pattern.
【０００８】以下、本発明につき更に詳しく説明する。
本発明の無電解めっき方法は、上述のように、銅層を剥
離する際のエッチングレジストとして錫又は錫合金皮膜
を用い、次いで錫又は錫合金皮膜を除去して銅回路パタ
ーンを形成したプリント配線板の該銅回路パターン上に
ニッケル、パラジウム又はニッケル・パラジウム合金め
っき皮膜を無電解めっき法により形成する際に、硫酸パ
ラジウムの硫酸酸性水溶液を用いてアクチベータ処理
し、次いで酸洗浄を施した後、無電解めっきを行うもの
である。Hereinafter, the present invention will be described in more detail.
As described above, the electroless plating method of the present invention uses a tin or tin alloy film as an etching resist when stripping a copper layer, and then removes the tin or tin alloy film to form a printed circuit formed with a copper circuit pattern. When forming a nickel, palladium or nickel-palladium alloy plating film on the copper circuit pattern of the board by an electroless plating method, after performing an activator treatment using a sulfuric acid aqueous solution of palladium sulfate, and then performing acid cleaning, This is for performing electroless plating.
【０００９】ここで、上記プリント配線板は、エッチン
グレジストとして錫又は錫合金皮膜を用いて銅回路パタ
ーンを形成したものであればよく、樹脂基板、セラミッ
ク基板、ガラス繊維基板、金属板に樹脂等の絶縁材を積
層した金属芯基板等に銅回路パターンを形成したものな
ど、いずれのものも使用することができる。Here, the printed wiring board may be one having a copper circuit pattern formed by using a tin or tin alloy film as an etching resist, and may be a resin substrate, a ceramic substrate, a glass fiber substrate, a metal plate, a resin or the like. Any of the above can be used, such as a metal core substrate or the like on which a copper circuit pattern is formed.
【００１０】本発明の無電解めっき方法は、まずこのよ
うなプリント配線板に硫酸パラジウムの硫酸酸性水溶液
を用いてアクチベータ処理を施し、銅回路パターン上に
パラジウムを触媒核として置換析出させるが、この場合
アクチベータ処理に先立ち、通常の前処理を行うことが
できる。前処理として具体的には、クリーナーで洗浄
し、水洗し、硫酸等を用いて酸洗し、水洗し、過硫酸ナ
トリウムや過硫酸アンモニウム等の過硫酸塩類でソフト
エッチングし、水洗し、硫酸にプレデップするなどの処
理を行うことができる。In the electroless plating method of the present invention, such a printed wiring board is first subjected to an activator treatment using an aqueous solution of palladium sulfate in a sulfuric acid solution to precipitate and replace palladium as a catalyst nucleus on a copper circuit pattern. In this case, normal pre-processing can be performed prior to the activator processing. Specifically, as a pretreatment, it is washed with a cleaner, washed with water, pickled with sulfuric acid or the like, washed with water, soft-etched with a persulfate such as sodium persulfate or ammonium persulfate, washed with water, and pre-dipped in sulfuric acid. And the like.
【００１１】上記アクチベータ処理は、上記のようにア
クチベータとして硫酸パラジウムの硫酸酸性水溶液を用
いて行われ、この場合硫酸パラジウムの硫酸酸性水溶液
としては、硫酸パラジウム０．００１〜０．１ｇ／Ｌ、
硫酸１〜１００ｇ／Ｌ、ｐＨ０．６以下のものが好適に
使用される。また、処理条件も通常の条件とすることが
でき、具体的には浴温２５〜５０℃で、０．１〜５分程
度プリント配線板を浸漬することにより行うことができ
る。The activator treatment is carried out using an aqueous solution of palladium sulfate in sulfuric acid as an activator as described above. In this case, the aqueous solution of palladium sulfate in sulfuric acid is 0.001-0.1 g / L of palladium sulfate.
Sulfuric acid having a pH of 1 to 100 g / L and a pH of 0.6 or less is preferably used. In addition, the processing conditions can be set to normal conditions. Specifically, the processing can be performed by immersing the printed wiring board at a bath temperature of 25 to 50 ° C. for about 0.1 to 5 minutes.
【００１２】次いで、水洗した後に酸洗浄を行い、プリ
ント配線板の銅回路パターン以外の基板表面に存在する
パラジウムイオンを除去する。この場合、酸洗浄に用い
る酸としては、硫酸、塩酸、メタンスルホン酸，エタン
スルホン酸等のスルホン酸などが好適に用いられる。こ
れらの中では塩酸を用いることが特に好ましく、これに
より一層確実に基板上のパラジウムイオンを除去するこ
とができるが、その他の酸であっても十分な効果が得ら
れる。なお、これらの酸は通常適宜濃度に希釈して用い
られ、具体的には酸濃度１〜１０重量％として用いられ
る。また、処理条件は浴温１５〜４０℃で、０．１〜５
分程度プリント配線板を浸漬することにより行うことが
できる。Next, after washing with water, acid washing is performed to remove palladium ions present on the substrate surface other than the copper circuit pattern of the printed wiring board. In this case, as the acid used for the acid cleaning, sulfuric acid, hydrochloric acid, sulfonic acid such as methanesulfonic acid, ethanesulfonic acid and the like are preferably used. Among these, it is particularly preferable to use hydrochloric acid, whereby palladium ions on the substrate can be more reliably removed, but a sufficient effect can be obtained with other acids. These acids are usually used after being appropriately diluted to a specific concentration, and specifically, used at an acid concentration of 1 to 10% by weight. The processing conditions are a bath temperature of 15 to 40 ° C. and 0.1 to 5
It can be performed by immersing the printed wiring board for about a minute.
【００１３】上記酸洗浄後、無電解めっきを行うが、こ
の場合無電解めっきとしては、通常無電解ニッケル、パ
ラジウム、ニッケル・パラジウム合金めっきが行われ、
めっき浴の組成、条件等は、公知のものとすることがで
きる。After the acid cleaning, electroless plating is performed. In this case, electroless plating is usually performed by electroless nickel, palladium, nickel-palladium alloy plating,
The composition and conditions of the plating bath can be known.
【００１４】この場合、上記酸洗浄処理によりプリント
配線板の銅回路パターン以外の基板表面に吸着していた
パラジウムイオンが完全に除去され、銅回路パターン上
にのみ触媒核となるパラジウムが存在しているので、銅
回路パターン以外の基板表面にめっき皮膜が析出する異
常析出を生じることが確実に防止され、銅回路パターン
のみに選択的に無電解めっき皮膜が析出する。In this case, the palladium ions adsorbed on the substrate surface other than the copper circuit pattern of the printed wiring board are completely removed by the above-mentioned acid cleaning treatment, and palladium serving as a catalyst nucleus exists only on the copper circuit pattern. Therefore, abnormal deposition of a plating film on the substrate surface other than the copper circuit pattern is reliably prevented, and the electroless plating film is selectively deposited only on the copper circuit pattern.
【００１５】[0015]
【実施例】以下、実施例、比較例を示して本発明を具体
的に説明するが、本発明は下記実施例に制限されるもの
ではない。 ［実施例，比較例］樹脂基板上に銅箔を積層した銅張積
層板の銅箔上に錫又は錫合金皮膜をエッチングレジスト
として回路パターン状に形成し、該錫又は錫合金めっき
皮膜形成部分を残して銅をエッチング除去することによ
り基板上に回路パターンを形成した後、該回路パターン
上の錫又は錫合金皮膜を溶解除去したプリント配線板を
使用し、これを硫酸錫溶液（硫酸１００ｇ／Ｌ、硫酸錫
１００ｇ／Ｌ）中に室温で２４時間浸漬し、水洗、乾燥
した後、７日間空気中に放置し、基板表面に付着した２
価の錫イオンを４価に酸化した。EXAMPLES The present invention will now be described specifically with reference to examples and comparative examples, but the present invention is not limited to the following examples. [Examples and Comparative Examples] A tin or tin alloy plating film is formed on a copper foil of a copper-clad laminate obtained by laminating a copper foil on a resin substrate in the form of a circuit pattern using an etching resist as a tin or tin alloy plating film. After forming a circuit pattern on the substrate by etching away copper while leaving a layer, a printed wiring board in which the tin or tin alloy film on the circuit pattern is dissolved and removed is used, and this is used as a tin sulfate solution (100 g / sulfuric acid). L, 100 g / L of tin sulfate) at room temperature for 24 hours, washed with water, dried, left in the air for 7 days, and adhered to the substrate surface.
The divalent tin ion was oxidized to tetravalent.
【００１６】次いで、このようにして得られた６つのプ
リント配線基板に、それぞれ表１に示した工程により無
電解ニッケルめっきを行い、銅回路パターン上に無電解
ニッケルめっき皮膜を形成した。めっき処理後、銅回路
パターン以外の基板上にニッケル皮膜の析出があるか否
かを目視により検査した。結果を表１に示す。なお、錫
残留物へのパラジウムの吸着量は、アクチベータ液のパ
ラジウム濃度にも依存することから、評価を容易ならし
めるためアクチベータ液中のパラジウム濃度を通常の１
０倍濃度とした。Next, the six printed wiring boards thus obtained were each subjected to electroless nickel plating by the steps shown in Table 1 to form an electroless nickel plating film on the copper circuit pattern. After the plating treatment, it was visually inspected whether a nickel film was deposited on the substrate other than the copper circuit pattern. Table 1 shows the results. Since the amount of palladium adsorbed on the tin residue also depends on the palladium concentration of the activator solution, the palladium concentration in the activator solution is reduced to a normal value of 1 to facilitate evaluation.
The concentration was set to 0 times.
【００１７】[0017]
【表１】 [Table 1]
【００１８】表１の結果から、本発明の無電解めっき方
法によれば、錫又は錫合金皮膜をエッチングレジストと
して回路パターンの形成を行ったプリント配線板の銅回
路パターン上に、回路パターン以外の非導電性基板部分
へめっき皮膜が析出することを確実に防止して、銅回路
パターン上のみに確実にめっき皮膜を形成することがで
きることが確認された。According to the results shown in Table 1, according to the electroless plating method of the present invention, a circuit pattern other than a circuit pattern was formed on a copper circuit pattern of a printed wiring board on which a circuit pattern was formed using a tin or tin alloy film as an etching resist. It was confirmed that the deposition of the plating film on the non-conductive substrate portion was reliably prevented, and the plating film could be reliably formed only on the copper circuit pattern.
【００１９】[0019]
【発明の効果】以上説明したように、本発明のプリント
配線板の銅回路パターン上への無電解めっき方法によれ
ば、錫又は錫合金皮膜をエッチングレジストとして回路
パターンの形成を行ったプリント配線板の銅回路パター
ン上に、回路パターン以外の非導電性基板上へめっき皮
膜が析出することを確実に防止して、銅回路パターン上
のみにめっき皮膜を形成することができる。As described above, according to the method of electroless plating on a copper circuit pattern of a printed wiring board according to the present invention, a printed wiring formed by using a tin or tin alloy film as an etching resist is formed. It is possible to reliably prevent the plating film from depositing on the non-conductive substrate other than the circuit pattern on the copper circuit pattern of the board, and to form the plating film only on the copper circuit pattern.
Claims (1)
膜をエッチングレジストとして回路パターン状に形成
し、該錫又は錫合金めっき皮膜形成部分を残して銅層を
エッチング除去し、基板上に回路パターンを形成した
後、該回路パターン表面の錫又は錫合金皮膜を溶解除去
することにより得られた銅回路パターン上に無電解めっ
きを施す際、上記銅回路パターンを有する基板を硫酸パ
ラジウムの硫酸酸性水溶液に浸漬して銅回路パターン上
にパラジウムを触媒核として置換析出させ、次いで該基
板を酸で洗浄した後、無電解めっきを施すことを特徴と
するプリント配線板の銅回路パターン上への無電解めっ
き方法。A tin or tin alloy film is formed in a circuit pattern on a copper layer of a non-conductive substrate as an etching resist, and the copper layer is removed by etching while leaving the tin or tin alloy plating film forming portion. After forming a circuit pattern on the substrate, when performing electroless plating on the copper circuit pattern obtained by dissolving and removing the tin or tin alloy film on the surface of the circuit pattern, the substrate having the copper circuit pattern is palladium sulfate. Immersed in a sulfuric acid solution of sulfuric acid to deposit and replace palladium on the copper circuit pattern as a catalyst nucleus, then wash the substrate with acid, and then apply electroless plating on the copper circuit pattern of the printed wiring board. Electroless plating method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5123580A JP2737599B2 (en) | 1993-04-27 | 1993-04-27 | Electroless plating method on copper circuit pattern of printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5123580A JP2737599B2 (en) | 1993-04-27 | 1993-04-27 | Electroless plating method on copper circuit pattern of printed wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06310831A JPH06310831A (en) | 1994-11-04 |
| JP2737599B2 true JP2737599B2 (en) | 1998-04-08 |
Family
ID=14864110
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5123580A Expired - Fee Related JP2737599B2 (en) | 1993-04-27 | 1993-04-27 | Electroless plating method on copper circuit pattern of printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2737599B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10054544A1 (en) * | 2000-11-01 | 2002-05-08 | Atotech Deutschland Gmbh | Process for the chemical metallization of surfaces |
| JP2010031312A (en) * | 2008-07-28 | 2010-02-12 | Ne Chemcat Corp | Pattern plating film, and forming method thereof |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS528473A (en) * | 1975-07-08 | 1977-01-22 | Hirotoshi Nomura | Method of manufacturing printed wiring board using tinnnickel alloy plated on substrate as etching gist |
| DE2847298A1 (en) * | 1978-10-27 | 1980-05-08 | Schering Ag | METHOD FOR PRODUCING METAL PATTERNS ON AN INSULATING SUPPORT |
| JPS61294891A (en) * | 1985-06-21 | 1986-12-25 | シチズン時計株式会社 | Surface treatment for circuit board |
-
1993
- 1993-04-27 JP JP5123580A patent/JP2737599B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06310831A (en) | 1994-11-04 |
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| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |