JP2726175B2 - Display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device for displaying radar video.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing a conventional radar video display device disclosed in, for example, Japanese Patent Publication No. 1-49906. In the figure, 1 is an A / D converter for A / D converting the input data video S _R , 2 is a threshold judging circuit for outputting only a signal exceeding a predetermined threshold, and 3 is a track generation memory to be described later. An adder circuit for adding a signal obtained by performing a predetermined arithmetic operation to the read output and the output of the A / D converter 1, a track generation memory 4 to which the added output of the adder circuit 3 is input as a write input; Is an arithmetic circuit for performing a predetermined arithmetic operation on the readout output of the wake generating memory 4 as described above, 6 is a synthesizing circuit for adding and synthesizing the output data from the wake generating memory 4 and the raw received signal as the latest data, It is subjected to D / a conversion to the additive synthesis output from the synthesizing circuit 6, an analog display signal S _d, CR
It is a D / A converter that outputs to T and the like.

Next, the operation will be described. In the conventional radar video display device, data in a memory area designated by an address in the same distance and the same direction as the input radar video is read out from the wake generation memory 4 and multiplied by a constant number smaller than 1 in an arithmetic circuit 5, and The output of the arithmetic circuit 5 and the output of the threshold value judgment circuit 2 are added, and the memory area at the same address as the readout of the track generation memory 4 is stored again.
Such processing is performed for each radar scan, and the combined output data of the wake generation memory 4 and the latest data of the input radar video directly input via the A / D converter 1 are combined by the combining circuit 6, and D D / A conversion by the / A converter 7 and CR
This is displayed on a display such as T.

[0004]

The conventional radar video display device is constructed as described above. Since the coefficient of the arithmetic circuit is constant, the afterimage time cannot be freely controlled, and only a fixed trail process can be performed. There is a problem that the video cannot be displayed on a normal television screen, and the display screen cannot be instantaneously enlarged or reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a display device capable of freely controlling the afterimage time and displaying radar video on a normal television screen. Aim.

It is another object of the present invention to provide a display device capable of instantaneously enlarging or reducing a display screen and not deteriorating the display resolution of a monitor even if the display screen is moved to an arbitrary position.

[0007]

A display device according to the present invention uses a large-capacity memory larger than a raster display capacity .

[0008]

[0009]

The display device according to the present invention is an address adder.
And a multiplexer with a resolution higher than the display resolution of the raster.
Since a large amount of memory is used, the display screen can be instantly expanded.
It can be scaled up and down, and can be monitored even when moved to any position.
Display resolution is not degraded .

[0010]

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a display device according to an embodiment of the present invention. In FIG. 1, reference numeral 10 denotes a switching and synthesizing circuit for taking out one of several types of radar video and selecting or synthesizing it. 1 is a switching and combining circuit 10
A / D converter for converting an analog radar video signal output from a digital signal into a digital signal, 11 is a range clock generator, 12 is a sinROM, and 13 is a sinROM.
A multiplier for multiplying the output of the range clock generator 11 by the output of the range clock generator 11; Reference numeral 3 denotes an addition circuit that adds the output of the EXP 14 and the offset value X from the control system 23. Also, 15 is cosRO
M, and the same processing as in the sinROM system is performed in the order of the multiplier 13, the EXP 14, and the addition circuit 3. Then, the polar coordinates are converted into the rectangular coordinates by such processing. 16 orthogonal coordinate system output of the video signal and the adder circuit 3 is output from the A / D converter 1, reading of the data to be described later, a buffer memory so as not to interfere with the writing portion, the 17 A raster coordinate generator 18 for generating raster coordinates from an input raster display clock 26, a video memory 18 for reading and writing data, and 19 for reducing the level of the data written in the video memory 18 gradually with the passage of time. And
A trail circuit (afterimage processing means) for performing a process of gradually erasing the video on the screen, 20 is a video signal, a rectangular coordinate system (X, Y), a raster coordinate system (X, Y), a write timing, and an output of the trail circuit 19 Is output to one transmission line, 21 is a data bus in which video signals from the multiplexer 20 and data read from the video memory 18 are commonly used, and 22 is video data from the data bus 21. output register and the shift register for taking out, by instruction from 23 CPU 25, and switching and combining circuit 10, EXP14, the offset value X is added by the adding circuit 3, Y, trails coefficients, read out and controls the writing of video memory 18 Control system 7 is an output register and an output from the shift register 22 A D / A converter 24 for converting a certain digital value into an analog signal, inputs a raster display video signal as an output result of the D / A converter 7 and a V / H synchronization signal generated from a raster coordinate generator 17. Monitor.

Next, the operation will be described. The switching and synthesizing circuit 10 selects or synthesizes only one radar video from several kinds of input radar videos. The output signal is digitized by the A / D converter 1 and input to the buffer memory 16.

The azimuth signal (θ) is obtained by a sinROM
12 and the cos ROM 15, the sin θ signal and co
The signal is converted into an sθ signal, and is multiplied by the multiplier 13 with output data from the range clock generator 11. The multiplied output is expanded or reduced by the EXP 14 according to the expansion control signal from the control system 23. The enlarged or reduced data is combined with the offset value X or the offset value Y by the adding circuit 3, and the display center coordinate system is shifted. With such an operation, the polar coordinate format of the azimuth signal is converted into X and Y in the rectangular coordinate system.
X and Y orthogonal coordinate position data (X, Y) are also input to the buffer memory 16. The buffer memory 16 is used so that the signal does not interfere with the operation of the next multiplexer 20.

The multiplexer 20 has a buffer memory 1
6, the (X, Y) write address data and the (X, Y) address of the raster coordinate generator 17 obtained by converting the raster display clock 26 into display address data under the control of the control system 23 are input. The multiplexer 20 performs an operation of switching the display to the writing side at a writing timing from the raster coordinate generator 17, that is, at a retrace time that is a time other than the display. When the mode is switched to the write side, write address data (X, Y) is input. When the display is switched to the display side, display address data (X, Y) is input.

The output data from the multiplexer 20 is
It is stored in the video memory 18. The data stored in the video memory 18 is connected to a data bus 21. Data from the data bus 21 is input to the output register and the shift register 22 and input to the trail circuit 19.

The data input to the output register and shift register 22 is connected to a D / A converter 7. As a result, the analog signal is output to the monitor 24 together with the V / H synchronization signal from the raster coordinate generator 17, and the required video is displayed on the monitor 24.

Next, the flow of data input to the trail circuit 19 will be described. The trail circuit 19 is configured so that the processing coefficient can be freely changed by the output of the control system 23 under the control of the CPU 25. For example, when the trail coefficient is set to -1 under the control of the CPU 25, when the video amplitude is 256 gradations, all are erased in 256 frames. When the trail coefficient is set to 0, the data inputted from the data bus 21 is displayed on the monitor in the state of the overwriting function which is stored as it is without being reduced. Therefore, a display device in which an afterimage remains forever is provided. Also, the trail coefficient is -2,
When the trail coefficient is set to -256, the displayed data is instantaneously displayed (in the case of one frame of the 60 Hz non-interlaced display, when the trail coefficient is set to -256). , About 16.7 ms).

The video memory 18 by the CPU 25
, The trail circuit 19 is operated once every two raster scans to reduce the display data signal amplitude,
Further, once every three raster scans, the trail circuit 19
Can be operated to reduce the amplitude of the display data signal to further extend the afterimage time.

As described above, the trail circuit 19 includes the CPU
The coefficient control from 25 changes the data input from the data bus 21 to increase the degree of freedom of the display device.

In the above embodiment, a display device using a memory having a resolution of 1: 1 with respect to the display resolution of the raster (X and Y each having 10 bits and a display resolution of 1024 × 1024) is shown. Large-capacity memory larger than the capacity (for example, both X and Y are 12 bits and 4096 ×
4096 display capacity). In this case, a display device that can instantaneously enlarge or reduce the display screen and that does not deteriorate the display resolution of the monitor even when moved to an arbitrary position can be realized. Becomes

FIG. 2 is a block diagram of a display device showing another embodiment of the present invention having such a large capacity memory. In the figure, the same reference numerals as those in FIG.
100 is an output controller, 101 is a multiplexer (address offset circuit) having an address addition function, 1
03 is a timing controller, 104 is 4096 × 4
A video memory having a display capacity of 096 and 105 is an address line switch. Further, FIG. 3 is a diagram showing the area when scaling display device according to another embodiment of the present invention. In the figure, A is the actual display area, B video Note
It is a virtual display screen of 4096 × 4096 points assumed on the screen. FIG. 4 is a view showing display writing of a display device according to another embodiment of the present invention, and FIG. 5 is an enlarged view of FIG.
It is a figure showing each dot of a screen at the time of reduction .

Next, the operation will be described. In order to move the display screen to an arbitrary position, the CPU 25 controls the output controller 100 that generates a display offset address. The timing controller 103 generates a write timing for moving the multiplexer 101 to the write address side at the retrace time of the raster scan, and a raster coordinate generator 1 for generating raster coordinates.
7 controls. The buffer memory 1
The operations up to 6 are the same as in the above embodiment. However, the offset values X and Y synthesized by the adding circuit 3 are offset values in the 10-bit area in the above embodiment, but are offset values in the 12-bit area in the present embodiment.

The operation of performing the data enlargement / reduction processing is performed by the same write address (X, Y) as the processing shown in FIG.
And a display offset address from the output controller 100, and a video memory for data having a display resolution or higher.
The memory to the memory 104 is performed by the multiplexer 101 that switches the address timing under the control of the timing controller 103.

The enlargement / reduction of the display screen will be described below with reference to FIGS. As shown in FIG. 3, the actual display area A of the display device is 1024.times.1024, but by providing a sufficient video memory, it is possible to provide a 4096 area having an area larger than the display area, for example, a 12-bit area for both X and Y.
A virtual display screen B having a display area of × 4096 is provided. The virtual display screen is provided with an address for each dot in both X and Y.

[0025] If you want to enlarge the display screen, X, Y together,
For example, the position of 255 dots is set to the address 0 of the actual display screen. Therefore, as shown in FIG. 4, the display write area of 10 bits for both X and Y is shifted by the multiplexer 101 by the display address to an arbitrary reference position ( +256
Address), an offset is taken at a position of 255 dots in both X and Y. The output of the multiplexer 101 is sent to the address line switch 105 for a 10 bit × 10 bit
Input the display address data and input it as 12bit x 12bit
When the input is shifted to 1 to 10 bits of the video memory 104, the display screen is the same as the original monitor display screen.
The screen is enlarged .

Similarly, 2-11bi of the video memory 104
If the input is shifted to t , the area enclosed by the dotted line in FIG.
As shown in the area, the scale of 1/2 of the above largest screen
This is the screen for displaying with . The screen display in this case is
Actually, the screen displayed by 11bit x 11bit is 10bit
Since the display is made by × 10 bits, as shown in FIG. 5, the display is thinned out by one dot. It should be noted that the address of the thinned portion is corrected by using a circuit for incrementing the address.

To reduce the display screen, a multiplexer 101 shown in FIG. 4 gives a display offset at a position of 0 dot for both X and Y. The multiplexer 101
Is input to the address line switch 105, and its 10bi
t × 10-bit data is stored in the video memory 104 from 3 to 12
Shift to bit and input. The display screen in this case is 4
The most reduced that displays all of the display area of 096 × 4096
Screen (be displayed in 1/4 of the scale of the screen to expand the best
Screen in case of Note that this display is a display in which three dots are thinned out, as shown in FIG.

As shown in FIG. 2, data stored in an arbitrary bit area in the video memory 104 is transmitted to the data bus 21.
Connected to Data from the data bus 21 is connected to an output register and a shift register 22, passes through the D / A converter 7, and is displayed on a monitor 24.

In this way, by switching display addresses to address lines having different weights and inputting them, it is possible to instantaneously enlarge or reduce the display screen without deteriorating the display resolution. By giving the address an offset, the display screen can be instantaneously moved without deteriorating the display resolution.

[0030]

As described above, according to the display device of the present invention, a large-capacity memory having a raster display resolution or more is used.
That the display screen can be instantaneously enlarged or reduced.
And the display resolution of the monitor deteriorates even if it is moved to any position.
There is an effect that does not give .

[0031]

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a display device according to an embodiment of the present invention.

FIG. 2 is a configuration diagram showing a display device according to another embodiment of the present invention.

FIG. 3 is an enlarged view of a display device according to another embodiment of the present invention;
It is a figure showing the field at the time of reduction.

FIG. 4 is a diagram showing display writing of a display device according to another embodiment of the present invention.

FIG. 5 is a diagram showing each dot on the screen at the time of enlargement / reduction in FIG. 3;

FIG. 6 is a block diagram showing a conventional radar video display device.

[Explanation of symbols]

 Reference Signs List 1 A / D converter 2 Threshold judgment circuit 3 Addition circuit 4 Wake generation memory 5 Arithmetic circuit 6 Synthesizing circuit 7 D / A converter 10 Switching and synthesizing circuit 11 Range clock generator 12 sinROM 13 Multiplier 14 EXP 15 cosROM 16 Buffer memory 17 Raster coordinate generator 18 Video memory 19 Trail circuit 20 Multiplexer 21 Data bus 22 Output register and shift register 23 Control system 24 Monitor 25 CPU 26 Raster display clock 100 Output controller 101 Multiplexer 103 Timing controller 104 Video memory 105 Address line switch

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-3-68886 (JP, A) JP-A-63-48485 (JP, A) JP-A-63-26070 (JP, A) JP-A-61-1988 95263 (JP, A) JP 1-32958 (JP, B2) JP 3-34831 (JP, B2)

Claims (1)

(57) [Claims] 1. A display device for displaying radar video on a monitor by raster scanning, a coordinate conversion means for converting azimuth data corresponding to video data based on the radar video into rectangular coordinate data and outputting the data, and A video memory for storing the video data at an address set so as to correspond to a position coordinate represented by the orthogonal coordinates of the dots of the virtual display screen obtained by enlarging the display screen by a predetermined number of dots, An address is output, and the video data is written into an address of the video memory corresponding to the rectangular coordinate data output from the coordinate conversion means.
A display address group for sequentially reading video data in an area corresponding to the display screen of the monitor on the virtual display screen of the video memory from a start address of the video memory is generated. An address offset circuit for adding and outputting an offset value; and outputting the output of the address offset circuit to an address line having a different weight of the video memory to an address line having the highest weight.
To the address line with a smaller weight based on the address line
A display device comprising: an address line switch capable of shifting and inputting by the number of address lines.