JPH0572998A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To realize the liquid crystal display device which puts both a video display part and a graphic display part in the best display quality states by controlling an LCD according to adequate gradation characteristics of the both. CONSTITUTION:When graphic data are written in frame memory 4 or 5, a flag generator 26 generates a flag with a GC address as a write address and writes it in a flag memory 27 or 28. When the graphic data are read out of the frame memory 4 or 5, an address is inputted to the frame memory 4 or 5 and flag memory 27 or 28 and data are read out, put together, and inputted to a mixer 6 and mixed with the graphic data given priority. An LUT 12 identifies the graphic data from the sent data by using the flag and outputs gradation control data matching the video data and graphic data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device in which incompatibility of gradation characteristics is improved when video data display and graphic data display are superimposed.

[0002]

2. Description of the Related Art There is a liquid crystal display device which displays video data by using an LCD (liquid crystal display element) for displaying the video data and superimposing the graphic data. For example, for an aircraft, it is a case where information such as the altitude and the attitude of the aircraft is superimposed on a photographed aerial photograph by superimposing a scale display and a graphic display of an aircraft model.

An example of such a conventional liquid crystal display device is shown in FIG. In the figure, 1 is an I / O port for receiving external data to be displayed as graphic data and outputting this data to the next stage. The CPU 2 uses the graphic controller (hereinafter referred to as G
Call C) 3. Reference numeral 4 denotes a frame memory A that stores data for one frame by matching each pixel of the display unit with each other.
Is a similar frame memory B, and the contact a of the switch S ₁ ,
Graphics data from the GC3 when c is connected is written into the frame memory A4, graphic data written in the frame memory B5 is outputted to the mixer 6 via the b-c contact of the switch S _2.

On the other hand the video data is converted into digital data is input to the AD converter 8 via an amplifier 7, written in the frame memory C9 via a-c contacts of the switch S _3, previously written into the frame memory D10 The video data being input is input to the mixer 6 via the bc contact of the switch S ₄ . The mixer 6 is a graphic data priority type mixer that preferentially outputs the graphic data when the graphic data and the video data are simultaneously input, stops the video data, and outputs the video data when the graphic data is not input.

Reference numeral 11 is a timing controller A for controlling the operation timings of the GC 3 and the AD converter 8 and for simultaneously switching the contacts of the switches S ₁ , S ₂ , S ₃ , S ₄ which are interlocking switches. .. Each of the above circuits belongs to the SG section (symbol generation section).

Reference numeral 12 denotes an LUT (Lo that stores a table for converting the input digital amount data into gradation control data corresponding to the input in order to convert the data.
ok Up Table), each input data is converted by the LUT 12 into gradation control data proportional to the size of each data. This output data is converted into an analog signal by the DA converter 13 and displayed on the LCD 14. 15 is the LUT
12, a timing controller B for controlling the operations of the DA converter 13 and the LCD 14. The circuits after the above LUT 12 belong to the DU section (display unit section).

To explain the outline of the operation of this conventional device, the SG section expands the video and graphic data into the frame memories A4, B5, C9 and D10 as digital data, mixes the graphic data with priority, and then the DU section. Then, in the DU unit, the LUT 12 converts the data into a signal according to the gradation characteristic of the LCD 14 and converts it into an analog signal, and drives the LCD 14.

[0008]

On the other hand, in general, the LCD gradation characteristic for graphics and the LCD gradation characteristic for video are not the same, and when determining the content of the LUT 13, that is, gradation control data, The only option was to sacrifice display quality. FIG. 4 shows a relationship curve diagram between the gradation control voltage and the brightness. 4-bit gradation data width (16 gradations) for both video display and graphic display
If 16 gradations are set in the graphic display range, only 8 to 10 gradations can be displayed in video display. That is, in the figure, when p and q are the range of gradation control voltage for graphic display, the range r-s of gradation control voltage for video display is 8 gradations.

The present invention has been made in view of the above points, and an object of the present invention is to control the LCD by gradation characteristics suitable for each of the video display portion and the graphic display portion so as to optimize the display quality of both. It is to realize a liquid crystal display device which can be brought into a state.

[0010]

According to the present invention for solving the above-mentioned problems, there is provided an SG section having a frame memory and a mixer for superimposing video data and graphic data on an LCD for display, and the video data. It is composed of an LCD for displaying graphic data, an LUT having data for determining the gradation characteristics of the LCD as a table, and a DU section including a DA converter for converting into an analog signal for displaying on the LCD. In a liquid crystal display device according to the present invention, a flag generator that generates a flag to be used as an index of graphic data written in a frame memory provided in the SG unit, and the flag is stored in the frame memory. The flag memory that is read out together with the data and input to the mixer, and the flag memory that is identified by the flag. ; And a LUT for storing two types of gradation control data corresponding to each of data and video data Fick as a table, the said SG portion D
By adding the 1-bit flag to the display data transmitted between the U parts, it is possible to display on the LCD with optimum gradation characteristics for video and graphic.

[0011]

The graphic data is written to the frame memory in the write mode by the GC address, and at the same time, the flag generator generates a flag and writes it in the flag memory. In the read mode, graphic data is read from the frame memory and flags are read from the flag memory.
Input to mixer.

The mixer gives priority to passing graphic data having a flag. When the LUT has a flag, it outputs data of gradation characteristics for graphics. For gradation-free video data, video gradation characteristic data is output, and for any data, the optimum gradation characteristic data is supplied to the LCD.

[0013]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention. In the present invention, since the data processing section of the graphic display section for processing the output data of the GC3 (shown in FIG. 3) of the conventional liquid crystal display device shown in FIG. 3 is improved, only that section is shown. .. Since the GC address and the GC graphic data are output from the GC 3, the input data for the apparatus of the embodiment is the GC address and the GC graphic data.

In the figure, the same parts as those in FIG.
It is attached with a code. In the figure, S_FiveIs G to the frame memory
Set the write address of C graphic data to frame
Switching between the memory A4 and the frame memory B5
The frame contact when the moving contact c enters the side a.
Data is written to memory A4, and moving contact c is set to b.
Writing data to frame memory B5 when entering side
Is done. S₆Frame GC graphic data
Switch to memory A4 and frame memory B5
Is a switch for setting the relationship between the contact position and the frame memory.
Switch is switch S _FiveIs the same as.

Reference numeral 21 denotes a selector A for switching between the GC address which is a write address and the read address output from the read address generator 22 for input to the frame memory A4. The selector 23 similarly switches between the GC address and the read address. Selector B for inputting to the frame memory B5. Although the selector A21 and the selector B23 are also included in the conventional device, they are not shown in FIG. Reference numerals 24 and 25 amplify the GC graphic data and respectively amplify the frame memory A4.
And an amplifier to be input to the frame memory B5.

Reference numeral 26 is a flag generator for generating data of "1" as a flag when the GC address is input. The output flag is written in the flag memory A27 and the flag memory B28 by the GC address. The flag memory A27 and the flag memory B28 are memories having a 1-bit data width for recording a flag, and the address width thereof is at least the same area as the area where the frame memory A4 and the frame memory B5 actually store data. Covering. An amplifier 29 amplifies n + 1-bit data obtained by combining the n-bit data read from the frame memory A4 and the 1-bit flag read from the flag memory A27 according to the read address.
Similarly, 0 is an amplifier for amplifying the data from the frame memory B5 and the combined data of the flag from the flag memory B28.

S ₇ is a switch for switching the outputs of the amplifiers 29 and 30 and inputting it to the mixer 6. S ₅ , S ₆ and S ₇ are interlocked, and writing and reading of data with respect to the frame memory A and the frame memory B are performed. It has the function of making and alternate.

31 is a selector A21, a selector B23,
The timing controller C has a function of controlling the operations of the switches S ₅ , S ₆ and S ₇ to control the alternate operation of the frame memory A 4 and the frame memory B 5 and also initializing the flag memory A 27 and the flag memory B 28.

Next, the operation of the embodiment configured as described above will be described. The frame memory A4 and the frame memory B
Since each line of 5 operates alternately by switching the switches S _5, S _6, S _7, shows only lines of the frame memory A4 in FIG. 2 will be described based on this. In the figure, the same reference numerals as those used in FIG. 1 are used for each portion.

First, the operation of writing the GC graphic data to the frame memory A4 will be described. At the time of data writing, the moving contact c of the switches S ₅ and S ₆ is set to the contact a side by the control of the timing controller C31.
The C address is connected to the selector A21, and the GC graphic data is input to the amplifier 24. Also, switch S
The moving contact c of ₇ is connected to the contact b, and the frame memory A
4 and the output circuit of the flag memory A27 are disconnected from the mixer 6. At the same time, the flag memory A27 is initialized by the control of the timing controller C31, and the contents thereof are all zero. Further, the selector A21 inputs the GC address to the frame memory A4 under the control of the timing controller C31.

The GC graphic data amplified by the amplifier 24 is written to the address of the frame memory A4 designated based on the GC address, and the flag output from the flag generator 26 is also written to the same address of the flag memory A27.

[0022] When the write mode for the frame memory A4 is completed, the timing controller C31 places the dynamic contact c of the switch S _5, S _6, S ₇ on the opposite side contacts, read from the address generator 22 reads the output of the selector A21 The address is switched and input to the frame memory A4 and the flag memory A27. By this read address and a 1-bit flag from n bits of GC graphic data and flag memory A27 from the frame memory A4 is output, are synthesized after being amplified by the amplifier 29, the a-c contact of the switch S ₇ It is then input to the mixer 6.

Video data is separately input to the mixer 6, and mixed here, but data accompanied by a flag,
That is, when the GC graphic data is input, the input of the video data is blocked and only the graphic data is passed together with the flag. When the flag is not input, that is, when the GC graphic data is not input, the video data is output. That is, the graphic data is mixed with priority.

The LUT 12 checks the existence of the flag,
It is switched so that the gradation characteristic data for graphics is output to the data with the flag and the gradation characteristic data for the video is output to the data without the flag. That is, the range of the gradation control voltage is extended and given to the video data.

When the timing controller C31 switches the frame memory A4 side to the read mode, the frame memory B5 side is in the write mode and operates as described above.

As described above, according to this embodiment, the LUT distinguishes between the video data and the graphic data by adding 1 bit for the flag to the display data conventionally transmitted from the SG section to the DU section. LUT for video
And LUT for graphics can be set respectively, and the gradation range of video data is not narrowed, and each data has an optimum gradation characteristic for LCD.
It is now possible to superimpose on.

The present invention is not limited to the above embodiment. For example, in the embodiment, an example in which a frame memory for video data and a frame memory for graphic data are separately provided as in the conventional device has been shown.
It is possible to adopt a method in which video data is first written in one frame memory, and graphic data is overwritten on the same frame memory at the blanking time of the video data. Even in this case, if a memory having a data width of 1 bit is added and "0" is written when writing video data and "1" is written when writing graphic data from GC, the same operation is performed. be able to.

[0028]

As described in detail above, according to the present invention, the LCD can be controlled by the video display gradation characteristic and the graphic display portion by the graphic gradation characteristic. Since both display qualities can be obtained in the best condition, the practical effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram showing a portion related to graphic display data of an apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram showing only one system for explaining the embodiment.

FIG. 3 is a block diagram showing a schematic configuration of a conventional liquid crystal display device.

FIG. 4 is a relationship curve diagram between the brightness of the LCD and the gradation control voltage, and particularly shows the gradation characteristics of the graphic display data and the video display data.

[Explanation of symbols]

 4, 5 Frame memory 6 Mixer 12 LUT 14 LCD 26 Flag generator 27, 28 Flag memory

Claims (1)

[Claims] 1. An SG unit having a frame memory and a mixer for superimposing video data and graphic data on an LCD for display, an LCD for displaying the video data and the graphic data, and a gradation of the LCD. An LUT having data for determining characteristics as a table, and the L
In a liquid crystal display device including a DU section including a DA converter for converting into an analog signal for displaying on a CD, a frame memory (4, 4) provided in the SG section is provided.
5) a flag generator (26) for generating a flag to be used as an index of the graphic data to be written, and for storing the flag and reading it together with the data stored in the frame memory (4, 5) A flag memory (27, 28) input to the mixer (6), and an LUT (12) that stores, as a table, two types of gradation control data corresponding to each of the graphic data and the video data identified by the flag. ) And 1 is added to the display data transmitted between the SG unit and the DU unit.
A liquid crystal display device, characterized in that, by adding the bit flag, it is possible to display on the LCD with optimum gradation characteristics for video and graphic respectively.