JP3522299B2 - Image storage device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image storage device which can be used, for example, for editing a video tape or searching the contents of a video database.

[0002]

2. Description of the Related Art The outline of a material recorded as a visible image such as a so-called cine film and the selection of a desired cut can be performed simply by visually observing the material.

On the other hand, in order to know the outline of a material in which moving image data such as a video tape or a video disk is invisible, (a) display one screen at a time on a monitor and perform a high speed search or the like as necessary. Method (b) A method of reducing moving images of a plurality of frames by a multi-screen display on a monitor and displaying them in a scrolling manner (see Japanese Patent Publication No. 61-44437) is adopted.

However, in the method (a), it takes more time to confirm the outline of the video tape of, for example, one hour of a television program, and there is a disadvantage that the editing efficiency is deteriorated. Further, in the method (b), short cuts such as TV commercials may be overlooked, and there is the inconvenience that the confirmation is not reproducible and varies depending on the operator.

Therefore, the applicant of the present invention has previously proposed a display device capable of easily grasping the overall flow of an image (Japanese Patent Laid-Open No. Hei 2).
-260075).

FIG. 9 shows the data processing of this display device. Reference numeral 1 indicates a video image group as an editing target as a whole. The video image group 1 includes a moving image corresponding to a series of moving image data recorded on, for example, a video tape or a video disc in a unit of frame 2 for a time (t).
It can be considered that they are arranged in the (axis) direction.

The frame frequency of the video signal is 30 Hz
Since it is (NTSC system), 1 as video image group 1
30 frames 2 are arranged per second. 2A to 2E are
A series of frames of the video image group 1 is shown.

Reference numeral 4 denotes a vertical slit (input slit) for inputting image data, which is set on the frame 2. The vertical slit 4 samples the image of the frame 2. The vertical slit 4 is scanned in the horizontal direction (H direction) at a predetermined speed, and when the right end portion of the frame 2 is reached, the vertical slit 4 is repeatedly scanned in the H direction from the left end portion again. Therefore,
The vertical slit 4 is scanned in a diagonal Ht direction in a three-dimensional space including the time axis.

When the vertical slit 4 scans the video image group 1 from the left end to the right end in the Ht direction, it crosses f frames 2 and n frames (normally n = 1) are framed by the vertical slit 4. Assume that one slit-like image is sampled for.

When f is selected to be a multiple of n, f = nX is established using a predetermined integer X, and a frame group (3
X slit-shaped images are sampled from A, 3B, etc.).

In this example, the time required for the vertical slit 4 to scan the video image group 1 from the left end to the right end in the Ht direction is set to 12 seconds and n = 1, and f = X = 12 × 30 = 360.

Then, the X slit-shaped images obtained from the frame group 3A are joined in the horizontal direction and then compressed in the horizontal and vertical directions, respectively, and the reduced screen 6 is displayed.
A is formed. The reduced screen 6A is fitted into the display screen 5 corresponding to one frame memory. Similarly, X slit-shaped images obtained from the frame group 3B are joined in the horizontal direction and then compressed to ⅕ to form a reduced screen 6B. The reduced screen 6B is displayed on the display screen 5B.
It is fitted next to the reduced screen 6A.

A reduced screen is similarly formed for the following frame groups, and the reduced screen is sequentially fitted into the display screen 5.

In practice, the slit-shaped images sampled by the vertical slits 4 are generated one by one in a time series, so they are compressed in the order of generation and fitted into the display screen 5 one by one.

For example, the vertical slits 4A to 4E are assigned so as to sequentially scan in the H direction corresponding to the frames 2A to 2E. The images 4a to 4e on the slits sampled by the vertical slits 4A to 4E are respectively compressed to be images of the vertical slits (output slits) 7A to 7E of the display screen 5.

FIG. 10 shows a display device for processing image data. In the figure, reference numeral 8 indicates a host computer. This host computer 8
Also functions as the coordinate value / frame number conversion means 9 and the control means 10 for the entire apparatus.

Reference numeral 11 is a system bus, and 12 is a keyboard.
And the host computer 8 via the system bus 11.
To give various commands to.

Reference numeral 14 is a VTR as a moving image data source, and 1
Reference numeral 5 is an A / D converter. Reference numeral 16 is a video RAM (VRAM1) including a frame memory, and the video signal output from the VTR 14 is separated into Y, RY, BY signals or R, G, B signals and then A / D converted. Bowl 15
Is converted into digital data and written in the video RAM 16.

The storage area of the video RAM 16 (VRAM1) corresponds to the actual display screen, as shown in FIG. 11A, in the horizontal direction (VX1 direction) with HL dots and in the vertical direction (VX1).
VL dots are formed in the Y1 direction). This video RAM1
The addresses of the respective pixel data read from 6 are coordinates (VX1, VY1) (0≤VX1≤HL-1, 0≤VY
1 ≦ VL−1).

Reference numeral 17 is an image processor.
With this image processor 17, the video RAM 1
Data of a portion surrounded by the vertical slits 4 (see FIG. 11A) is read from the image data of one frame of No. 6 and the data is compressed to form a video R including a frame memory.
The data is written in a portion surrounded by the vertical slit (output slit) 7 (see FIG. 11B) of the AM (VRAM2) 23. In addition to this, the image processor 17 uses the video RA.
It has a function of moving an instruction cursor indicating an arbitrary area surrounded by each vertical slit 7 on the screen corresponding to M23.

Expressing the image processor 17 as a set of means corresponding to the functions, the image processor 17 has an input slit moving means 18, a slit data reading means 19, an output slit moving means 20, a slit data writing means 21 and an indication cursor display. Means 22.

Similarly to the video RAM 16, the storage area of the video RAM 23 (VRAM2) also corresponds to the actual screen and is H in the horizontal direction (VX2 direction) as shown in FIG. 11B.
L dots are VL dots in the vertical direction (VY2 direction). The address of each pixel data written in the video RAM 23 is designated by the coordinates (VX2, VY2).

Reference numeral 24 is a cursor RAM for storing the position of the pointing cursor. The pixel data read from the video RAM 23 and the cursor data read from the cursor RAM 24 are supplied to the combining circuit 25 to form combined image data.

The composite pixel data output from the composition circuit 25 is converted into an analog signal by the D / A converter 26 and supplied to the monitor 27 and a video printer (not shown), and at the same time an external storage device (VTR, VTR, Floppy disk, etc.)
Also supplied to 28.

The video signal reproduced from the external storage device 28 is the A / D converter 29 and the system bus 11.
Via the video RAM 23 and cursor RAM 24
To be able to write to.

Video image group 1 output from VTR 14
Image data of the video RAM 16 (shown in FIG. 11A)
Video RAM 23 as a series of slit data via
A series of data processing operations when written in (illustrated in FIG. 11B) will be described step by step along the flowchart of FIG.

In this case, X pieces of slit data extracted one by one from each frame of the video RAM 16 are collectively compressed and reduced images 6A, 6B, ... Of (X × Y) pixels of the video RAM 23.・ It shall be written as.

[Step 101] Δ according to the following equation:
Calculate X and ΔY.

ΔX = HL / X ΔY = VL / Y ΔX and ΔY do not have to be integers, and the pixel data of the block 30 of (ΔX × ΔY) pixels of the video RAM 16 is stored in the video RAM 23. The value of one pixel 31 is compressed.

In the example of FIG. 10, in order to simplify the compression, the pixel data whose address is the coordinates (VX1, VY1) of the upper left corner of the block 30 of the video RAM 16 are used as they are as the coordinates (VX2, VY2) of the video RAM 23. Is the data of the pixel 31 whose address is. When ΔX and ΔY are non-integers, the coordinates (VX1, VY1) are not a pair of integers, so the pixel value indicated by the coordinates (VX1, VY1) is calculated by interpolation from the values of surrounding pixels. .

Further, the number h of horizontal arrangement of reduced screens (6A, 6B, etc.) consisting of X vertical slits 7 in the video RAM 23 is calculated according to the following formula. Xs is a blank pixel in the horizontal direction.

H = (HL-Xs) / X Further, the numbers FR of the reduced screens 6A, 6B ... Are set to 0, 1 ..., FR0, respectively, and FR = 0 is initially set.

Further, one frame of image data is written in the video RAM 16, and the corresponding frame number is written in the cursor RAM 24.

[Step 102] With the coordinates of the upper left corner of the reduced screen (6A, 6B, etc.) of the number FR in the video RAM 23 as (BX, BY), BX and BY are calculated according to the following equation. Xs1 is the number of pixels in the left margin, and Ys1 is the number of pixels in the top margin in the vertical direction.

BX = (FRmod h) X + Xs1 BY = [FR / h] Y + Ys1 In these formulas, (FRmod h) represents the remainder of FR / h, and [FR / h] is the maximum that does not exceed FR / h. Indicates an integer.

[Step 103] The initial values of the coordinates VX1 of the vertical slit 4 of the video RAM 16 and the coordinates VX2 of the vertical slit 7 of the video RAM 23 are set to 0 and BX, respectively.

[Step 104] The initial values of the coordinates VY1 of the vertical slit 4 of the video RAM 16 and the coordinates VY2 of the vertical slit 7 of the video RAM 23 are set to 0 and BY, respectively.

[Steps 105 and 106] The image processor 17 determines the coordinates (VX1, VY) of the video RAM 16.
After the pixel data of 1) is read and written as pixel data of the coordinates (VX2, VY2) of the video RAM 23, the value of the coordinates VY1 is increased by ΔY and the value of the coordinates VY2 is increased by 1.

[Step 107] When the data of the vertical slit 4 of the video RAM 16 is read in the D1 direction,
The data of the vertical slit 7 of the video RAM 23 is written in the D2 direction. Then, when the coordinate VY1 of the vertical slit 4 of the video RAM 16 is equal to or less than VL, the process returns to step 105, and when the coordinate VY1 exceeds VL, the process proceeds to step 108.

[Steps 108 and 109] The value of VX1 is increased by ΔX and the value of VX2 is increased by 1. This is
The position of the vertical slit 4 of the video RAM 16 is moved to the right by ΔX, and the position of the vertical slit 7 of the video RAM 23 is set to 1.
It only means moving to the right.

The host computer 8 is the VTR1.
4, the image data of the nth frame from the current frame is input and written in the video RAM 16. At this time, the frame number of the image data is written in a predetermined area of the cursor RAM 24.

[Step 110] When the coordinate VX1 of the vertical slit 4 of the video RAM 16 is HL or less, the process returns to step 104. When the coordinate VX1 exceeds HL, it means that one horizontal scanning of the vertical slit 4 of the video RAM 16 is completed.
Proceed to 11.

[Steps 111 and 112] The number FR of the reduced screen is incremented by 1, and the number FR is added to the video RAM 2.
When the number of reduced screens FR3 is equal to or less than FR0, the process returns to step 102. When the number FR exceeds the number FR0, it means that the creation of the video index for one screen is completed. Therefore, the process proceeds to step 113 for post-processing.

As post-processing, the image data in the video RAM 23 is accumulated in the external storage device 28 via the D / A converter 26, or the image data is supplied to the monitor 27 via the D / A converter 26. However, after that, the operation returns to step 101 again.

According to the above-mentioned example, a still image is formed by joining the images of the vertical slits 7 corresponding to the image data obtained by sampling using the vertical slits 4. This still image can be confirmed as a still image that is a summary of a series of moving image data compressed according to the passage of time, and if there is a sudden change such as insertion of a commercial, a disconnection occurs at a predetermined position of the still image. , It is possible to accurately recognize the entire flow of the image.

In the example of FIG. 10, the video RAM 16 for storing the input image data and the video RAM 23 corresponding to the display screen 5 are defined by the same number of pixels in the horizontal direction and the vertical direction. This is a video RAM
The image data of the video RAM 16 is compressed and written in the reduced screen area 23, but the video RAM 16 has a large capacity for the filtering process and the interpolation process for preventing the aliasing noise at the time of this compression.

However, it is not necessary to make the still image displayed on the display screen 5 so high in quality in order to confirm the outline of the moving image data and the confirmation of short cuts such as commercials.

Therefore, the present applicant has proposed a display device as shown in FIG. 13 for the purpose of reducing the memory capacity of the input image memory and making it inexpensive. This Figure 1
3, parts corresponding to those in FIG. 10 are designated by the same reference numerals, and detailed description thereof will be omitted.

In this example, a video RA is used as an input image memory between the A / D converter 15 and the system bus 11.
M40 is arranged. The capacity of the video RAM 40 is made equal to the capacity of each reduced screen area such as 6A, 6B, ... Of the video RAM 23.

In this case, each of the reduced screens 6A, 6B, ... (Shown in FIG. 14C) of the video RAM 23 is 98 × 153.
When composed of pixels, the video RAM 40 is 98 × 1
It has a capacity of 53 pixels. Then, for example, if the sampling frequency in the A / D converter 15 is 1
At 4.3 MHz, the frame data of 490 × 768 pixels output from the A / D converter 15 (see FIG. 14).
The data of 98 × 153 pixels (shown by “□”) is selectively written in the video RAM 40 from FIG.
4B).

Then, the video RAM 40 is set for each frame.
While moving the slit position in the horizontal direction at every predetermined frame from the data of 98 × 153 pixels written in
Video RAM with 1-pixel vertical slit data read out
Sequentially written in 23 reduced screen areas. This allows
A still image similar to that in the example of FIG. 10 is formed.

As described above, in the example of FIG. 13, the capacity of the video RAM 40 is made equal to the capacity of each reduced screen area of the video RAM 23, so that the memory capacity of the input image memory can be reduced and the cost can be reduced.

By the way, in the example of FIG. 13, A / D
490 × 768 of each frame output from the converter 15
Of the image data of pixels, only the image data of 98 × 153 pixels is accumulated in the video RAM 40, and the remaining image data becomes unnecessary.

Therefore, the applicant further proposed a display device as shown in FIG. In this example, the conversion speed in the A / D converter is reduced so that all the image data output from the A / D converter is stored in the video RAM 40. 15, parts corresponding to those in FIG. 13 are designated by the same reference numerals, and detailed description thereof will be omitted.

In this example, the analog color video signal output from the VTR 14 is supplied to the decoder 41 and decoded, and the three primary color signals R, G, B output from this decoder 41 are supplied to the sample hold circuit 42. It In the sample hold circuit 42, the video RAM 4
The three primary color signals R, G, and B are sample-held at the timing of the image data to be written to 0 (“□” in FIG. 14A).

The three primary color signals R, G, B output from the sample hold circuit 42 are sequentially supplied from the switch circuit 43 to the A / D converter 44, converted into digital signals, and then sequentially written into the video RAM 40. Be done.

This example is constructed as described above, and the other parts are constructed similarly to the example of FIG.

In this example, the same effects as those of the example of FIG. 13 can be obtained, and in the A / D converter 44, only the three primary color signals R, G, B of the required timing are sequentially converted into digital signals. Therefore, one A / D converter 44 can convert the three primary color signals R, G, and B into digital signals, and the cost can be reduced.

Here, in the A / D converter 15 of the example of FIG. 13, an analog signal as shown in FIG. 16A is converted into digital data as shown in FIG. 16B, and this digital data is shown in FIG. Video RAM 40 selectively
Written in. On the other hand, in the example of FIG.
After the analog signal as shown in A is sampled and held as shown in B in the same figure, it is converted into digital data by the A / D converter 44 as shown in D in the same figure, and all this digital data is written in the video RAM 40. Be done.

Considering the purpose of use of the still image,
It is also possible to further compress the useless image data.
For example, even if the allocation of 8 bits for each of R, G, and B per pixel is compressed to about 5 bits for each, there is no problem in the purpose of using the still image.

According to this example, since the capacity of the video RAM 40 is made equal to the capacity of one reduced screen area of the video RAM 23, the capacity of the video RAM 40 can be reduced and the cost can be reduced. Further, since the capacity of the video RAM 40 is reduced, the conversion speed of the A / D converter 44 that converts an analog video signal into a digital signal can be slowed down, and one A
The / D converter 44 has the effect that the three primary color signals can be sequentially converted into digital signals, and the cost can be further reduced.

[0062]

By the way, in the example of FIGS. 13 and 15, the image data of 98.times.153 pixels is written in the video RAM 40 for each frame. Of the image data, the video RAM 23 is actually used.
Only 98 pixels corresponding to one vertical slit are accumulated in. If the timing of A / D conversion can be shifted in accordance with the position of the vertical slit to be actually stored, the capacity of the video RAM 40 is sufficient for 98 pixels.

Therefore, it is an object of the present invention to stop writing unnecessary pixel data in the input image memory and to further reduce the memory capacity of the input image memory so as to be inexpensive.

[0064]

A first image storage device of the present invention comprises a conversion circuit for sampling a video signal, converting it into digital data, and outputting it as image data, and an input image memory for storing the image data. A vertical slit, which includes an output image memory for storing output image data for a display device, and a timing control circuit for controlling the operation of the conversion circuit, and the position of which moves for each frame of the video signal. Alternatively, image data for one horizontal slit is sampled by the conversion circuit and stored in the input image memory, and the stored image data for one vertical slit or one horizontal slit is transferred to the output image memory. Is characterized by. The input image memory of the first image storage device may have a capacity capable of storing the image data for one vertical slit or one horizontal slit. A second image storage device of the present invention includes a conversion circuit that samples a video signal in response to a sampling timing signal, converts the video signal into digital data, and outputs the image data, and an input image memory that stores the image data. And an output image memory for storing output image data for the display device, and a timing control circuit for controlling the operation of the conversion circuit. The timing control circuit is a sampling unit determined for each frame of a video signal. The sampling timing signal is supplied in accordance with the timing, and the image data stored in the input image memory is transferred to the output image memory at a timing determined in advance according to the capacity of the input image memory. The sampling timing (Td) of this second image storage device is set to T
0 is a predetermined offset value, Ts is a pixel clock cycle, n
When T is the number of thinned pixels and S is a series of numbers, Td = T0 + Ts × n × S. The conversion circuit of the second image storage device includes a decoder for converting the video signal into three primary color signals, and a sample hold circuit connected to the decoder for sampling the three primary color signals and holding their values. A switch circuit connected to the sample and hold circuit and sequentially outputting respective values of sampled three primary color signals, wherein the timing control circuit operates the sample and hold circuit according to the sampling timing signal, The switch circuit may operate according to a switching timing signal obtained by multiplying the sampling timing signal.
Furthermore, a third image storage device of the present invention is connected to the decoder for converting a color video signal into three primary color signals, and the three primary color signals for one pixel are connected in accordance with the timing determined for each frame of the video signal. A sample and hold circuit that samples and holds those values, a switch circuit that is connected to the sample and hold circuit, and that sequentially outputs each value of the sampled three primary color signals, and an output from the switch circuit that is digitally converted. A / D converter for outputting as image data, a latch circuit for storing the image data, an output image memory for storing output image data for a display device, and an operation for controlling the operation of the sample hold circuit. And a timing control circuit that supplies a sample and hold timing signal. And outputs a pull hold timing signal as an interrupt request signal, said from the latch circuit to the host computer to the output image memory to perform the transfer of the image data, and wherein the.

[0065]

1 is a block diagram showing the configuration of an embodiment of the present invention. In FIG. 1, parts corresponding to those in FIG. 15 are designated by the same reference numerals, and detailed description thereof will be omitted.

In this example, the video RAM 40 in the example of FIG. 3 is replaced with a slit memory 46 capable of storing image data for one slit. Further, a timing generator 45 is provided which supplies a sample hold timing signal to the sample hold circuit 42 and supplies a switching timing signal to the switch circuit 43.

This example is constructed as described above, and the other parts are constructed similarly to the example of FIG.

FIG. 2 shows how pixel data is transferred in this example. Of the image data for one frame shown in FIG. 2A, data for one vertical slit whose position moves every predetermined frame is sample-held and stored in the slit memory 46 (shown in FIG. B), and then output. It is transferred to the video RAM 23 and stored in the corresponding position of the reduced screen area (shown in FIG. 7C). Note that n in the figure is 5.

FIG. 3 shows the operation timing. A in the figure is a vertical synchronization signal Vsync, and B in the figure is a horizontal synchronization signal Hsyn.
FIG. 7C shows a sample hold timing signal. In this example, sample hold is performed once every five horizontal periods. Therefore, in this example, sample holding is performed 98 times during one frame.

Also, D and E in the same figure and F and G in the same figure.
Shows more precisely the relationship between the horizontal synchronizing signal Hsync and the sample hold timing signal. The time Td does not change in one frame, but the time Td changes when the frame changes.

The sample hold timing is expressed by the following equation: Td = To + Ts * n * S (1) Here, To is the delay amount at the leftmost vertical slit, Ts is the pixel clock period, n is the number of thinned pixels (5), and S is the slit position (0 to 152) (see FIG. 2A).

The timing generator 45 will generate the sample hold timing signal by the equation (1). Since To, Ts, and n are constants in the equation (1), it is sufficient to repeat the addition of Ts * n according to the increment of S. FIG. 4 shows an example of the adder circuit.
In the figure, 51 is a selector and latch circuit, and 52 is an adder circuit. In the circuit 51, the data of To is latched when S = 0 and the addition circuit 52 when S is 1 or more.
Output data is sequentially latched. And the adder circuit 5
In 2, the data of Ts * n is added to the output data of the circuit 51. As a result, the adder circuit 52 obtains Td data at each slit position.

FIG. 5D shows a switching timing signal, and the selection in the switch circuit 43 is switched at the rising edge of this switching timing signal. This switching timing signal is formed by multiplying the sample hold timing signal shown in FIG. 5A shows the vertical synchronization signal Vsync, and FIG.
Shows a horizontal synchronizing signal Hsync, and FIG. 8E shows an input signal of the A / D converter 44.

By the way, in this example, the slit memory 4
Transfer rate from 6 to video RAM 23 is 1 per pixel
Second / (30 frames × 98 pixels) = about 340 μsec, which is also a speed that can be achieved by software processing of the host computer 8.

FIG. 6 is a block diagram showing the structure of another embodiment of the present invention. 6, parts corresponding to those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

In this example, the slit memory 46 in the example of FIG. 3 is replaced with a latch circuit 47 for data for one pixel. The switching timing signal supplied from the timing generator 45 to the switch circuit 43 is also supplied to the host computer 8 as an interrupt request signal.

This example is constructed as described above, and the others are constructed in the same manner as the example of FIG.

FIG. 7 shows how pixel data is transferred in this example. Of the image data for one frame shown in FIG. 7A, the data for one pixel of the vertical slit whose position moves every predetermined frame is sample-held and latched by the latch circuit 47 (shown in FIG. B). After that, it is transferred to the output video RAM 23 and stored in the corresponding position of the reduced screen area (shown in FIG. 7C).

FIG. 8 shows the operation timing. A in the figure is a vertical synchronization signal Vsync, and B in the figure is a horizontal synchronization signal Hsyn.
c and C in the figure show a sample hold timing signal, D in the figure shows a switching timing signal, and E in the figure shows an interrupt request signal.

The host computer 8 which receives the interrupt request reads the data of the latch circuit 47, and the video RAM
Write in 23 appropriate positions. The time given to the host computer 8 for this processing is 340 in this example.
/ 3 = about 113 μsec, which can be processed in time even if the overhead required for interrupt processing is subtracted.

Although the vertical slits 4 and 7 are used as the input slits and the output slits in the above-mentioned embodiment, the present invention can be similarly applied to the processing using the horizontal slits. Is.

[0082]

According to the present invention, the capacity of the input image memory can be further reduced and the cost can be further reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing transfer of pixel data in the example of FIG.

FIG. 3 is a diagram showing operation timings in the example of FIG.

FIG. 4 is a diagram showing a partial configuration of the example of FIG.

5 is a diagram showing the operation timing of the example of FIG.

FIG. 6 is a block diagram showing the configuration of another embodiment of the present invention.

FIG. 7 is a diagram showing transfer of pixel data in the example of FIG.

8 is a diagram showing operation timings in the example of FIG.

FIG. 9 is a diagram for explaining data processing of the display device.

FIG. 10 is a block diagram showing a configuration of a conventional example.

11 is a diagram showing a data structure of a video RAM in the example of FIG.

12 is a flowchart showing a data processing operation of the example of FIG.

FIG. 13 is a diagram showing the configuration of another conventional example.

FIG. 14 is a diagram showing transfer of pixel data in the example of FIG.

FIG. 15 is a diagram showing the configuration of another conventional example.

16 is a diagram for explaining the example of FIG. 15. FIG.

[Explanation of symbols]

1 video footage 2 frames 4, 7 vertical slits 5 Display screen 6A, 6B reduced screen 8 Host computer 11 system bus 12 keyboard 14 VTR 17 Image Processor 23 Video RAM 25 Compositing circuit 27 monitors 28 External storage device 41 decoder 42 Sample and hold circuit 43 switch circuit 44 A / D converter 45 Timing generator 46 slit memory 47 Latch circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-2-260075 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04N 5/76-5/956

Claims (6)

(57) [Claims] 1. A conversion circuit for sampling a video signal, converting it into digital data, and outputting it as image data, an input image memory for storing the image data, and an output image for storing output image data for a display device. The conversion circuit is configured to include a memory and a timing control circuit that controls the operation of the conversion circuit, and causes the conversion circuit to sample the image data of one vertical slit or one horizontal slit whose position moves for each frame of the video signal. Stored in the input image memory and stored in one of the vertical slits or
An image storage device that transfers image data for horizontal slits to the output image memory. 2. The image storage device according to claim 1, wherein the input image memory has a capacity capable of storing image data for the one vertical slit or one horizontal slit. 3. A conversion circuit for sampling a video signal in response to a sampling timing signal, converting it into digital data, and outputting it as image data, an input image memory for storing the image data, and an output for a display device. An output image memory that stores image data, and a timing control circuit that controls the operation of the conversion circuit are included, and the timing control circuit supplies the sampling timing signal in accordance with a sampling timing determined for each frame of a video signal. Then, the image storage device in which the image data stored in the input image memory is transferred to the output image memory at a predetermined timing according to the capacity of the input image memory. 4. The sampling timing (Td)
The image according to claim 3, wherein Td is defined as Td = T0 + Ts × n × S, where T0 is a predetermined offset value, Ts is a pixel clock period, n is a thinned pixel number, and S is a series of numbers. Storage device. 5. The conversion circuit includes a decoder for converting the video signal into three primary color signals, a sample hold circuit connected to the decoder for sampling the three primary color signals and holding the values thereof. A switch circuit connected to a hold circuit and sequentially outputting respective values of sampled three primary color signals, wherein the timing control circuit operates the sample hold circuit according to the sampling timing signal, and the switch circuit Operates according to a switching timing signal obtained by multiplying the sampling timing signal,
The image storage device according to claim 3. 6. A decoder for converting a color video signal into three primary color signals, and a decoder which is connected to the decoder and which samples one pixel of the three primary color signals in accordance with a timing determined for each frame of the video signal and holds the values thereof. A sample and hold circuit, a switch circuit connected to the sample and hold circuit, which sequentially outputs respective values of the sampled three primary color signals, and an A / A which digitally converts the output from the switch circuit and outputs it as image data. A D converter, a latch circuit for storing the image data, an output image memory for storing output image data for a display device, and a timing for supplying a sample hold timing signal for controlling the operation of the sample hold circuit. And a control circuit, wherein the sample hold timing Outputs a grayed signals as interrupt request signals, an image memory device which from the latch circuit to the host computer to perform the transfer of said image data to said output image memory.