JP2719597B2 - Method for manufacturing active matrix silicon thin film transistor substrate - Google Patents
Method for manufacturing active matrix silicon thin film transistor substrateInfo
- Publication number
- JP2719597B2 JP2719597B2 JP63229426A JP22942688A JP2719597B2 JP 2719597 B2 JP2719597 B2 JP 2719597B2 JP 63229426 A JP63229426 A JP 63229426A JP 22942688 A JP22942688 A JP 22942688A JP 2719597 B2 JP2719597 B2 JP 2719597B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- thin film
- film transistor
- forming
- silicon thin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05005—Structure
- H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01024—Chromium [Cr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01042—Molybdenum [Mo]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01073—Tantalum [Ta]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Thin Film Transistor (AREA)
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、液晶表示器等に用いられるアクティブマト
リクスシリコン薄膜トランジスタ基板の製造方法に関す
るものである。Description: TECHNICAL FIELD The present invention relates to a method for manufacturing an active matrix silicon thin film transistor substrate used for a liquid crystal display or the like.
［従来の技術］ 第３図はアクティブマトリクス型液晶表示器に用いら
れるシリコン薄膜トランジスタを示したもものである。[Prior Art] FIG. 3 shows a silicon thin film transistor used for an active matrix type liquid crystal display.
同図において１は基板、2bはCr（クロム）、Mo（モリ
ブデン）、Ta（タンタル）等を用いたゲート電極、３は
ゲート絶縁層、４は真性シリコン層、5aおよび5bはドナ
ーあるいはアクセプタとなる不純物を含んだ不純物シリ
コン層によるソース電極およびドレイン電極、６および
6bは、ITO（Indium Tin Oxide）等により形成されたソ
ース配線および表示電極、７は保護絶縁層、8bはシリコ
ン層４のチャネル形成部に入射する光を遮断するため、
Al（アルミニウム）等により形成された遮光膜である。In the figure, 1 is a substrate, 2b is a gate electrode using Cr (chromium), Mo (molybdenum), Ta (tantalum) or the like, 3 is a gate insulating layer, 4 is an intrinsic silicon layer, 5a and 5b are donors or acceptors. And drain electrodes made of an impurity silicon layer containing impurities
6b is a source wiring and a display electrode formed of ITO (Indium Tin Oxide) or the like, 7 is a protective insulating layer, and 8b is a light shielding element for blocking light incident on a channel forming portion of the silicon layer 4.
A light-shielding film formed of Al (aluminum) or the like.
ところで、アクティブマトリクスシリコン薄膜トラン
ジスタでは、ソース配線およびゲート配線と外部回路と
の接続が必要である。接続方法としては、外部回路を集
積化したIC（インテグレイティド サーキッツ）をアク
ティブマトリクス基板上に実装し、上記ICと上記ソース
配線およびゲート配線をワイヤボンディング法により接
続したものが提案されている。Incidentally, in an active matrix silicon thin film transistor, connection between a source wiring and a gate wiring and an external circuit is required. As a connection method, there has been proposed a method in which an integrated circuit (IC) in which external circuits are integrated is mounted on an active matrix substrate, and the IC and the source wiring and the gate wiring are connected by a wire bonding method.
第４図は、上記ワイヤボンディング法を用いて接続を
行うときのソース配線端子部を示した従来例である。FIG. 4 is a conventional example showing a source wiring terminal portion when a connection is made using the wire bonding method.
同図において、１は基板、２はゲート電極と同一材料
（Cr、Mo、Ta等）を用いて形成され、後述のソース配線
を接続する接続電極、３はゲート絶縁層、４は真性シリ
コン層、５は不純物シリコン層、６はITO等を用いたソ
ース配線、７は保護絶縁層である。In the figure, 1 is a substrate, 2 is formed using the same material (Cr, Mo, Ta, etc.) as a gate electrode, a connection electrode for connecting a source wiring described later, 3 is a gate insulating layer, 4 is an intrinsic silicon layer Reference numeral 5 denotes an impurity silicon layer, reference numeral 6 denotes a source wiring using ITO or the like, and reference numeral 7 denotes a protective insulating layer.
従来、上記接続電極２の端部2Cで、外部回路のリード
線とのワイヤボンディングを行い、外部回路とソース配
線６との接続を行っていた。Conventionally, at the end 2C of the connection electrode 2, wire bonding with a lead wire of an external circuit is performed to connect the external circuit to the source wiring 6.
［解決しようとする課題］ ワイヤボンディングを行う上記接続電極２は、ゲート
電極と同一材料、すなわちCr、Mo、Ta等の高融点金属で
形成されているため、ボンディングの電気的、機械的信
頼性に難点があり、特に長期信頼性に問題があった。[Problem to be Solved] Since the connection electrode 2 for performing wire bonding is formed of the same material as the gate electrode, that is, a high melting point metal such as Cr, Mo, and Ta, the electrical and mechanical reliability of the bonding is improved. In particular, there was a problem with long-term reliability.
本発明の目的は、ワイヤボンディングに対する信頼性
を高くすることが可能なアクティブマトリクスシリコン
薄膜トランジスタ基板の製造方法を提供することであ
る。An object of the present invention is to provide a method of manufacturing an active matrix silicon thin film transistor substrate that can increase the reliability of wire bonding.
［課題を解決するための手段］ 本発明におけるアクティブマトリクスシリコン薄膜ト
ランジスタ基板の一の製造方法は、基板の主面側にゲー
ト電極と所定の接続電極とを同時に形成する工程と、ゲ
ート絶縁層を形成する工程と、真性シリコン層、ドナー
またはアクセプタとなる不純物を含んだ不純物シリコン
層を選択的に形成してソース電極、ドレイン電極を形成
する工程と、上記接続電極上で上記接続電極に接続され
るソース配線を形成する工程と、保護絶縁層を形成する
工程と、上記接続電極上で上記接続電極に接続され外部
回路に対する接続端子となる端子電極とシリコン薄膜ト
ランジスタへの入射光を遮蔽するための遮光膜とを同一
の導電材料にて同時に形成する工程とを有する。[Means for Solving the Problems] According to one method of manufacturing an active matrix silicon thin film transistor substrate of the present invention, a step of simultaneously forming a gate electrode and a predetermined connection electrode on a main surface side of the substrate; Forming a source electrode and a drain electrode by selectively forming an intrinsic silicon layer, an impurity silicon layer containing an impurity serving as a donor or an acceptor, and connecting to the connection electrode on the connection electrode A step of forming a source wiring, a step of forming a protective insulating layer, and a light-shielding portion for shielding incident light to a silicon thin film transistor and a terminal electrode connected to the connection electrode on the connection electrode and serving as a connection terminal for an external circuit. Simultaneously forming a film with the same conductive material.
［実施例］ 以下、図面に基き本発明における一実施例の説明を行
う。Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
第１図は本発明におけるアクティブマトリクスシリコ
ン薄膜トランジスタの製造工程を示したものである。以
下、同図（ａ）〜（ｄ）に従い製造工程の説明を行う。FIG. 1 shows a manufacturing process of an active matrix silicon thin film transistor according to the present invention. Hereinafter, the manufacturing process will be described with reference to FIGS.
（ａ）基板１上にCr、Mo、Ta等の高融点金属を堆積し、
ゲート電極（図示せず。）と同時に接続電極２を形成
し、引続き窒化シリコンまたは酸化シリコンを用いたゲ
ート絶縁層３、非晶質シリコンを用いた真性シリコン層
４、および非晶質シリコン中に、ドナーあるいはアクセ
プタとのる不純物を含んだ不純物シリコン層５を、基板
１の周辺部を覆うようなメタルマスクを用いて選択的に
堆積する。(A) depositing a high melting point metal such as Cr, Mo, Ta on the substrate 1;
A connection electrode 2 is formed at the same time as the gate electrode (not shown). Subsequently, a gate insulating layer 3 using silicon nitride or silicon oxide, an intrinsic silicon layer 4 using amorphous silicon, and amorphous silicon Then, an impurity silicon layer 5 containing an impurity serving as a donor or an acceptor is selectively deposited using a metal mask that covers a peripheral portion of the substrate 1.
（ｂ）上記真性シリコン層４および不純物シリコン層５
をパターニングした後、ITOをメタルマスクを用いて選
択的に堆積し、このITOをパターニングしてソース配線
６を形成する。このソース配線６は上記接続電極２上で
上記接続電極に接するように形成することが重要であ
る。(B) The intrinsic silicon layer 4 and the impurity silicon layer 5
After patterning, ITO is selectively deposited using a metal mask, and the ITO is patterned to form a source wiring 6. It is important that the source wiring 6 is formed on the connection electrode 2 so as to be in contact with the connection electrode.
（ｃ）窒化シリコンまたは酸化シリコンを用いた保護絶
縁層７をメタルマスクを用いて選択的に堆積する。この
とき保護絶縁層７は、上記ソース配線６の端部を覆うよ
うに形成することが好ましい。(C) A protective insulating layer 7 using silicon nitride or silicon oxide is selectively deposited using a metal mask. At this time, the protective insulating layer 7 is preferably formed so as to cover the end of the source wiring 6.
（ｄ）Alを堆積し、これをパターニングして、薄膜トラ
ンジスタ部の遮光膜（図示せず。）、および外部回路の
リード線をワイヤボンディングする端子電極８を同時に
形成する。(D) Al is deposited and patterned to simultaneously form a light-shielding film (not shown) of the thin film transistor portion and a terminal electrode 8 for wire-bonding a lead wire of an external circuit.
ところで、薄膜トランジスタを駆動するICを上記基板
１上に実装する場合、上記ICの電源ラインを上記基板１
上に形成する必要があるが、上記端子電極８と同時に上
記電源ラインを形成することが製造工程を簡略化でき好
ましい。特に上記端子電極８がAlであれば、電源ライン
の抵抗値を小さくすることができるため、ICの電源ライ
ンとしては好適である。When an IC for driving a thin film transistor is mounted on the substrate 1, the power supply line of the IC is connected to the substrate 1.
Although it is necessary to form the power supply line on the power supply line, it is preferable to form the power supply line simultaneously with the terminal electrode 8 because the manufacturing process can be simplified. In particular, if the terminal electrode 8 is Al, the resistance value of the power supply line can be reduced, so that it is suitable as a power supply line of an IC.
上記端子電極８にはAlが最適であるが、これ以外に
も、例えばAlを主成分とした合金等を用いてもよい。Al is optimal for the terminal electrode 8, but other than this, for example, an alloy containing Al as a main component may be used.
なお、上記製造工程により、第２図に示すようなゲー
タ配線端子部が同時に得られる。同図において、2aは上
記接続電極と同時に形成されるゲート配線、6aは上記ソ
ース配線と同時に形成されるITO等の層、8aは上記端子
電極と同時に形成されるゲート配線の端子電極、他は第
１図と同一のものを示している。By the above manufacturing steps, a gater wiring terminal portion as shown in FIG. 2 is obtained at the same time. In the figure, 2a is a gate wiring formed simultaneously with the connection electrode, 6a is a layer of ITO or the like formed simultaneously with the source wiring, 8a is a terminal electrode of the gate wiring formed simultaneously with the terminal electrode, and the like. The same thing as FIG. 1 is shown.
また、シリコン薄膜トランジスタは、第３図に示すよ
うなものが同時に得られる。Further, as the silicon thin film transistor, one as shown in FIG. 3 can be obtained at the same time.
［発明の効果］ 本発明によれば、接続電極に接続される端子電極を形
成する工程を有し、この端子電極により外部回路との接
続を行うことになるので、ワイヤボンディングに対する
信頼性を大幅に向上させることが可能となる。[Effects of the Invention] According to the present invention, a step of forming a terminal electrode connected to a connection electrode is provided, and connection to an external circuit is performed by the terminal electrode. Can be improved.
また、端子電極とシリコン薄膜トランジスタへの入射
光を遮蔽するための遮光膜とを同一の導電材料で同時に
形成するので、端子電極の製造工程を別途設ける必要が
なく製造工程を増すことなく信頼性を大幅に向上させる
ことが可能となる。In addition, since the terminal electrode and the light-shielding film for shielding incident light to the silicon thin film transistor are formed at the same time with the same conductive material, there is no need to separately provide a terminal electrode manufacturing process, and reliability is increased without increasing the manufacturing process. It is possible to greatly improve.
第１図は本発明における一実施例を示したソース配線端
部の製造工程断面図、第２図は第１図の製造工程により
得られるゲート配線端部の断面図第３図は本発明および
従来例におけるシリコン薄膜トランジスタの断面図、第
４図は従来例におけるソース配線端部の断面図である。 １……基板 ２……接続電極 2b……ゲート電極 ６……ソース配線 ８……端子電極 8b……遮光膜FIG. 1 is a sectional view showing a manufacturing step of an end portion of a source wiring showing one embodiment of the present invention. FIG. 2 is a sectional view showing an end portion of a gate wiring obtained by the manufacturing process shown in FIG. FIG. 4 is a cross-sectional view of a silicon thin film transistor in a conventional example, and FIG. 4 is a cross-sectional view of an end of a source wiring in the conventional example. DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... Connection electrode 2b ... Gate electrode 6 ... Source wiring 8 ... Terminal electrode 8b ... Light shielding film
───────────────────────────────────────────────────── フロントページの続き (72)発明者 斎藤 和則 栃木県那須郡塩原町大字下田野531―１ 日本プレシジョン・サーキッツ株式会 社内 (72)発明者 金澤 由理 東京都墨田区太平４丁目１番１号 株式 会社精工舎内 (56)参考文献 特開 昭63−136571（ＪＰ，Ａ) 実開 昭60−166162（ＪＰ，Ｕ) ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kazunori Saito 531-1 Shimodano, Shiojibara-cho, Nasu-gun, Tochigi Japan Precision Circuits Stock Company In-house (72) Inventor Yuri Kanazawa 4-1-1 Taihei, Sumida-ku, Tokyo No. Inside Seikosha Co., Ltd. (56) References JP-A-63-136571 (JP, A) JP-A-60-166162 (JP, U)
Claims (2)
極とを同時に形成する工程と、 ゲート絶縁層を形成する工程と、 真性シリコン層、ドナーまたはアクセプタとなる不純物
を含んだ不純物シリコン層を選択的に形成してソース電
極、ドレイン電極を形成する工程と、 上記接続電極上で上記接続電極に接続されるソース配線
を形成する工程と、 保護絶縁層を形成する工程と、 上記接続電極上で上記接続電極に接続され外部回路に対
する接続端子となる端子電極とシリコン薄膜トランジス
タへの入射光を遮蔽するための遮光膜とを同一の導電材
料にて同時に形成する工程と を有することを特徴とするアクティブマトリクスシリコ
ン薄膜トランジスタ基板の製造方法。1. A step of simultaneously forming a gate electrode and a predetermined connection electrode on a main surface side of a substrate; a step of forming a gate insulating layer; Forming a source electrode and a drain electrode by selectively forming a layer; forming a source wiring connected to the connection electrode on the connection electrode; forming a protective insulating layer; Simultaneously forming, with the same conductive material, a terminal electrode connected to the connection electrode on the electrode and serving as a connection terminal for an external circuit, and a light-shielding film for shielding light incident on the silicon thin film transistor. Of manufacturing an active matrix silicon thin film transistor substrate.
形成することを特徴とする請求項１に記載のアクティブ
マトリクスシリコン薄膜トランジスタ基板の製造方法。2. The method for manufacturing an active matrix silicon thin film transistor substrate according to claim 1, wherein said terminal electrode is formed of Al (aluminum).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63229426A JP2719597B2 (en) | 1988-09-13 | 1988-09-13 | Method for manufacturing active matrix silicon thin film transistor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63229426A JP2719597B2 (en) | 1988-09-13 | 1988-09-13 | Method for manufacturing active matrix silicon thin film transistor substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0277167A JPH0277167A (en) | 1990-03-16 |
| JP2719597B2 true JP2719597B2 (en) | 1998-02-25 |
Family
ID=16892041
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63229426A Expired - Fee Related JP2719597B2 (en) | 1988-09-13 | 1988-09-13 | Method for manufacturing active matrix silicon thin film transistor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2719597B2 (en) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5958479A (en) * | 1982-09-28 | 1984-04-04 | セイコーエプソン株式会社 | Ic board for active matrix display body |
| JPS5958480A (en) * | 1982-09-28 | 1984-04-04 | セイコーエプソン株式会社 | Ic board for active matrix display body |
| JP2513739Y2 (en) * | 1984-04-11 | 1996-10-09 | キヤノン株式会社 | Thin film transistor substrate |
-
1988
- 1988-09-13 JP JP63229426A patent/JP2719597B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0277167A (en) | 1990-03-16 |
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