JPH01287625A - Top stagger type amorphous silicon thin-film transistor array - Google Patents
Top stagger type amorphous silicon thin-film transistor arrayInfo
- Publication number
- JPH01287625A JPH01287625A JP63118479A JP11847988A JPH01287625A JP H01287625 A JPH01287625 A JP H01287625A JP 63118479 A JP63118479 A JP 63118479A JP 11847988 A JP11847988 A JP 11847988A JP H01287625 A JPH01287625 A JP H01287625A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- gate wiring
- film transistor
- alloy
- amorphous silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910021417 amorphous silicon Inorganic materials 0.000 title claims abstract description 16
- 239000010409 thin film Substances 0.000 title claims abstract description 11
- 230000004888 barrier function Effects 0.000 claims abstract description 19
- 229910001069 Ti alloy Inorganic materials 0.000 claims abstract description 16
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 12
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 5
- 239000010936 titanium Substances 0.000 claims abstract 9
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract 3
- 239000011651 chromium Substances 0.000 claims description 31
- 229910045601 alloy Inorganic materials 0.000 claims description 5
- 239000000956 alloy Substances 0.000 claims description 5
- 229910052804 chromium Inorganic materials 0.000 claims description 4
- 230000008018 melting Effects 0.000 claims description 4
- 238000002844 melting Methods 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910001295 No alloy Inorganic materials 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 55
- 239000000758 substrate Substances 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 238000003491 array Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 101150017724 Crhr1 gene Proteins 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、アクティブマトリクス型液晶表示器等に用い
られるトップスタガー型非晶質シリコン（以下、ａ−ｓ
ｉという。）薄膜トランジスタ（以下、ＴＰＴという。Detailed Description of the Invention [Industrial Application Field] The present invention relates to top staggered amorphous silicon (hereinafter referred to as a-s) used in active matrix liquid crystal displays, etc.
It's called i. ) Thin film transistor (hereinafter referred to as TPT).
）アレイに関するものである。) is related to arrays.
［従来の技術］
近年、アクティブマトリクス型液晶表示器等への応用を
目指して、ａ−ＳｉＴＦＴアレイの研究開発が各所で行
われている。[Prior Art] In recent years, research and development of a-Si TFT arrays has been carried out in various places with the aim of applying them to active matrix liquid crystal displays and the like.
第３図は、上記アクティブマトリクス型液晶表示器に用
いられるａ−ＳｉＴＦＴアレイの一例を示したものであ
る。同図において、１はガラス等を用いた絶縁性基板、
５は層間絶縁層、６はゲ−上絶縁層、７は保護絶縁層、
９は非晶質シリコン層、１０はＡｌ（アルミニウム）を
用いて形成されたゲート電極、１１．１２はそれぞれｎ
型の不純物を適量含んだｎ型シリコン層を用いたソース
電極とドレイン電極、１３はＣｒ（クロム）を用いたソ
ース配線、１４は上記非晶質シリコン層９への入射光を
遮断してＴＦ’Ｔの光電流の増加を抑えるため、上記ソ
ース配線１３と同様にＣｒを用いて形成された遮光層、
１５は透明導電層を用いて形成され、上記ドレイン電極
１２に接続された画素電極、１６は上記画素電極１５と
同様に透明導電層を用いて形成され、上記ソース電極１
１とソース配線１３を接続する接続層である。FIG. 3 shows an example of an a-Si TFT array used in the active matrix liquid crystal display. In the figure, 1 is an insulating substrate made of glass or the like;
5 is an interlayer insulating layer, 6 is an upper insulating layer, 7 is a protective insulating layer,
9 is an amorphous silicon layer, 10 is a gate electrode formed using Al (aluminum), and 11 and 12 are n
A source electrode and a drain electrode are made of an n-type silicon layer containing an appropriate amount of type impurities, 13 is a source wiring made of Cr (chromium), and 14 is a TF by blocking incident light to the amorphous silicon layer 9. In order to suppress the increase in the photocurrent of 'T, a light shielding layer formed using Cr similarly to the source wiring 13,
A pixel electrode 15 is formed using a transparent conductive layer and is connected to the drain electrode 12. A pixel electrode 16 is formed using a transparent conductive layer similarly to the pixel electrode 15 and is connected to the source electrode 1.
This is a connection layer that connects the source wiring 13 and the source wiring 13.
同図に示されるように、ソース電極１１およびドレイン
電極１２とゲート電極１０が、非晶質シリコン層９およ
びゲート絶縁層６を挾んで形成され、しかもソース電極
１１およびドレイン電極１２がゲート電極６よりも絶縁
性基板１側に形成された構造を有するａ−３ｉＴＦＴを
、トップスタガー型ａ−５ｉＴＦＴと呼んでいる。As shown in the figure, a source electrode 11, a drain electrode 12, and a gate electrode 10 are formed sandwiching an amorphous silicon layer 9 and a gate insulating layer 6; An a-3i TFT having a structure formed closer to the insulating substrate 1 is called a top staggered a-5i TFT.
第４図は上記トップスタガー型ａ−３ｉＴＦＴをアレイ
状に設けたトップスタガー型ａ−３ｉＴＦＴアレイのゲ
ート配線と外部回路との接続部であるゲート配線端子付
近を示したちのある。同図において、１は絶縁性基板、
２はＣｒ層、４はＡ１を用いて形成され、各ＴＰＴのゲ
ート電極を接続したゲート配線、５は層間絶縁層、６は
ゲート絶縁層、７は保護絶縁層、８は上記Ｃｒ層２によ
り形成されソース配線（図示せず。）と遮光層（図示せ
ず。）と同時に形成されるゲート配線端子である。FIG. 4 shows the vicinity of the gate wiring terminal, which is the connection portion between the gate wiring and an external circuit of the top staggered A-3i TFT array in which the top staggered A-3i TFTs are arranged in an array. In the figure, 1 is an insulating substrate;
2 is a Cr layer, 4 is a gate wiring formed using A1 and connects the gate electrodes of each TPT, 5 is an interlayer insulating layer, 6 is a gate insulating layer, 7 is a protective insulating layer, and 8 is formed by the above Cr layer 2. A gate wiring terminal is formed simultaneously with a source wiring (not shown) and a light shielding layer (not shown).
ゲート配線端子には、ゲート配線４に用いられるＡｌを
使用することはできないため、ゲート配線４とＣｒ層２
を接続し、Ｃｒ層２によりゲート配線端子８を形成して
いる。Since Al used for the gate wiring 4 cannot be used for the gate wiring terminal, the gate wiring 4 and the Cr layer 2 cannot be used.
The Cr layer 2 forms a gate wiring terminal 8.
［解決しようする課題］
トップスタガー型ａ−ＳｉＴＦＴでは、ゲート配線４を
形成した後、３００’Ｃ程度の温度雰囲気にさらされる
。例えば保護絶縁層は３００”Ｃ程度の温度で形成しな
いと良質のものを得ることができないためである。[Problems to be Solved] In the top staggered a-Si TFT, after the gate wiring 4 is formed, it is exposed to an atmosphere at a temperature of about 300'C. This is because, for example, a protective insulating layer must be formed at a temperature of about 300''C to obtain a good quality one.
ところで、ゲート配線４に使用されるＡｌとゲート配線
端子８に使用されるＣｒは３００’Ｃ程度の温度で容易
にアロイ化し、Ｃｒ Ａ １７が形成される。このＣｒ
Ａ ｌ ７は抵抗率が極めて高い物質であり、ゲート
配線４とＣｒ層２の接続部のシート抵抗は非常に高くな
る。従ってゲート配線端子８からゲート配線４に接続さ
れたａ−３ｉＴＦＴまでの抵抗値は、殆ど上記ゲート配
線４とＣｒ層２の接続部の抵抗値によって決まる高抵抗
値となる。そのために、外部回路からゲート配線端子８
に印加された信号は各ＴＰＴに忠実に伝達されず、回路
動作上大きな問題であった。By the way, Al used for the gate wiring 4 and Cr used for the gate wiring terminal 8 are easily alloyed at a temperature of about 300'C, and Cr A 17 is formed. This Cr
Al 7 is a substance with extremely high resistivity, and the sheet resistance of the connection portion between the gate wiring 4 and the Cr layer 2 becomes extremely high. Therefore, the resistance value from the gate wiring terminal 8 to the a-3i TFT connected to the gate wiring 4 is a high resistance value determined mostly by the resistance value of the connection portion between the gate wiring 4 and the Cr layer 2. Therefore, from the external circuit to the gate wiring terminal 8
The signals applied to the TPTs were not faithfully transmitted to each TPT, which caused a serious problem in circuit operation.
本発明は上記従来の課題に対してなされたものであり、
ゲート配線とＣｒ層の接続部の抵抗値を低く抑えること
を目的としている。The present invention has been made to solve the above-mentioned conventional problems,
The purpose is to keep the resistance value of the connection between the gate wiring and the Cr layer low.
［課題を解決するための手段］
本発明は、ゲート配線がＡｌにより形成されたトップス
タガー型非晶質シリコン薄膜トランジスタアレイにおい
て、ゲート配線端子をＣｒ層により形成し、上記ゲート
配線と上記Ｃｒ層の間に°、ＴｉまたはＴｉ合金による
バリア層を形成することにより上記目的を達成するもの
である。[Means for Solving the Problems] The present invention provides a top staggered amorphous silicon thin film transistor array in which the gate wiring is formed of Al, in which the gate wiring terminal is formed of a Cr layer, and the gate wiring and the Cr layer are connected to each other. The above object is achieved by forming a barrier layer of Ti or Ti alloy between the two.
ゲート配線端子は、Ｃｒ層とＴｉまたはＴｉ合金による
バリア層とにより形成されていてもよい。The gate wiring terminal may be formed of a Cr layer and a barrier layer made of Ti or a Ti alloy.
なお、上記Ｔｉ合金には、ＴｉとＴｉ以外の高融点金属
とによる合金を用いることが好ましい。Note that it is preferable to use an alloy of Ti and a high melting point metal other than Ti as the Ti alloy.
［実施例］
以下、本発明における一実施例を図面に基いて説明する
。第１図において、１はガラス等を用いた絶縁性基板、
２はＣｒ層（１００ｎｍ）、３はＴｉまたはＴｉ合金を
用いたバリア層（１００ｎｍ）、４はＡ１を用いたゲー
ト配線（３００ｎｍ）、５は層間絶縁層、６はゲート絶
縁層、７は保護絶縁層、８は上記ＣｒＨｒにより形成さ
れ、ソース配線（図示せず。）と遮光層（図示せず。）
と同時に形成されるゲート配線端子である。[Example] Hereinafter, an example of the present invention will be described based on the drawings. In FIG. 1, 1 is an insulating substrate made of glass or the like;
2 is a Cr layer (100 nm), 3 is a barrier layer using Ti or Ti alloy (100 nm), 4 is a gate wiring using A1 (300 nm), 5 is an interlayer insulating layer, 6 is a gate insulating layer, 7 is a protection layer The insulating layer 8 is formed of the above-mentioned CrHr, and includes a source wiring (not shown) and a light shielding layer (not shown).
This is a gate wiring terminal formed at the same time.
本例では、ＴｉまたはＴｉ合金を用いたバリア層３をＡ
ｌを用いたゲート配線４とＣｒ層２の間に設けたため、
Ａ１とＣ「の相互拡散がなくなりアロイを形成しないた
め、Ｃｒ層２、バリア層３およびゲート配線４の接続部
で抵抗値が増大することはない。In this example, the barrier layer 3 made of Ti or Ti alloy is
Since it was provided between the gate wiring 4 using l and the Cr layer 2,
Since interdiffusion between A1 and C is eliminated and no alloy is formed, the resistance value does not increase at the connection portion between the Cr layer 2, the barrier layer 3, and the gate wiring 4.
また、ＴｉあるいはＴｉ合金は、応力を吸収しやすい物
質であるため、各層の膜はがれ防止に対して有効に働く
。Furthermore, since Ti or Ti alloy is a substance that easily absorbs stress, it effectively works to prevent the films from peeling off from each layer.
第２図は、本発明における他の実施例を示したものであ
る。FIG. 2 shows another embodiment of the present invention.
本例では、ゲート配線端子８をＣｒ層２とＴｉまたはＴ
ｉ合金によるバリア層３により形成したものであり、上
記実施例と同様の効果を得ることができる。In this example, the gate wiring terminal 8 is connected to the Cr layer 2 and Ti or T.
The barrier layer 3 is formed of i-alloy, and the same effects as in the above embodiment can be obtained.
本例では、外部回路のリード端子との接続を、Ｔｉまた
はＴｉ合金によるバリア層３により行なってもよいが、
ＴｉまたはＴｉ合金は比較的酸化されやすい物質である
ため、バリア層３の厚さを薄くして上記リード端子との
接続が実質的にバリア層３下のＣｒ層８との間で行われ
るようにしてもよい。In this example, the connection with the lead terminal of the external circuit may be made by the barrier layer 3 made of Ti or Ti alloy.
Since Ti or Ti alloy is a substance that is relatively easily oxidized, the thickness of the barrier layer 3 is made thin so that the connection with the lead terminal is substantially made between the Cr layer 8 under the barrier layer 3. You may also do so.
なお、上記バリア層にＴｉ合金を使用する場合、Ｔｉ合
金は、ＴｉとＴｉ以外の高融点金属との合金であること
が好ましい。上記高融点金属としては、Ｍｏ（モリブデ
ン）、Ｗ（タングステン）、Ｔａ（タンタル）等を用い
ることができる。Note that when using a Ti alloy for the barrier layer, the Ti alloy is preferably an alloy of Ti and a high melting point metal other than Ti. As the high melting point metal, Mo (molybdenum), W (tungsten), Ta (tantalum), etc. can be used.
［発明の効果］
本発明によれば、ＴｉまたはＴｉ合金を用いたバリア層
をＡｌを用いたゲート配線とＣｒ層の間に設けたため、
Ａ１とＣｒの相互拡散がなくなり、アロイを形成しない
ため、Ｃｒ層、バリア層およびゲート配線の接続部で抵
抗値が増大することはない。従ってゲート配線端子から
ゲート配線に接続されたａ−３ｉＴＦＴまでの抵抗値を
低抵抗に保つことができるため、ゲート配線端子に印加
される信号を忠実に伝達することができる。[Effects of the Invention] According to the present invention, since a barrier layer using Ti or a Ti alloy is provided between a gate wiring using Al and a Cr layer,
Since mutual diffusion of A1 and Cr is eliminated and no alloy is formed, the resistance value does not increase at the connection portion between the Cr layer, the barrier layer, and the gate wiring. Therefore, the resistance value from the gate wiring terminal to the a-3i TFT connected to the gate wiring can be kept low, so that the signal applied to the gate wiring terminal can be faithfully transmitted.
また、ＴｉあるいはＴｉ合金は応力を吸収しやすいため
、各層の膜はがれ防止に対して有効に働き歩留り向上に
寄与する。Further, since Ti or Ti alloy easily absorbs stress, it effectively works to prevent film peeling of each layer and contributes to improving yield.
第１図は本発明における一実施例を示した断面図、第２
図は本発明における他の実施例を示した断面図、第３図
はトップスタガー型非晶質シリコン薄膜トランジスタア
レイの一部を示した断面図、第４図は従来例を示した断
面図ある。
２・・・Ｃｒ層
３・・・バリア層
４・・・ゲート配線
以 上
出願人 株式会社 精 工 舎FIG. 1 is a sectional view showing one embodiment of the present invention, and FIG.
FIG. 3 is a sectional view showing another embodiment of the present invention, FIG. 3 is a sectional view showing a part of a top staggered amorphous silicon thin film transistor array, and FIG. 4 is a sectional view showing a conventional example. 2...Cr layer 3...Barrier layer 4...Gate wiring and above Applicant Seikosha Co., Ltd.
Claims (3)
れたトップスタガー型非晶質シリコン薄膜トランジスタ
アレイにおいて、ゲート配線端子がＣｒ（クロム）層に
より形成され、上記ゲート配線と上記Ｃｒ層の間にＴｉ
（チタン）またはＴｉ合金によるバリア層が形成されて
いることを特徴とするトップスタガー型非晶質シリコン
薄膜トランジスタアレイ。(1) In a top staggered amorphous silicon thin film transistor array in which the gate wiring is formed of Al (aluminum), the gate wiring terminal is formed of a Cr (chromium) layer, and a Ti layer is formed between the gate wiring and the Cr layer.
1. A top staggered amorphous silicon thin film transistor array, characterized in that a barrier layer is formed of (titanium) or a Ti alloy.
れたトップスタガー型非晶質シリコン薄膜トランジスタ
アレイにおいて、ゲート配線端子がＣｒ（クロム）層と
このＣｒ層上に形成されたＴｉ（チタン）合金によるバ
リア層とにより形成され、上記ゲート配線とＣｒ層の間
に上記バリア層が形成されていることを特徴とするトッ
プスタガー型非晶質シリコン薄膜トランジスタアレイ。(2) In a top staggered amorphous silicon thin film transistor array in which the gate wiring is made of Al (aluminum), the gate wiring terminal is made of a Cr (chromium) layer and a barrier made of a Ti (titanium) alloy formed on the Cr layer. A top staggered amorphous silicon thin film transistor array, characterized in that the barrier layer is formed between the gate wiring and the Cr layer.
の合金であることを特徴とする請求項１または２記載の
トップスタガー型非晶質シリコン薄膜トランジスタアレ
イ。(3) The top staggered amorphous silicon thin film transistor array according to claim 1 or 2, wherein the Ti alloy is an alloy of Ti and a high melting point metal other than Ti.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63118479A JPH01287625A (en) | 1988-05-16 | 1988-05-16 | Top stagger type amorphous silicon thin-film transistor array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63118479A JPH01287625A (en) | 1988-05-16 | 1988-05-16 | Top stagger type amorphous silicon thin-film transistor array |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01287625A true JPH01287625A (en) | 1989-11-20 |
Family
ID=14737694
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63118479A Pending JPH01287625A (en) | 1988-05-16 | 1988-05-16 | Top stagger type amorphous silicon thin-film transistor array |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01287625A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8766448B2 (en) * | 2007-06-25 | 2014-07-01 | Sensor Electronic Technology, Inc. | Chromium/Titanium/Aluminum-based semiconductor device contact |
| US20140308766A1 (en) * | 2007-06-25 | 2014-10-16 | Sensor Electronic Technology, Inc. | Chromium/Titanium/Aluminum-based Semiconductor Device Contact |
| US9514947B2 (en) | 2007-06-25 | 2016-12-06 | Sensor Electronic Technology, Inc. | Chromium/titanium/aluminum-based semiconductor device contact fabrication |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6113227A (en) * | 1984-06-28 | 1986-01-21 | Toshiba Corp | Method for connecting electrode wiring |
| JPS6260240A (en) * | 1985-09-10 | 1987-03-16 | Matsushita Electric Ind Co Ltd | Multilayer interconnection |
-
1988
- 1988-05-16 JP JP63118479A patent/JPH01287625A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6113227A (en) * | 1984-06-28 | 1986-01-21 | Toshiba Corp | Method for connecting electrode wiring |
| JPS6260240A (en) * | 1985-09-10 | 1987-03-16 | Matsushita Electric Ind Co Ltd | Multilayer interconnection |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8766448B2 (en) * | 2007-06-25 | 2014-07-01 | Sensor Electronic Technology, Inc. | Chromium/Titanium/Aluminum-based semiconductor device contact |
| US20140308766A1 (en) * | 2007-06-25 | 2014-10-16 | Sensor Electronic Technology, Inc. | Chromium/Titanium/Aluminum-based Semiconductor Device Contact |
| US9064845B2 (en) * | 2007-06-25 | 2015-06-23 | Sensor Electronic Technology, Inc. | Methods of fabricating a chromium/titanium/aluminum-based semiconductor device contact |
| US9514947B2 (en) | 2007-06-25 | 2016-12-06 | Sensor Electronic Technology, Inc. | Chromium/titanium/aluminum-based semiconductor device contact fabrication |
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