JP2715776B2 - MOS type sample and hold driver circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS type sample and hold driver circuit device comprising MOS transistors used for driving a liquid crystal display element.

[0002]

2. Description of the Related Art A conventional MOS sample-and-hold driver circuit device will be described below. FIG. 4 shows a conventional M
FIG. 3 is a circuit diagram of an OS-type sample-and-hold driver circuit device. In FIG. 4, 1 is an analog signal, 2 is a first switch element, 3 is a control signal for controlling the first switch element 2, and 4 is a hold capacitor that holds the charge flowing through the first switch element 2. Reference numeral 5 denotes a differential amplifier for amplifying the voltage held in the hold capacitor 4 by inputting the voltage to a non-inverting input terminal. Reference numeral 6 denotes a source follower circuit that receives the output of the differential amplifier 5 as an input. Be composed. Reference numeral 9 denotes an external output terminal of the sample hold driver circuit device, and reference numeral 10 denotes a load capacitance of the external output terminal 9.
The output terminal of the source follower circuit 6 is connected to the external output terminal 9 and the inverting input terminal of the differential amplifier 5 to form a buffer circuit having an amplification factor of 1. Reference numeral 11 denotes a constant voltage signal connected to the gate of the PMOS transistor 7;
Is a PMO that fixes the external output terminal 9 to the power supply potential for a certain period.
The S transistor 13 is a control signal connected to the gate of the PMOS transistor 12 and having a phase opposite to that of the control signal 3.

The operation of the conventional MOS sample / hold driver circuit device configured as described above will be described below. However, FIG. 4 shows the case where the control signal 3 of the first switch element 2 is equal to the power supply potential (hereinafter referred to as “
H "), that is," O "
N ", and when the control signal 3 is equal to the ground potential (hereinafter referred to as" L "), the first switch element 2
Is reversed from that in FIG. First, the control signal 3 becomes “H”.
Then, when the first switch element 2 is turned on, the electric charge flows into the hold capacitor 4 via the first switch element 2, so that the potential of the analog signal 1 is sampled. During this period, the control signal 13 is "L" and the PMO
Since the S transistor 12 is ON, the external output terminal 9 is fixed at the power supply potential, and the load capacitance 10 is charged rapidly. Next, the control signal 3 is set to "L" and the control signal 13 is set to "L".
When the first switch element 2 and the PMOS transistor 12 are turned OFF by setting the voltage to H ”, the voltage of the hold capacitor 4 is input to the non-inverting input terminal of the differential amplifier 5. Next, the differential amplifier 5 and the source follower The voltage sampled by the buffer circuit constituted by the circuit 6 is output to the external output terminal 9. The sampled voltage is supplied to the first output terminal 9.
Switch element 2 and PMOS transistor 12
Output continues until N is reached.

[0004]

However, in the above conventional configuration, the external output terminal 9 is still at the power supply potential when the first switch element 2 is switched from ON to OFF and the sampling operation is completed. Since feedback is applied while being connected to the differential amplifier 5, it takes time for the output voltage of the buffer circuit composed of the differential amplifier 5 and the source follower circuit 6 to stabilize, and the response of the output voltage becomes slow. Had.

An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to provide a MOS-type sample-and-hold driver circuit device capable of improving the accuracy of the output voltage and increasing the response speed.

[0006]

In order to achieve this object, a MOS sample-and-hold driver circuit device according to the present invention comprises a sample-and-hold circuit comprising a first switch element, a hold capacitor and a differential amplifier, and an input terminal. Is connected to the output terminal of the differential amplifier, the output terminal is always connected to the inverting input terminal of the differential amplifier, and the first source follower circuit forms a feedback loop. One MOS transistor and a second switch element between the external output terminal and the first source follower circuit.

[0007]

With this configuration, during the period when the load capacitance is charged via the MOS transistor, the feedback loop of the buffer circuit having the amplification factor of 1 can be separated from the external output terminal, and it takes time to stabilize the feedback loop. And a high-speed response of the output voltage can be obtained.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of a MOS type sample and hold driver circuit device according to a first embodiment of the present invention. In FIG. 1, the same parts as those in the conventional example shown in FIG. 14 is the second
Between the contact 15 on the output terminal side of the first source follower circuit 6 and the contact 16 on the side where the PMOS transistor 12 is connected to the external output terminal 9.
N, turn OFF. The control signal 13 is the second switch element 1
4 is controlled.

The operation of the first embodiment configured as described above will be described below. The operation by the first switch element 2, the hold capacitor 4, and the differential amplifier 5 is the same as that of the conventional example shown in FIG. While the first switch element 2 is ON, the second switch element 14 is OFF. At this time, the external output terminal 9 is connected to the PMOS transistor 1
2 raises the voltage to the power supply potential, but does not affect the inverting input terminal of the differential amplifier 5. As a result, feedback is always applied to the differential amplifier 5 and the operation is stabilized as compared with the conventional example, so that a high-speed response of the output voltage can be realized.

Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a circuit diagram of a MOS type sample and hold driver circuit device according to a second embodiment of the present invention. In FIG. 2, the same parts as those in the conventional example shown in FIG. In addition,
14 is a second switch element, 17 is a third switch element controlled by a control signal 19, and is a differential amplifier 5
Between the output terminal of the PMOS transistor 8 and the gate of the PMOS transistor 8
N, turn OFF. 18 is a PMOS transistor,
The drain is connected to the gate of the PMOS transistor 8, the source is connected to the power supply potential, and the gate is connected to the control signal 19.

The operation of the second embodiment configured as described above will be described below. The operation by the first switch element 2, the hold capacitor 4, and the differential amplifier 5 is the same as that of the conventional example shown in FIG. Here, while the first switch element 2 is ON, the second switch element 14 and the third switch element 17 are OFF, and the PMOS transistor 18 is ON. At this time, since the gate of the PMOS transistor 8 is OFF, no current flows through the source follower circuit 6. As described above, according to the second embodiment, the inverting input terminal of the differential amplifier 5 temporarily "
H ", but if the timing of the control signals 13 and 19 is set so that the third switch element 17 is turned on and the PMOS transistor 18 is turned off before the second switch element 14 is turned on, the differential The inverting input terminal of amplifier 5 is "
H "is temporarily prevented from being pulled up, so that the feedback loop stabilizes quickly and the first switch element 2 is turned on.
In the sampling period, no current flows through the source follower circuit 6, so that power consumption can be reduced.

Next, a third embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a circuit diagram of a MOS sample / hold driver circuit device according to a third embodiment of the present invention. 3, the same parts as those in the conventional example shown in FIG. Reference numeral 20 denotes a second source follower circuit, which includes PMOS transistors 21 and 22. The output terminal of the differential amplifier 5 is connected to the gate of the PMOS transistor 22.
The constant voltage signal 23 is applied to the gate of the PMOS transistor 21.
Is connected. 24 is a fourth switch element,
The inverting input terminal of the differential amplifier 5 is switched to and connected to the contact 25 or 26, and is controlled by a control signal 27. The contact 25 is connected to the output terminal of the second source follower circuit 20, and the contact 26 is connected to the external output terminal 9.
7, 8, 12, and 18 are PMOS transistors,
MOS transistors 7 and 8 constitute a first source follower circuit 6, and a constant voltage signal 11 is connected to the gate of the PMOS transistor 7. Reference numeral 17 denotes a third switch element, which is controlled by the control signal 13. The gates of the PMOS transistors 12 and 18 are connected to the control signal 13, and the sources are connected to the power supply potential. The drain of the PMOS transistor 12 is connected to the external output terminal 9, and the drain of the PMOS transistor 18 is connected to the gate of the PMOS transistor 8. The third switch element 17 is inserted between the output terminal of the differential amplifier 5 and the drain of the PMOS transistor 18. 10 is an external output terminal 9
Load capacity.

The operation of the third embodiment configured as described above will be described below. The operation by the first switch element 2, the hold capacitor 4, and the differential amplifier 5 is the same as in the conventional example. Here, the control signals 3 and 13 are signals having phases opposite to each other. First, the first switch element 2
During the sampling period of N, the PMOS transistor 12,
18 is ON, and the third switch element 17 is OFF.
At this time, since the control signal 27 is “H” and the fourth switch element 24 connects the inverting input terminal of the differential amplifier 5 to the contact 25, a feedback loop via the second source follower circuit 20 is formed. Have been. The gate of the PMOS transistor 8 is set to “H” by the PMOS transistor 18.
, The PMOS transistor 8 is OFF, and the external output terminal 9 is connected to the PMOS transistors 7 and 12
To the power supply potential. At this time, the source follower circuit 6 does not operate as a source follower circuit, and no current flows. Next, when the sampling period ends, the first switch element 2 is turned off, the third switch element 17 is turned on, and the PMOS transistors 12 and 18 are turned off.
It becomes FF. On the other hand, the control signal 27 is for a while
At H ”, the fourth switch element 24 keeps the inverting input terminal of the differential amplifier 5 connected to the contact 25. In this state, the feedback loop of the differential amplifier 5 remains connected via the second source follower circuit 20. Until the output voltage of the differential amplifier 5 is PM
The voltage is applied to the gate of the OS transistor 8 and is output from the first source follower circuit 6 to the external output terminal 9. At this point, the feedback loop is not affected by the voltage fluctuation due to the load capacitance 10 of the external output terminal 9. Next, when the charge is charged in the load capacitor 10 and the voltage of the external output terminal 9 is stabilized, the control signal 27 is set to “L” and the inverting input terminal of the differential amplifier 5 is connected to the contact 26 by the switch element 24. The feedback loop of the dynamic amplifier 5 goes through the first source follower circuit 6, and the feedback is directly applied from the external output terminal 9. According to the above third embodiment,
During the sampling period, no current flows through the source follower circuit, power consumption is reduced, the inverting input terminal of the differential amplifier 5 is not temporarily pulled up to the power supply potential, and a feedback loop is established while the load capacitance 10 is being charged. Is always stable because it is not affected by outside.
Therefore, the accuracy of the output voltage and the response speed can be further improved.

In the above-mentioned first, second or third embodiment, one sample hold circuit is used. However, two or more sample hold circuits are arranged in parallel, and another control signal and a switch element are used. Alternatively, the output from the differential amplifier may be switched and input to the source follower circuit.

FIGS. 1 to 3 show a first switch element 2.
3 shows the state of the switch element when the control signal 3 is equal to the power supply potential, that is, "ON". When the control signal 3 is equal to the ground potential, the state of the first switch element 2 is shown in these figures. The opposite is true.

[0016]

As described above, the present invention has a configuration in which the feedback loop of the differential amplifier is disconnected from the external output terminal during the period when the load capacitance is charged via the MOS transistor, thereby stabilizing the feedback loop. An excellent MO that can obtain a high-speed response of the output voltage because no time is required
An S-type sample and hold driver circuit device can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a MOS sample / hold driver circuit device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a MOS sample-and-hold driver circuit device according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a MOS sample / hold driver circuit device according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram of a conventional MOS sample / hold driver circuit device.

[Explanation of symbols]

 2 First switch element 4 Hold capacitance 5 Differential amplifier 6 First source follower circuit 9 External output terminal 12 First MOS transistor 14 Second switch element

Claims (3)

(57) [Claims] A sample-and-hold circuit including a first switch element, a hold capacitor, and a differential amplifier; an input terminal connected to an output terminal of the differential amplifier; and an output terminal connected to an inverting input terminal of the differential amplifier. A first source follower circuit that is always connected to form a feedback loop, a first MOS transistor that fixes an external output terminal to a constant potential for a fixed period, and a second MOS transistor between the external output terminal and the source follower circuit. MOS sample-and-hold driver circuit device comprising: 2. A third switch element inserted between an output terminal of a differential amplifier and an input terminal of a first source follower circuit and opened during a sampling period, and a third switch element which is open during a sampling period. 2. The MOS type sample and hold driver circuit device according to claim 1, further comprising a second MOS transistor for fixing an input terminal voltage of the first source follower circuit to a power supply potential during the period. 3. A first switch element, a hold capacitor and
A sample and hold circuit comprising a differential amplifier and a differential amplifier, wherein the input terminal is connected to the differential amplifier through a third switch element.
Output terminal is connected to the external output terminal
And the output terminal is connected via a fourth switch element.
The feedback loop is connected to the inverting input terminal of the differential amplifier.
A configurable first source follower circuit, an input terminal connected to the output terminal of the differential amplifier,
The terminal is connected to the differential amplifier via the fourth switch element.
A second source connected to the input terminal
A follower circuit, and a first circuit for fixing the external output terminal to a constant potential for a fixed period.
A MOS transistor and a first source during feedback of release of the third switch element;
The terminal voltage is fixed to the power supply potential at the input of the follower circuit.
And the fourth switch element is connected to the first source transistor.
An output terminal of the lower circuit or the second source follower circuit;
One of the output terminals of the road is connected alternatively
MOS-type sample-and-hold driver circuit device according to.