JPH0722258B2 - Switching comparator - Google Patents

Description

The present invention relates to an improvement in a switching comparator, and more particularly to a sample hold circuit using a switching comparator suitable for implementation in an A / D converter. It is about improvement.

[Conventional technology]

As a conventional technique of a sample and hold circuit using a switching comparator, there is USP 4,237,390, which was registered on December 2, 1980, by the invention of National Semiconductor Company, USA. The circuit diagram is shown in FIG. This sample-hold circuit performs a series of operations of a high-speed sampling operation, a high-precision sampling operation and a comparison operation on the signal applied to the input terminal VIN118. The operation will be described below.

First, for high-speed sampling operation, clock D
Becomes high level and the input signal is amplified by the CMOS (127, 128) and applied to the node 113. Next, clock D
Becomes low level and the switch 129 is turned off.

Then, the high precision sampling operation is performed, and the clocks C and E are set to the high level, whereby the input signals are applied to the nodes 113 and 126 (input of CMOS) via the switches 114 and 130. Then switch 111, then switch 11 before comparing with REF.
Each 4 turns off.

Next, the switch 119 is turned on and the comparison operation is performed. At this time, the switch 130 is in the on state, and both the input and output points of the CMOS have the potential of REF. When the comparison operation is completed, the switches 119 and 130 are turned off.

[Problems to be solved by the invention]

In the conventional sample hold circuit described above, both the input and output points of the CMOS are at the REF potential at the end of the comparison operation. Therefore, when one comparison operation is completed and the next high-speed sampling operation is started, the CMOS must start from the operation of amplifying the input signal again. For this reason, the conventional sample hold circuit has a drawback that the high-speed sampling operation takes time.

An object of the present invention is to provide a switching comparator capable of shortening a high speed sampling period.

[Means for Solving the Problems]

In the switching comparator of the present invention, an analog input terminal is connected to a non-inverting input terminal of a differential amplifier capable of obtaining a desired gain in a power supply voltage range, and an inverting input terminal and an output terminal of the differential amplifier are firstly connected. Connected via the switch of the analog input terminal and the non-inverting input terminal of the differential amplifier,
An inverting input terminal of the differential amplifier, an output terminal of the differential amplifier, and a power supply voltage source for supplying a reference voltage to be compared with an analog input are respectively provided through second, third, fourth and fifth switches. Connected to one terminal of the sampling capacitor,
The input terminal of the operational amplifier and the output terminal of the operational amplifier are connected to the other terminal of the sampling capacitor via a sixth switch, and the first, second, third, fourth, fifth and sixth terminals are connected.
Set the time-series control period for the switch to 3
In the first control period, the inverting input terminal and the output terminal of the differential amplifier are short-circuited via the third and fourth switches,
The input terminal and the output terminal of the differential amplifier are connected via the sixth switch, and the inverting input terminal and the output terminal of the differential amplifier are short-circuited via the first switch in the second control period. Then, the analog input terminal and one terminal of the sampling capacitor are short-circuited via the second switch, the input terminal and the output terminal of the operational amplifier are short-circuited via the sixth switch, and the third control In the period, the reference voltage and one terminal of the sampling capacitor are short-circuited via the fifth switch, and the inverting input terminal and the output terminal of the differential amplifier are short-circuited via the first switch. ing.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of a switching comparator of the present invention.

The differential amplifier 5 is a differential amplifier that can obtain a desired gain for an analog input within the power supply voltage range.

The analog input terminal 1 is connected to the non-inverting input 2 of the differential amplifier 5 and the sampling capacitor 8 via the switch 13, and the inverting input 3 of the differential amplifier is connected to the output 4 of the differential amplifier via the switch 10. Further, the sampling capacitor 8 is connected via the switch 12, and the inverting input 3 of the differential amplifier is further connected to the sampling capacitor 8 via the switch 11. The sampling capacitor 8 is connected to a sampling comparison result output terminal 16 via an operational amplifier 9, and the input and output of the operational amplifier 9 are connected via a switch 15.
The reference voltage source 7 is connected to the sampling capacitor 8 via the switch 14. The switches 11 and 12 are controlled by a control signal CLOCK1, the switch 10 is controlled by an inverted signal of the switch control signal CLOCK1, and the switches 13, 14, 15 are controlled by control signals CLOCK4, 3, 2, respectively.

The operation of the switching comparator of the present invention is shown below.

When the control signal CLOCK1 is in the "H" state, the switches 11 and 12 are connected, and the analog input voltage value of the analog input terminal 1 is sampled in the sampling capacitor 8 via the differential amplifier 5 in the voltage follower state. This period is called a high speed sampling period. Next, when the control signal CLOCK4 is in the "H" state, the switch 13 is connected and the analog input voltage value of the analog input terminal 1 is sampled in the sampling capacitor 8. This period is called a high precision sampling period. When the control signal CLOCK1 is in the'L 'state, the inverting input terminal 3 and the output terminal 4 of the differential amplifier 5 are connected via the switch 10 to be in the voltage follower state. Up to the above states, control signal CLOC
The input terminal and the output terminal of the operational amplifier 9 are connected by K2, and one side of the sampling capacitor 8 is fixed at an intermediate level between the highest potential and the lowest potential of the circuit. In this state, the sampling capacitor 8 is charged with the electric charge of the difference between the analog input voltage value and the intermediate level between the highest potential and the lowest potential of the circuit. Next, the control signal CLOCK3 becomes "H" state, and the reference voltage source 7 is connected to the sampling 8 via the switch 14.
This period is called a comparison period. At this time, switches 13 and 15
Are disconnected, the analog input terminal is disconnected from the sampling capacitor 8, and the input terminal and the output terminal of the operational amplifier 9 are disconnected. During this comparison period, since the charge charged in the sampling capacitor 8 is stored in the input terminal of the operational amplifier 9, the analog input voltage value and the voltage of the reference voltage source are changed from the intermediate level between the circuit highest potential and the lowest potential. The value of the difference fluctuates, and the voltage value of the difference is amplified by the operational amplifier 9 and output from the comparison result output terminal 16. That is, the result of comparing the analog input voltage value within the power supply voltage range and the voltage value of the reference voltage source is output from the comparison result output terminal 16.

A typical embodiment realized by a CMOS monolithic integrated circuit of the differential amplifier 5 which can be used for the switching comparator of the present invention and can obtain a desired gain for an analog input within a power supply voltage range is shown in FIG. Show. Here, the n-channel field effect transistor and the P-channel field effect transistor are a three-terminal amplifying element pair, and the three terminals are a gate, a drain, and a source.

The first differential pair formed by the transistors 61 and 62 is the first differential pair.
The second differential pair formed by the transistors 54 and 55 operates as a gain stage for an input voltage from an intermediate level between the power supply terminal 6 and the ground of the first power supply terminal 6 to a level equal to that of the first power supply terminal 6. It operates as a gain stage for the input voltage from the intermediate level between the power supply terminal 6 and the ground to the ground level.

〔The invention's effect〕

As described above, in the present invention, the clock 10 is on and the switches 11 and 12 are off because the clock 3 is at a high level and the switch 14 is on at the same time as the clock 1 is at a low level during the comparison operation. At this time, the differential amplifier amplifies the level of the input terminal, and the potential of its output point 4 is almost the same as that of the input terminal. That is, the amplifier 5 is preparing for the next high-speed sampling during the comparison operation, and the output terminal 4 is already at substantially the same potential as the input terminal at the start of the high-speed sampling operation, so that the high-speed sampling period can be shortened. Becomes

[Brief description of drawings]

FIG. 1 is an embodiment of the present invention, FIG. 2 is a specific circuit diagram of the differential amplifier shown in FIG. 1, and FIG. 3 is a circuit diagram of a conventional sampling and holding circuit. 1 ... Analog input terminal, 2 ... Differential amplifier non-inverting input terminal, 3 ... Differential amplifier inverting input terminal, 4 ... Differential amplifier output terminal, 5 ... Differential amplifier, 6 ... Power supply terminal, 7 ...
… Reference voltage source, 8 …… Sampling capacity, 9 …… Operational amplifier, 10 to 15 …… Switch, 16 …… Comparison result output terminal,
17 …… Analog input high speed sampling section, 18 …… Analog input high precision sampling section, 51 ～ 57 …… MOSP type transistor, 60 ～ 70 …… MOS N type transistor, 81 …… Constant current source, 82 …… Phase compensation Capacity.

Claims (1)

[Claims] 1. An analog input terminal is connected to a non-inverting input terminal of a differential amplifier capable of obtaining a desired gain in a power supply voltage range, and an inverting input terminal and an output terminal of the differential amplifier are first connected.
And a reference voltage to be compared with the analog input terminal and the non-inverting input terminal of the differential amplifier, the inverting input terminal of the differential amplifier, the output terminal of the differential amplifier, and the analog input. And a power supply voltage source for supplying the power supply voltage source to the one terminal of the sampling capacitor via the second, third, fourth and fifth switches, respectively, and the other terminal of the sampling capacitor is connected to the input terminal of the operational amplifier and the first terminal of the sampling capacitor. The output terminal of the operational amplifier is connected through the switch of No. 6, and the time series control periods for the first, second, third, fourth, fifth, and sixth switches are set to three, and In the first control period, the inverting input terminal and the output terminal of the differential amplifier are short-circuited via the third and fourth switches, and the input terminal and the output terminal of the differential amplifier are connected via the sixth switch. Connect the second control period A short circuit between the inverting input terminal and the output terminal of the differential amplifier via the first switch, and a short circuit between the analog input terminal and one terminal of the sampling capacitor via the second switch; The input terminal and the output terminal of the operational amplifier are short-circuited via the sixth switch, and the reference voltage and one terminal of the sampling capacitor are short-circuited via the fifth switch during the third control period. A switching comparator characterized in that the inverting input terminal and the output terminal of the differential amplifier are short-circuited via the switch of 1.