JP2713979B2 - Method of forming insulating film - Google Patents

Method of forming insulating film

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Publication number
JP2713979B2
JP2713979B2 JP11831188A JP11831188A JP2713979B2 JP 2713979 B2 JP2713979 B2 JP 2713979B2 JP 11831188 A JP11831188 A JP 11831188A JP 11831188 A JP11831188 A JP 11831188A JP 2713979 B2 JP2713979 B2 JP 2713979B2
Authority
JP
Japan
Prior art keywords
insulating film
reaction vessel
inp
semiconductor crystal
compound semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP11831188A
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Japanese (ja)
Other versions
JPH01289256A (en
Inventor
浩 石村
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Toshiba Corp
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Toshiba Corp
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Priority to JP11831188A priority Critical patent/JP2713979B2/en
Publication of JPH01289256A publication Critical patent/JPH01289256A/en
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Description

【発明の詳細な説明】 〔発明の目的〕 (産業上の利用分野) この発明は、半導体結晶上への絶縁膜の形成方法に係
り、特に構成元素に燐元素を含む化合物半導体結晶、と
りわけインジウム燐(InP)を用いた絶縁物ゲート電界
効果トランジスタ(以下MISFETと略称する)における絶
縁膜の形成方法に関する。
The present invention relates to a method for forming an insulating film on a semiconductor crystal, and more particularly to a compound semiconductor crystal containing a phosphorus element as a constituent element, particularly indium. The present invention relates to a method for forming an insulating film in an insulator gate field effect transistor (MISFET) using phosphorus (InP).

(従来の技術) 現在マイクロ波半導体素子用材料の主流を占めている
GaAsに対しInPは、電子飽和速度が大きく、かつ、熱伝
導率が大きいなどの特性を備えているため、GaAsを上回
る高周波動作が期待される半導体素子材料として注目を
集めている。
(Prior art) Currently dominant in materials for microwave semiconductor devices
InP has attracted attention as a semiconductor element material that is expected to operate at a higher frequency than GaAs because of its characteristics such as high electron saturation velocity and high thermal conductivity, as compared to GaAs.

InPは、GaAsのように逆方向リーク電流の小さな良好
なショットキ接合を形成することが難しいため、金属−
絶縁膜−半導体接合をゲートとするMISFETが中心に開発
されてきた。InP MISFETを実用化するに当っての最も大
きな問題点の1つは、ドレイン電流が時間と共に変動す
る、いわゆる電流ドリフトが生ずることであった。電流
ドリフトの原因については現在のところ不明な点も多い
が、絶縁膜/InP界面(MIS界面)に存在する界面準位へ
の電子の充放電により、動作チャネルが時間と共に変調
を受けることが主な原因の1つと考えられる。従ってMI
S界面の界面準位密度を極力低減させることが、電流ド
リフトを低減させるための必要条件となる。しかしなが
ら、InPのようなIII−V族化合物半導体は一般にV族元
素が蒸発し易いため、高温で絶縁膜を形成しようとする
と、V族元素である燐(P)の解離により半導体表面の
劣化を招き、InP表面(MIS界面)に欠陥が発生し、この
ことが高密度の界面準位の生成につながる。このような
理由から、例えば200〜300℃以下の低温で絶縁膜を形成
することが通常行なわれている。しかし、絶縁膜の堆積
を低温で行なった場合でも、例えばプラズマ中で堆積さ
せるような方法では、プラズマによる損傷のために表面
欠陥が発生し、やはり界面準位が発生する。
InP is difficult to form a good Schottky junction with small reverse leakage current like GaAs.
MISFETs using an insulating film-semiconductor junction as a gate have been mainly developed. One of the biggest problems in putting InP MISFETs to practical use is that a so-called current drift occurs in which the drain current varies with time. At present, there are many unclear points about the cause of the current drift, but it is mainly that the operating channel is modulated with time by the charge and discharge of electrons to the interface state existing at the insulating film / InP interface (MIS interface). This is considered to be one of the causes. Therefore MI
Reducing the interface state density of the S interface as much as possible is a necessary condition for reducing the current drift. However, since a group III-V compound semiconductor such as InP generally evaporates a group V element easily, when an insulating film is formed at a high temperature, deterioration of a semiconductor surface due to dissociation of phosphorus (P) which is a group V element is caused. As a result, defects are generated on the InP surface (MIS interface), which leads to generation of high-density interface states. For this reason, it is common practice to form an insulating film at a low temperature of, for example, 200 to 300 ° C. or lower. However, even when the insulating film is deposited at a low temperature, for example, in a method in which the insulating film is deposited in plasma, a surface defect occurs due to plasma damage, and an interface level also occurs.

このために、従来の種々の絶縁膜形成方法、例えば熱
酸化法、陽極酸化法、化学的気相堆積(CVD)法、光(C
VD)法等により、種々の絶縁膜、例えばIn2O3膜、陽極
酸化膜、SiO2膜、Al2O3膜、Si3N4膜等を形成することが
試みられてきた。しかしながら、未だ界面準位密度を満
足なレベルに迄低下させ得る絶縁膜は見出せておらず、
従って電流ドリフトが生じないInP MISFETも実現されて
いないのが実状である。
For this purpose, various conventional methods for forming an insulating film, such as a thermal oxidation method, an anodic oxidation method, a chemical vapor deposition (CVD) method, and a light (C
Attempts have been made to form various insulating films, for example, In 2 O 3 films, anodic oxide films, SiO 2 films, Al 2 O 3 films, Si 3 N 4 films, etc. by the VD) method or the like. However, an insulating film that can reduce the interface state density to a satisfactory level has not yet been found.
Therefore, in reality, an InP MISFET in which no current drift occurs has not been realized.

(発明が解決しようとする課題) 以上述べたように、InPのような化合物半導体では、
界面準位密度の小さな、良好な特性を有するMIS界面を
形成し得る絶縁膜、および、その堆積方法が見出せてい
なかった。このため、例えば、InP MISFETに於いて電流
ドリフトの問題が解消できず、InP MISFETを実用化する
上で大きな障害となっていた。
(Problems to be Solved by the Invention) As described above, in a compound semiconductor such as InP,
An insulating film capable of forming an MIS interface having good characteristics with a low interface state density and a deposition method thereof have not been found. For this reason, for example, the problem of current drift cannot be solved in the InP MISFET, which has been a major obstacle in putting the InP MISFET into practical use.

本発明は、上記課題を解説すべくなされたもので、界
面準位密度が小さくPをその構成元素とする化合物半導
体結晶、特にInPを用いたMISFETのゲート絶縁膜に用い
て好適な絶縁膜の形成方法を提供することを目的とする
ものである。
The present invention has been made to explain the above problem, and has a low interface state density, a compound semiconductor crystal having P as a constituent element thereof, and particularly an insulating film suitable for use as a gate insulating film of a MISFET using InP. It is an object to provide a forming method.

〔発明の構成〕[Configuration of the invention]

(課題を解決するための手段) この発明にかかる絶縁膜の形成方法は、反応容器中に
一部構成元素に燐元素を含む化合物半導体結晶基体を保
持させ、前記反応容器とは異なる室で窒素ガラスを励起
して生成された窒素プラズマをホスフィンと共に前記反
応容器中に導入して前記化合物半導体結晶基体上に少な
くとも燐を含む絶縁膜を形成することを特徴とする。ま
た、前記における化合物半導体結晶基体がインジウム
燐、またはガリウム燐のいずれかであることを特徴とす
る。さらに、前記における絶縁膜が燐珪酸ガラスである
ことを特徴とするものである。
(Means for Solving the Problems) According to a method for forming an insulating film according to the present invention, a compound semiconductor crystal substrate containing a phosphorus element as a constituent element is partially held in a reaction vessel, and nitrogen is contained in a chamber different from the reaction vessel. Nitrogen plasma generated by exciting the glass is introduced into the reaction vessel together with phosphine to form an insulating film containing at least phosphorus on the compound semiconductor crystal substrate. Further, the compound semiconductor crystal substrate in the above is one of indium phosphide and gallium phosphide. Further, the insulating film in the above is a phosphor silicate glass.

(作 用) この発明は、窒素プラズマを、絶縁膜堆積を施す反応
容器とは異なる室で生成させることにより、半導体結晶
基体が直接プラズマに曝されるのを防止し、かつ、ここ
で生成された窒素プラズマを前記反応容器中にPH3とと
もに絶縁膜堆積工程の前に導入することにより、半導体
表面が安定化され、MIS界面を形成した際の界面準位密
度が著しく低減されることを見出してなされたものであ
る。さらに、この発明では前記工程の後に、燐を含む絶
縁膜を形成することにより、燐を含む半導体表面から燐
が解離するのを防止するのを防止している。
(Operation) The present invention prevents the semiconductor crystal substrate from being directly exposed to the plasma by generating nitrogen plasma in a chamber different from the reaction vessel for depositing the insulating film, and also generates the nitrogen plasma. By introducing nitrogen plasma into the reaction vessel together with PH 3 before the insulating film deposition step, the semiconductor surface was stabilized, and the interface state density when the MIS interface was formed was found to be significantly reduced. It was done. Further, in the present invention, an insulating film containing phosphorus is formed after the above step, thereby preventing the dissociation of phosphorus from the surface of the semiconductor containing phosphorus.

(実施例) 以下、この発明の一実施例を図面を参照して説明す
る。
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

第1図に一実施例に係る絶縁膜形成装置の概略を断面
図で示す。第1図において、1はマイクロ波励起のプラ
ズマ生成器、2は反応容器、3はInP基板、4はInP基板
を保持するためのサセプタであり、このサセプタ中には
ヒータが埋込まれており、前記InP基板3を所望の温度
に加熱できるようになっている。
FIG. 1 is a sectional view schematically showing an insulating film forming apparatus according to one embodiment. In FIG. 1, 1 is a microwave-excited plasma generator, 2 is a reaction vessel, 3 is an InP substrate, 4 is a susceptor for holding the InP substrate, and a heater is embedded in the susceptor. The InP substrate 3 can be heated to a desired temperature.

前記プラズマ生成器1にはガス導入管が窒素用5と酸
素用6の二系統設けられており切替コック7により切替
可能となっている。生成されたプラズマは、管8を通じ
て反応容器2に導入される。この反応容器2にはシラン
(SiH4)及びホスフィン(PH3)を導入するための導入
管9、10が各々設けられている。さらに、反応容器2の
下方にはガス排出口11が設けられ、その先は排気ポンプ
(図示せず)に連なり、反応容器2中を10-3Torr程度の
減圧状態にすることが可能な構成になっている。
The plasma generator 1 is provided with two gas introduction pipes 5 for nitrogen and 6 for oxygen, and can be switched by a switching cock 7. The generated plasma is introduced into the reaction vessel 2 through the tube 8. The reaction vessel 2 is provided with introduction pipes 9 and 10 for introducing silane (SiH 4 ) and phosphine (PH 3 ), respectively. Further, a gas discharge port 11 is provided below the reaction vessel 2, and the gas discharge port 11 is connected to an exhaust pump (not shown) so that the pressure inside the reaction vessel 2 can be reduced to about 10 −3 Torr. It has become.

このような構成の装置を用い、InP基板上に燐珪酸ガ
ラス膜(以下PSG膜と略称する)を形成する場合につい
て以下に説明する。先ず、InP基板3をサセプタ4上に
載置し、排出口11より反応容器2中を約10-3Torrに迄排
気する。次に、サセプタ4に埋込まれたヒータに通電
し、InP基板3を所定の温度、例えば300℃に加熱する。
なお、加熱時には、導入管10より所定量のPH3を反応容
器2中に流入させる。基板温度が定常値に達した時点
で、導入管5より窒素ガスを所定量流入させる。窒素ガ
スを流入させた後、プラズマ生成器1を作動させ窒素プ
ラズマとなし、管8を通して反応容器2に導入する。な
お、導入管10よりPH3は流し続けておく。この状態を所
定時間保持した後、切替コック7によってプラズマ生成
器1に導入するガスを窒素から所定量の酸素に切替え
る。この際、プラズマ生成器1は作動状態のままでも或
は、一時停止させてもいずれでも良い。本実施例では作
動状態のままで酸素ガスに切替えた。同時にPH3の導入
量を次のPSG膜の組成に合わせて調整し、引続いてSiH4
を導入管9より所定量反応容器2中に流入し、所望の厚
さのPSG膜12を堆積させる。
A case where a phosphosilicate glass film (hereinafter, abbreviated as a PSG film) is formed on an InP substrate by using an apparatus having such a configuration will be described below. First, the InP substrate 3 is placed on the susceptor 4, and the inside of the reaction vessel 2 is evacuated to about 10 −3 Torr from the outlet 11. Next, the heater embedded in the susceptor 4 is energized to heat the InP substrate 3 to a predetermined temperature, for example, 300 ° C.
At the time of heating, a predetermined amount of PH 3 is allowed to flow into the reaction vessel 2 from the introduction pipe 10. When the substrate temperature reaches a steady value, a predetermined amount of nitrogen gas is introduced from the introduction pipe 5. After flowing the nitrogen gas, the plasma generator 1 is operated to generate nitrogen plasma, and is introduced into the reaction vessel 2 through the pipe 8. Note that PH 3 is kept flowing from the introduction pipe 10. After maintaining this state for a predetermined time, the gas introduced into the plasma generator 1 is switched from nitrogen to a predetermined amount of oxygen by the switching cock 7. At this time, the plasma generator 1 may be kept operating or temporarily stopped. In this embodiment, the operating state is changed to oxygen gas. The introduction amount of PH 3 was adjusted to the composition of the next PSG film simultaneously, SiH 4 and subsequently
Flows into the reaction vessel 2 through the introduction pipe 9 to deposit a PSG film 12 having a desired thickness.

このように形成したPSG膜の比抵抗、及び、絶縁破壊
電界強度は膜厚が600Åの場合で、各々1×1013Ω−c
m、6×106V/cmであった。これはMISFET用のゲート絶縁
膜として充分に実用に供し得るものである。また、上述
の方法で形成したMIS界面を有する金属電極面積2×10
-3cm2のMISダイオードを作成し、周波数1MHzに於てC−
V特性を測定(バイアスは+10→0→−10→0→+10V
と掃引した)したところ第2図に示す如く、ヒステリシ
スのほとんどない特性が得られた。なお、第2図のInP
はキャリア濃度5×1015cm-3のn型で、PSG膜厚は約600
Åの場合についてのものである。このことは、本発明の
方法によれば界面準位の少ないMIS界面が形成できるこ
とを示している。
The specific resistance and dielectric breakdown electric field strength of the PSG film thus formed were 1 × 10 13 Ω-c when the film thickness was 600 °.
m, 6 × 10 6 V / cm. This can be sufficiently used practically as a gate insulating film for MISFET. Further, the metal electrode area having the MIS interface formed by the above-described method is 2 × 10
-3 cm 2 MIS diode was fabricated and C-
Measure V characteristics (bias is + 10 → 0 → −10 → 0 → + 10V
As shown in FIG. 2, characteristics with almost no hysteresis were obtained. The InP shown in FIG.
Is an n-type with a carrier concentration of 5 × 10 15 cm −3 and a PSG film thickness of about 600
It is about the case of Å. This indicates that the method of the present invention can form an MIS interface having a low interface level.

さらに、本発明による方法により形成された膜をゲー
ト絶縁膜とするディプレッション型InP MISFETを作成
し、ドレイン電流ドリフトを測定したところ、第3図
に、実線で示す如く、ドリフト量は1mA以内と極めて小
さなものであった。なお、第3図は、ソース・ドレイン
間に5V印加し、ゲートバイアス電圧を時刻(t)=0で
0Vから〜−4V迄ステップ状に変化させた場合のドレイン
電流の時間変化を示したものであり、本発明の効果を明
確にするために、同一形状で形成した常圧CVD法により
形成したSiO2膜をゲート絶縁膜とするInP MISFETの結果
も図中に破線で併せて示した。これでドリフト特性が大
幅に向上したことが判明する。
Further, a depletion-type InP MISFET using the film formed by the method according to the present invention as a gate insulating film was prepared, and the drain current drift was measured. As shown by the solid line in FIG. 3, the drift amount was extremely less than 1 mA. It was small. In FIG. 3, 5 V is applied between the source and the drain, and the gate bias voltage is set at time (t) = 0.
It shows the time change of the drain current when changing stepwise from 0V to -4V.In order to clarify the effect of the present invention, SiO formed by the normal pressure CVD method formed in the same shape is shown. The results of the InP MISFET using the two films as gate insulating films are also shown by broken lines in the figure. This shows that the drift characteristics have been greatly improved.

なお、上記実施例に於ては、絶縁膜がPSG膜の場合に
ついて説明したが、本発明の方法においては、絶縁膜形
成に先立って、反応容器とは異なるプラズマ生成室で発
生させた窒素プラズマをPH3と共に反応容器に導入する
工程(これを工程Aとする)が重要な役割を果してお
り、従って、この絶縁膜はPSG膜に限らず例えば、Pド
ープ窒化シリコン膜或は、窒化燐膜等であっても良い。
また、工程Aと、それに引続く絶縁膜形成の工程は、必
ずしも同一容器内で連続して行なう必要はなく、工程A
の後に他の適当な方法で絶縁膜を形成しても良い。さら
に、上記実施例においては、反応容器中の真空度として
10-3Torr膜形成温度として300℃なる場合について説明
したが、本発明は何らこれらの堆積条件に拘束されるも
のではない。
In the above embodiment, the case where the insulating film is a PSG film has been described, but in the method of the present invention, prior to the formation of the insulating film, the nitrogen plasma generated in a plasma generation chamber different from the reaction vessel is used. a step (referred to as step a) introducing into the reaction vessel together with PH 3 has played an important role, therefore, the insulating film, is not limited PSG film, or a P-doped silicon nitride film, phosphorous nitride film And so on.
Further, the step A and the subsequent step of forming an insulating film need not necessarily be performed continuously in the same container.
After that, an insulating film may be formed by another appropriate method. Further, in the above embodiment, the degree of vacuum in the reaction vessel is
Although the case where the temperature for forming a 10 -3 Torr film is 300 ° C. has been described, the present invention is not limited to these deposition conditions.

〔発明の効果〕〔The invention's effect〕

以上述べたように、この発明には次にあげる顕著な利
点がある。すなわち、MIS界面の界面準位密度を大幅に
低減させ、これをMISFET用のゲート絶縁膜に適用した場
合には、ドレイン電流のドリフト量を従来に比べて大幅
に低減させることが可能になる。
As described above, the present invention has the following remarkable advantages. That is, when the interface state density at the MIS interface is significantly reduced and the MIS interface is applied to the gate insulating film for the MISFET, the drift amount of the drain current can be significantly reduced as compared with the related art.

なお、前記実施例では半導体結晶基体がInPである場
合について述べたが、GaP等燐を含む半導体に適用して
も優れた効果を得ることができる。
In the above embodiment, the case where the semiconductor crystal substrate is InP has been described. However, excellent effects can be obtained by applying the present invention to a semiconductor containing phosphorus such as GaP.

【図面の簡単な説明】[Brief description of the drawings]

第1図は本発明にかかる絶縁膜形成のための装置の概要
を示す断面図、第2図は本発明の方法によって形成した
絶縁膜を用いたMISダイオードのC−V特性を示す線
図、第3図はMISFETのドレイン電流の時間変化につき、
本発明の方法による絶縁膜と、従来の方法による絶縁膜
とについて比較した結果を示す線図である。 1……プラズマ発生器 2……反応容器 3……InP基体 12……PSG膜
FIG. 1 is a sectional view showing an outline of an apparatus for forming an insulating film according to the present invention, FIG. 2 is a diagram showing CV characteristics of an MIS diode using an insulating film formed by the method of the present invention, FIG. 3 shows the time change of the drain current of the MISFET.
FIG. 4 is a diagram showing a result of comparison between an insulating film according to a method of the present invention and an insulating film according to a conventional method. 1 Plasma generator 2 Reactor 3 InP substrate 12 PSG film

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】反応容器中に一部構成元素に燐元素を含む
化合物半導体結晶基体を保持させ、前記反応容器とは異
なる室で窒素ガスを励起して生成された窒素プラズマを
ホスフィンと共に前記反応容器中に導入して前記化合物
半導体結晶基体上に少なくとも燐を含む絶縁膜を形成す
ることを特徴とする絶縁膜の形成方法。
1. A compound semiconductor crystal substrate containing a phosphorus element as a constituent element is partially held in a reaction vessel, and nitrogen gas generated by exciting nitrogen gas in a chamber different from the reaction vessel is produced together with phosphine. A method for forming an insulating film, comprising introducing an insulating film containing at least phosphorus on the compound semiconductor crystal substrate by introducing the insulating film into a container.
【請求項2】化合物半導体結晶基体がインジウム燐、ま
たはガリウム燐のいずれかであることを特徴とする請求
項1記載の絶縁膜の形成方法。
2. The method for forming an insulating film according to claim 1, wherein the compound semiconductor crystal substrate is one of indium phosphide and gallium phosphide.
【請求項3】絶縁膜が燐珪酸ガラスであることを特徴と
する請求項1または請求項2記載の絶縁膜の形成方法。
3. The method according to claim 1, wherein the insulating film is a phosphor silicate glass.
JP11831188A 1988-05-17 1988-05-17 Method of forming insulating film Expired - Lifetime JP2713979B2 (en)

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JP2713979B2 true JP2713979B2 (en) 1998-02-16

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