JPH0823095A - Semiconductor device and production process thereof - Google Patents
Semiconductor device and production process thereofInfo
- Publication number
- JPH0823095A JPH0823095A JP15595794A JP15595794A JPH0823095A JP H0823095 A JPH0823095 A JP H0823095A JP 15595794 A JP15595794 A JP 15595794A JP 15595794 A JP15595794 A JP 15595794A JP H0823095 A JPH0823095 A JP H0823095A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- semiconductor device
- film
- insulating film
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、例えばゲート電極下に
酸化膜を有するＭＯＳ型ＦＥＴ等の半導体装置及びその
製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a MOS FET having an oxide film under a gate electrode and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】近年、フラッシュメモリのような高電界
のかかるデバイスの信頼性を確保するため、ＢＦ2のイ
オン注入により形成したｐ+型ポリシリコンゲートにお
いて、Ｂ（ボロン）がゲート下の酸化膜をつき抜けて、
チャネル領域に影響を及ぼすことを防止するため等の目
的で、ゲート酸化膜を窒化処理する方法が検討されてい
る。2. Description of the Related Art In recent years, in order to ensure the reliability of a device such as a flash memory to which a high electric field is applied, in a p + type polysilicon gate formed by ion implantation of BF 2 , B (boron) is oxidized under the gate. Stick through the membrane,
A method of nitriding the gate oxide film is being studied for the purpose of preventing the channel region from being affected.
【０００３】例えば、「IEEE Electron Device Lett.,v
ol.11 No.7 PP294-296,1990」には、酸化膜をＮＨ3ガス
を用いて窒化し、更に、Ｏ2雰囲気で再酸化する方法が
記載され、また「IEICE Trans.Electron.,vol.E76-C,N
o.4 April,1993」には、酸化膜をＮ2ＯやＮＯを用いて
窒化する方法が記載されている。しかしながら、前者の
方法にあっては、９５０℃以上の高温プロセスが必要
で、この高温処理のために、基板上に既に形成されてい
る不純物領域の不純物が拡散しやすい問題がある。ま
た、窒化処理と同時に水素が取り込まれて膜中トラップ
が発生することを防止するために、別途Ｏ2雰囲気で再
酸化する工程が必要である。更には、この再酸化工程も
１０００℃以上の高温プロセスが必要である。For example, "IEEE Electron Device Lett., V
ol.11 No.7 PP294-296,1990 "describes a method of nitriding an oxide film using NH 3 gas and further reoxidizing it in an O 2 atmosphere, and also" IEICE Trans. Electron., vol. .E76-C, N
4 April, 1993 ”describes a method of nitriding an oxide film with N 2 O or NO. However, the former method requires a high-temperature process at 950 ° C. or higher, and this high-temperature treatment has a problem that impurities in the impurity regions already formed on the substrate are likely to diffuse. In addition, in order to prevent hydrogen from being taken in at the same time as the nitriding treatment to generate traps in the film, a separate step of reoxidizing in an O 2 atmosphere is necessary. Furthermore, this reoxidation step also requires a high temperature process of 1000 ° C. or higher.
【０００４】また、後者の方法にあっては、前者の方法
に比べて、再酸化工程が不必要で、処理温度も若干低く
することができるが、導入される窒素の絶対量が少ない
上に、酸素による反応が同時に起こるために、その反応
制御が難しい。したがって、所望の膜厚が得にくい上に
均一性が劣るという問題がある。そこで、比較的低温プ
ロセスで且つ簡単に酸化膜を窒化処理する方法として、
「１９９４年春 応用物理学会予稿集 29p-ZG-16,29p-ZG
-18」に、ｐ+型ポリシリコンゲートにＮ（窒素）イオン
を注入し、この窒素をゲート酸化膜に偏析させる技術が
記載されている。In the latter method, the reoxidation step is unnecessary and the treatment temperature can be lowered a little as compared with the former method, but the absolute amount of nitrogen introduced is small. However, it is difficult to control the reaction because the reaction by oxygen occurs at the same time. Therefore, there is a problem that it is difficult to obtain a desired film thickness and the uniformity is poor. Therefore, as a method of nitriding the oxide film easily in a relatively low temperature process,
"Spring 1994 Proceedings of the Japan Society of Applied Physics 29p-ZG-16,29p-ZG
-18 "describes a technique of implanting N (nitrogen) ions into a p + -type polysilicon gate and segregating the nitrogen into the gate oxide film.
【０００５】[0005]
【発明が解決しようとする課題】従来例にあっては、窒
素イオンをポリシリコンゲートに注入するために、高い
注入エネルギーを必要とし、このエネルギーによってゲ
ート酸化膜がダメージを受け、デバイスとしての信頼性
を損なう危惧がある。本発明は、半導体装置及びその製
造方法に関し、斯かる問題点を解消することを目的とす
る。In the conventional example, a high implantation energy is required for implanting nitrogen ions into the polysilicon gate, and this energy damages the gate oxide film, resulting in reliability as a device. There is a fear of impairing sex. The present invention relates to a semiconductor device and a method of manufacturing the same, and an object thereof is to solve such a problem.
【０００６】[0006]
【課題を解決するための手段】第１の発明における半導
体装置は、活性窒素を含有した絶縁膜を有するものであ
る。また、第２の発明における半導体装置の製造方法
は、絶縁膜中に活性窒素を導入するものである。The semiconductor device according to the first invention has an insulating film containing active nitrogen. In the method for manufacturing a semiconductor device according to the second invention, active nitrogen is introduced into the insulating film.
【０００７】また、第３の発明における半導体装置の製
造方法は、絶縁膜中に、この絶縁膜を実質的に損傷しな
い程度に低いエネルギーで、窒素イオンを注入するもの
である。また、第４の発明における半導体装置及びその
製造方法は、前記第１乃至第３の発明をゲート絶縁膜に
適用したものである。In the method of manufacturing a semiconductor device according to the third aspect of the invention, nitrogen ions are implanted into the insulating film with low energy that does not substantially damage the insulating film. A semiconductor device and a method of manufacturing the same according to a fourth aspect of the invention apply the first to third aspects of the invention to a gate insulating film.
【０００８】また、第５の発明における半導体装置及び
その製造方法は、前記第１乃至第３の発明を酸化膜又は
ゲート酸化膜に適用したものである。また、第６の発明
における半導体装置は、シリコン基板上に形成され、活
性窒素を含有したシリコン酸化膜をゲート酸化膜とする
ものである。また、第７の発明における半導体装置の製
造方法は、シリコン基板上にシリコン酸化膜を形成し、
この酸化膜中に活性窒素を導入するものである。Further, a semiconductor device and a method of manufacturing the same according to a fifth aspect of the invention are the first to third aspects of the invention applied to an oxide film or a gate oxide film. A semiconductor device according to a sixth aspect of the present invention uses a silicon oxide film formed on a silicon substrate and containing active nitrogen as a gate oxide film. In the method for manufacturing a semiconductor device according to the seventh invention, a silicon oxide film is formed on a silicon substrate,
Active nitrogen is introduced into this oxide film.
【０００９】また、第８の発明における半導体装置の製
造方法は、シリコン基板上にシリコン酸化膜を形成し、
この酸化膜中に、酸化膜を実質的に損傷しない程度に低
いエネルギーで、窒素イオンを注入するものである。ま
た、第９の発明における半導体装置及びその製造方法
は、前記第６乃至第８の発明をｐ型ゲート電極下のゲー
ト酸化膜に適用したものである。Further, in the method of manufacturing a semiconductor device according to the eighth invention, a silicon oxide film is formed on a silicon substrate,
Nitrogen ions are implanted into this oxide film with low energy that does not substantially damage the oxide film. Further, a semiconductor device and a method of manufacturing the same according to a ninth aspect of the invention are the sixth to eighth aspects of the invention applied to a gate oxide film below a p-type gate electrode.
【００１０】[0010]
【作用】即ち、活性窒素（窒素ラジカル、以下、Ｎラジ
カルという）又は窒素イオンを絶縁膜（層間絶縁膜、ゲ
ート酸化膜）に導入し、窒化物層を形成するので、窒化
物層により、ボロン（Ｂ）等の不純物の通過を阻止する
能力が高くなり、ゲート電極等の上層導電層からボロン
（Ｂ）イオン等の不純物が拡散しても、このイオンが、
絶縁膜よりも下層につき抜けることが阻止できる。That is, active nitrogen (nitrogen radical, hereinafter referred to as N radical) or nitrogen ion is introduced into the insulating film (interlayer insulating film, gate oxide film) to form a nitride layer, so that the nitride layer allows boron to be formed. Even if impurities such as boron (B) ions diffuse from the upper conductive layer such as the gate electrode because the ability to block passage of impurities such as (B) becomes high, these ions
The lower layer than the insulating film can be prevented from coming off.
【００１１】また、窒素を導入することにより、シリコ
ン基板と酸化膜との界面が滑らかになるので、前記ゲー
ト電極等の上層導電層膜に大電流が流れても、絶縁膜が
劣化しにくい。また、Ｎラジカルの導入工程や低エネル
ギーでのＮイオンの注入工程は、低温で容易に行え、絶
縁膜が受けるダメージもほとんどない。Further, since the interface between the silicon substrate and the oxide film is smoothed by introducing nitrogen, the insulating film is not easily deteriorated even when a large current flows through the upper conductive layer film such as the gate electrode. Further, the step of introducing N radicals and the step of implanting N ions with low energy can be easily performed at low temperature, and the insulating film is hardly damaged.
【００１２】[0012]
【実施例】本発明の実施例を図１乃至図３に基づいて説
明する。図１において、１はｎ型（１００）シリコン基
板であり、４〜８Ω・ｃｍの比抵抗を有する。２は前記
Ｓｉ基板１の表面に、このＳｉ基板１を８５０℃の温度
でパイロ酸化することによって形成されたシリコン酸化
膜であり、８ｎｍの膜厚を有する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. In FIG. 1, reference numeral 1 denotes an n-type (100) silicon substrate, which has a specific resistance of 4 to 8 Ω · cm. A silicon oxide film 2 is formed on the surface of the Si substrate 1 by pyrooxidizing the Si substrate 1 at a temperature of 850 ° C. and has a film thickness of 8 nm.
【００１３】そして、前記Ｓｉ酸化膜２内にＮラジカル
３・・を導入する。このＮラジカルの導入装置は、例え
ば、特開平３−１５６９１９号公報に記載されている装
置を用いる。即ち、図３に示す通り、装置はガス解離室
４と試料室５とから構成され、これらは石英からなる輸
送パイプ６により接続されている。前記ガス解離室４に
はガス導入口７と導波管８とが設けられ、前記試料室５
にはガス排出口９と試料台１０とが設けられている。Then, N radicals 3 ... Are introduced into the Si oxide film 2. As the N radical introduction device, for example, the device described in JP-A-3-156919 is used. That is, as shown in FIG. 3, the apparatus comprises a gas dissociation chamber 4 and a sample chamber 5, which are connected by a transportation pipe 6 made of quartz. The gas dissociation chamber 4 is provided with a gas inlet 7 and a waveguide 8, and the sample chamber 5
A gas outlet 9 and a sample table 10 are provided in the.
【００１４】このような構成において、試料室１０内を
１ｍTorr以下の圧力に排気した後、窒素ガスを例えば流
量５l(リットル)/min、圧力３Torrの条件で前記ガス導入口
７からガス解離室４内に導入し、導波管８からマイクロ
波電界（マイクロ波パワー：１ｋｗ）を印加して解離室
４内の窒素ガスを放電、解離させて、窒素プラズマ１１
を発生させる。In such a structure, after the sample chamber 10 is evacuated to a pressure of 1 mTorr or less, nitrogen gas is introduced from the gas inlet 7 to the gas dissociation chamber 4 under the conditions of a flow rate of 5 l (liter) / min and a pressure of 3 Torr. And a microwave electric field (microwave power: 1 kw) is applied from the waveguide 8 to discharge and dissociate the nitrogen gas in the dissociation chamber 4, and the nitrogen plasma 11
Generate.
【００１５】この際に生成される長寿命のＮラジカルを
輸送パイプ６から試料室５に導き、前記試料台１０の上
に設置されたＳｉ基板１の表面（Ｓｉ酸化膜２）をＮラ
ジカルに晒す。すると、Ｎラジカルが前記Ｓｉ酸化膜２
内に導入される。ここで、前記試料室５はプラズマ発生
部と離れているので、試料室５内の温度（基板温度）は
比較的低温に設定できる（本実施例では基板温度を２５
０℃に設定した）。即ち、Ｎラジカルの導入作業は低温
プロセスで行うことができる。また、Ｎラジカルの導入
は、高エネルギーでＮイオンをＳｉ酸化膜２に打ち込む
ものでもないので、酸化膜２がダメージを受けにくい。The long-lived N radicals generated at this time are guided from the transport pipe 6 to the sample chamber 5, and the surface of the Si substrate 1 (Si oxide film 2) placed on the sample table 10 is converted into N radicals. Expose. Then, the N radicals are transferred to the Si oxide film 2
Introduced within. Here, since the sample chamber 5 is separated from the plasma generating part, the temperature (substrate temperature) in the sample chamber 5 can be set to a relatively low temperature (the substrate temperature is 25 in this embodiment).
Set to 0 ° C). That is, the work of introducing the N radicals can be performed in a low temperature process. Further, since the introduction of N radicals does not drive N ions into the Si oxide film 2 with high energy, the oxide film 2 is less likely to be damaged.
【００１６】その後、図２に示す通り、前記Ｓｉ酸化膜
２の上に、通常の減圧ＣＶＤ法により、温度６２０℃の
条件下で、（ボロン）Ｂイオンがドープされたポリシリ
コン膜１２を２００ｎｍ堆積した後、８００℃〜８５０
℃の温度で熱処理し、デバイスを完成させる。このよう
なデバイスは、前記Ｓｉ酸化膜２をゲート酸化膜とし、
前記ドープされたポリシリコン膜１２をゲート電極とし
て、ＭＯＳ−ＦＥＴに適用できる。Thereafter, as shown in FIG. 2, a 200 nm thick polysilicon film 12 doped with (boron) B ions is formed on the Si oxide film 2 by a normal low pressure CVD method at a temperature of 620 ° C. 800 ℃ ~ 850 after deposition
Heat treatment is performed at a temperature of ° C to complete the device. In such a device, the Si oxide film 2 is used as a gate oxide film,
The doped polysilicon film 12 can be applied to a MOS-FET as a gate electrode.
【００１７】以上のように作成したデバイスを本出願の
発明者により定電流ストレス(10mA/cm2)でのＴＤＤＢ評
価を行った結果、酸化膜のダメージによるＱBDの低下は
見られなかった。また、ポリシリコン膜１２にドープさ
れているＢイオンが酸化膜をつき抜ける現象も見られな
かった。ここで、ＴＤＤＢ評価とＱBD測定について以下
に説明する。As a result of TDDB evaluation of the device manufactured as described above under constant current stress (10 mA / cm 2 ) by the inventor of the present application, no decrease in QBD due to oxide film damage was observed. Further, the phenomenon that the B ions doped in the polysilicon film 12 penetrate through the oxide film was not observed. Here, TDDB evaluation and QBD measurement will be described below.
【００１８】絶縁膜は、ある一定の電圧を印加し続ける
と、ある時間が経過した後、絶縁破壊を生じる。この絶
縁破壊に至る時間は絶縁膜に加えられる電界強度の関数
である。これが経時的絶縁破壊現象、即ち、ＴＤＤＢ(T
ime-Dependent DielectricBreakdown)と呼ばれる。ＱBD
（破壊に至るまでに酸化膜を流れた電荷量）は、種々の
条件でイオン注入を行った（ポリシリコン膜等の）アン
テナキャパシタに定電流ストレス（１０〜２５ｍＡ／ｃ
ｍ2）を印加したＴＤＤＢ測定から５０％破壊に至るま
での時間を求め、次式から計算できる。When a certain constant voltage is continuously applied to the insulating film, dielectric breakdown occurs after a certain period of time. The time to this breakdown is a function of the electric field strength applied to the insulating film. This is a dielectric breakdown phenomenon over time, that is, TDDB (T
ime-Dependent Dielectric Breakdown). QBD
The constant current stress (10 to 25 mA / c) was applied to the antenna capacitor (polysilicon film or the like) which was ion-implanted under various conditions (the amount of electric charge flowing through the oxide film until breakdown).
The time from the TDDB measurement with m 2 ) applied to 50% breakdown can be obtained and calculated from the following equation.
【００１９】ＱBD＝ｉst×ｔbd ・・・（１） ｉst：ストレス電流、ｔbd：５０％破壊に至るまでの時
間 次に、本発明の別例を以下に説明する。前記実施例にお
いて、Ｓｉ酸化膜２にＮラジカルを導入する工程に代え
て、この酸化膜２がダメージを受けない程度（ダメージ
がゼロという意味ではなく、若干のダメージがあって
も、特性上、酸化膜２が半導体デバイスに適用できる程
度であればよい）の低エネルギーでＮイオンを注入する
（例えば、図１の如く膜厚８ｎｍの酸化膜２であれば、
エネルギー電圧は１．０ｋｅＶ以下が望ましい、もちろ
ん、酸化膜の膜厚や質に応じてエネルギー電圧の上限は
変動する）。QBD = ist × tbd (1) ist: stress current, tbd: time until 50% breakdown Next, another example of the present invention will be described. In the above-described embodiment, instead of the step of introducing N radicals into the Si oxide film 2, the oxide film 2 is not damaged (this does not mean that the damage is zero; N ions are implanted with low energy such that the oxide film 2 can be applied to a semiconductor device (for example, if the oxide film 2 is 8 nm thick as shown in FIG. 1,
The energy voltage is preferably 1.0 keV or less, of course, the upper limit of the energy voltage varies depending on the film thickness and quality of the oxide film).
【００２０】低エネルギー注入にはイオンシャワードー
ピング装置を用いる。このように低エネルギーで注入さ
れたＮイオンも、前記Ｎラジカルと同様の働きをする。
尚、以上の実施例においては、酸化膜をＳｉ基板上に形
成し、その上に導電性のポリシリコン膜を形成するとい
うＭＯＳ構造を例として説明したが、単なる層間絶縁膜
としての酸化膜に、Ｎラジカル導入や低エネルギーでの
Ｎイオン注入を行ってもよい。An ion shower doping apparatus is used for low energy implantation. Thus, the N ions implanted with low energy also have the same function as the N radicals.
In the above embodiments, the MOS structure in which the oxide film is formed on the Si substrate and the conductive polysilicon film is formed on the oxide film is explained as an example. , N radical introduction or low energy N ion implantation may be performed.
【００２１】[0021]
【発明の効果】本発明における半導体装置にあっては、
信頼性及び絶縁効果の高い絶縁膜を有するので、商品的
価値の非常に高いものである。また、本発明における半
導体装置の製造方法にあっては、比較的低温のプロセス
で簡単に、ダメージのほとんどない良質の絶縁膜を得る
ことができ、商品的価値の高い半導体装置を得るのに非
常に有益なものである。According to the semiconductor device of the present invention,
Since it has an insulating film with high reliability and high insulating effect, it has a very high commercial value. Further, in the method of manufacturing a semiconductor device according to the present invention, it is possible to easily obtain a high-quality insulating film with almost no damage by a relatively low temperature process, which is very useful for obtaining a semiconductor device having high commercial value. Be beneficial to.
【図１】本発明の第１の実施例における半導体装置の製
造プロセスを示す基板断面図である。FIG. 1 is a substrate sectional view showing a manufacturing process of a semiconductor device according to a first embodiment of the invention.
【図２】本発明の第１の実施例における半導体装置の製
造プロセスを示す基板断面図である。FIG. 2 is a substrate cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the invention.
【図３】Ｎラジカル導入装置の概略図である。FIG. 3 is a schematic view of an N radical introduction device.
１ Ｓｉ基板 ２ Ｓｉ酸化膜（絶縁膜、ゲート酸化膜） ３ Ｎラジカル（活性窒素） １２ ポリシリコン膜（ｐ型ゲート電極） 1 Si substrate 2 Si oxide film (insulating film, gate oxide film) 3 N radical (active nitrogen) 12 Polysilicon film (p-type gate electrode)
Claims (9)
体装置。1. A semiconductor device having an insulating film containing active nitrogen.
徴とする半導体装置の製造方法。2. A method of manufacturing a semiconductor device, wherein active nitrogen is introduced into the insulating film.
しない程度に低いエネルギーで、窒素イオンを注入した
ことを特徴とする半導体装置の製造方法。3. A method of manufacturing a semiconductor device, wherein nitrogen ions are implanted into the insulating film with energy low enough not to substantially damage the insulating film.
特徴とした請求項１乃至３のいずれかに記載の半導体装
置又は半導体装置の製造方法。4. The semiconductor device or the method of manufacturing a semiconductor device according to claim 1, wherein the insulating film is a gate insulating film.
あることを特徴とした請求項１乃至４のいずれかに記載
の半導体装置又は半導体装置の製造方法。5. The semiconductor device or the method of manufacturing a semiconductor device according to claim 1, wherein the insulating film or the gate insulating film is an oxide film.
含有したシリコン酸化膜をゲート酸化膜とする半導体装
置。6. A semiconductor device which is formed on a silicon substrate and uses a silicon oxide film containing active nitrogen as a gate oxide film.
し、この酸化膜中に活性窒素を導入したことを特徴とす
る半導体装置の製造方法。7. A method of manufacturing a semiconductor device, comprising forming a silicon oxide film on a silicon substrate and introducing active nitrogen into the oxide film.
し、この酸化膜中に、酸化膜を実質的に損傷しない程度
に低いエネルギーで、窒素イオンを注入したことを特徴
とする半導体装置の製造方法。8. A method of manufacturing a semiconductor device, characterized in that a silicon oxide film is formed on a silicon substrate, and nitrogen ions are implanted into the oxide film with energy low enough not to substantially damage the oxide film. Method.
のゲート酸化膜であることを特徴とした請求項６乃至８
のいずれかに記載の半導体装置又は半導体装置の製造方
法。9. The silicon oxide film is a gate oxide film below a p-type gate electrode.
A semiconductor device or a method for manufacturing a semiconductor device according to any one of 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15595794A JPH0823095A (en) | 1994-07-07 | 1994-07-07 | Semiconductor device and production process thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15595794A JPH0823095A (en) | 1994-07-07 | 1994-07-07 | Semiconductor device and production process thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0823095A true JPH0823095A (en) | 1996-01-23 |
Family
ID=15617235
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15595794A Pending JPH0823095A (en) | 1994-07-07 | 1994-07-07 | Semiconductor device and production process thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0823095A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0824268A2 (en) * | 1996-08-12 | 1998-02-18 | Texas Instruments Inc. | Method of fabricating a gate oxide layer |
| JPH11204793A (en) * | 1997-10-24 | 1999-07-30 | Lsi Logic Corp | Electronic device gate oxide hardening method and semiconductor device |
| US6027977A (en) * | 1997-05-14 | 2000-02-22 | Nec Corporation | Method of fabricating semiconductor device with MIS structure |
| JP2002543584A (en) * | 1999-04-22 | 2002-12-17 | アプライド マテリアルズ インコーポレイテッド | Apparatus and method for exposing a substrate to plasma radicals |
| JPWO2004097925A1 (en) * | 2003-04-30 | 2006-07-13 | 富士通株式会社 | Manufacturing method of semiconductor device |
-
1994
- 1994-07-07 JP JP15595794A patent/JPH0823095A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0824268A2 (en) * | 1996-08-12 | 1998-02-18 | Texas Instruments Inc. | Method of fabricating a gate oxide layer |
| EP0824268A3 (en) * | 1996-08-12 | 1999-05-26 | Texas Instruments Inc. | Method of fabricating a gate oxide layer |
| US6040249A (en) * | 1996-08-12 | 2000-03-21 | Texas Instruments Incorporated | Method of improving diffusion barrier properties of gate oxides by applying ions or free radicals of nitrogen in low energy |
| US6027977A (en) * | 1997-05-14 | 2000-02-22 | Nec Corporation | Method of fabricating semiconductor device with MIS structure |
| JPH11204793A (en) * | 1997-10-24 | 1999-07-30 | Lsi Logic Corp | Electronic device gate oxide hardening method and semiconductor device |
| JP2002543584A (en) * | 1999-04-22 | 2002-12-17 | アプライド マテリアルズ インコーポレイテッド | Apparatus and method for exposing a substrate to plasma radicals |
| JPWO2004097925A1 (en) * | 2003-04-30 | 2006-07-13 | 富士通株式会社 | Manufacturing method of semiconductor device |
| JP5121142B2 (en) * | 2003-04-30 | 2013-01-16 | 富士通セミコンダクター株式会社 | Manufacturing method of semiconductor device |
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