JP2695773B2 - Multi CPU control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Purpose of the Invention] (Industrial application field) The present invention relates to a multi-CPU control method capable of effectively using the performance of a microprocessor. (Prior Art) Conventionally, there are several methods for improving system performance by using a plurality of microprocessors from the viewpoint of functional distribution. Many of them operate as a main processor and the other functions as a sub-processor, for example, a function as a dedicated processor such as a screen control. Let us specifically illustrate a graphic system. When displaying graphic data in such a system, it is necessary to develop the dot pattern data in a memory and transfer it to a terminal. Therefore, a function distribution architecture is adopted in which the main processor and the graphic processor are made independent, and the two are mediated by a common memory that exchanges graphic commands. (Problems to be Solved by the Invention) In recent years, in spite of the remarkable improvement in the performance of microprocessors accompanying the progress of semiconductor technology, apart from the main processor in the above-mentioned function distribution system, It is hard to say that the performance of the sub-processor has been fully utilized, and it has not been possible to use it flexibly. The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a multi-CPU control method that realizes flexible usage while effectively utilizing the performance of a processor. [Structure of the Invention] (Means for Solving the Problems) The present invention changes the connection method of two microprocessors in a programmable manner, makes effective use of the performance of the microprocessors, and easily realizes function expansion of the system. Is what you do. Therefore, the components of the conventional system are accessed by a microprocessor connected to the system, a mode control register for setting the operation mode is added, and each bus of the microprocessor is connected to a driver. By connecting the system bus via a // receiver, one of the drivers / receivers is enabled according to the contents set in the mode control register, and one of the microprocessors functions as a main. is there. (Operation) In the above configuration, the mode control register is in the mode of one of the microprocessors in the initial state. Therefore, the driver / receiver connected to the bus of the microprocessor is enabled, and the system is controlled. The main memory and input / output devices connected to the bus can be accessed. At this time, the other CPU operates as a sub-processor and uses its own local memory to perform, for example, screen control. On the other hand, when the microprocessor accesses the mode control register and changes the mode, the other driver / receiver becomes valid,
The microprocessor, which previously functioned as a sub-processor, is connected to the system bus and can access the main memory and input / output devices connected to this bus. The mode control register can be accessed by all microprocessors connected to the system, and both modes can be switched programmably. When different microprocessors are connected to the system according to the method of the present invention, a plurality of operating systems can be operated in one system. (Example) Hereinafter, an example of the present invention is described in detail using drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. For reference, FIG. 2 also shows a conventional example, and the blocks with the same numbers are the same as those in FIG. In the figure, 1 is a processor (CPU1), 2 and 7 are buses, 3
Is a common memory serving as a mailbox between the processor 1 and the processor (CPU 2) 6. Reference numeral 4 denotes a mode control register added according to the present invention, which is configured to be accessible from both the processors 1 and 6. Reference numeral 5 denotes a driver / receiver (D / R) for the bus 2 of the CPU 1. 6 is the other processor (CPU2), 7 is its bus, 8 is CPU2
Local memory for 9 and 10 are a screen control unit and a display device (CRT), respectively. Reference numeral 11 denotes a driver / receiver (D / R) of the bus 7 of the CPU 2. Reference numeral 12 denotes a system bus to which a main memory 13 and an input / output device 14 are connected. Hereinafter, the operation of the embodiment of the present invention will be described in detail in comparison with the conventional example. Conventionally, the CPU 1 operates as a main processor as shown in FIG.
Runs on CPU1. In order to reduce the load on the CPU 1, for example, screen control and the like are left to the dedicated sub-processor CPU 2 (6), and information during that time is performed in the common memory 3.
In recent years, the performance of microprocessors has been significantly improved due to advances in semiconductor technology. is there. FIG. 1 shows the mode control register 4 in the CPU1 mode in the initial state according to the embodiment of the present invention. In this mode, the driver / receiver 5 is enabled and the bus 2 of the CPU1 is activated.
Is connected to the system bus 12 so that the CPU 1 can access the main memory 13 and the input / output device 14. That is, S operates on the processor of CPU1. At that time, the CPU 2 operates as a sub-processor and controls the screen controller 9 using the local memory 8. CPU1
The information of (1) and the information of the CPU 2 (6) are exchanged by the common memory 3. When the mode control register 4 is accessed by the program on the CPU 1 and the mode is changed, the driver /
The receiver 5 becomes invalid. Instead, the driver / receiver 11 becomes effective, and the bus 7 of the CPU 2 becomes the system bus.
12 connected to CPU2 (6) as main memory 13, input / output device
14 will be accessible. In this mode, CPU1
(1) does not operate, and control of all systems is performed by the CPU 2 (6). Mode control register 4 is CPU2 (6)
And both modes can be switched programmably. According to the method of the present invention, if the CPU 1 and the CPU 2 are constituted by different types of microprocessors, two S can be operated by one system. [Effects of the Invention] As described above, according to the method of the present invention, the mode 1 is a function distribution mode in which the CPU 1 operates as the main processor and the CPU 2 operates as the sub-processor.
Regarding the above, by setting the mode in which only the CPU 2 operates as the main processor, if the CPU 1 and the CPU 2 are constituted by different types of microprocessors, two different S can be operated by one system. As described above, by switching modes while aiming at improving system performance by distributing functions, a flexible usage such as moving two Ss becomes possible.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional example. 1,6 processor (CPU), 2,7 CPU bus, 3 common memory, 4 mode control register, 8 local memory,
5, 11: Driver / receiver, 12: System bus.

Claims (1)

(57) [Claims] A system bus; a first processor bus connected to the system bus via first gate means; a first processor connected to the first processor bus; and a second gate connected to the system bus. A second processor bus connected through the means, a second processor connected to the second processor bus, a mode control register in which operation modes of the first and second processors are set, A common memory connected to the first and second processor buses; a local memory connected to the second processor bus; a screen control unit connected to the second processor bus; And a connected input / output device, wherein when the first mode is set in the mode control register, the first processor is connected to the first processor. The system controller is connected to the system bus via the processor bus and the first gate means, operates as a main processor to control the input / output device, and transmits to the second processor via the common memory for the screen control unit. The second processor transfers data, receives the data transmitted from the first processor via the common memory, and controls the screen control unit as a sub-processor of the first processor using the local memory. When a second mode is set in the mode control register, the first processor disconnects the first processor, and the second processor disconnects the second processor bus and the second processor. The main processor is connected to the system bus via gate means and replaces the first processor. A multi-CPU control method wherein the input / output device is controlled as a processor.