JP2694957B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2694957B2 JP2694957B2 JP63004883A JP488388A JP2694957B2 JP 2694957 B2 JP2694957 B2 JP 2694957B2 JP 63004883 A JP63004883 A JP 63004883A JP 488388 A JP488388 A JP 488388A JP 2694957 B2 JP2694957 B2 JP 2694957B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- semiconductor substrate
- layer
- forming
- conductive layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
Description
【発明の詳細な説明】 〔発明の目的〕 （産業上の利用分野） 本発明は、半導体基板表面に不純物導電層を形成する
半導体装置の製造方法に関する。The present invention relates to a method for manufacturing a semiconductor device in which an impurity conductive layer is formed on the surface of a semiconductor substrate.
（従来の技術） 近年、ダイナミックRAM（DRAM）等の半導体集積回路
は、構成素子の微細化による高集積化が著しい。特に１
トランジスタ/1キャパシタ構成をメモリセルを用いたDR
AMにおいては、メモリセルの縮少が重要である。メモリ
セル縮少の際に問題となるのが、十分な読み出しマージ
ンのあるS/N比の確保およびソフトエラーの耐性の点か
らセルキャパシタの蓄積電荷を減少させることが困難な
ことである。従来通りのキャパシタ絶縁膜の薄膜化によ
り蓄積電荷を維持する方法は、現在その絶縁膜が、電界
強度および信頼性の面から薄膜化限界に近付くため、そ
の適応が困難である。これに代わって、第４図に示すよ
うな、キャパシタ領域のシリコン基板４−１の表面に溝
４−５を掘り、この溝側壁部４−６を利用して実効的な
キャパシタ面積を稼ぐ構造（トレンチキャパシタセル）
が、蓄積電荷量を維持する方法として有望視されてい
る。尚、このキャパシタはシリコン基板４−１、キャパ
シタ酸化膜４−２、多結晶シリコン層４−３および不純
物拡散層４−４で構成されている。(Prior Art) In recent years, a semiconductor integrated circuit such as a dynamic RAM (DRAM) has been remarkably highly integrated due to miniaturization of constituent elements. Especially 1
DR using a memory cell with a transistor / capacitor configuration
In AM, the reduction of memory cells is important. A problem when the memory cell is reduced is that it is difficult to reduce the charge stored in the cell capacitor from the viewpoint of securing an S / N ratio with a sufficient read margin and resistance to soft error. The conventional method of maintaining the accumulated charge by thinning the capacitor insulating film is difficult to apply because the insulating film is currently approaching the thinning limit in terms of electric field strength and reliability. Instead of this, as shown in FIG. 4, a trench 4-5 is dug in the surface of the silicon substrate 4-1 in the capacitor region, and the trench sidewalls 4-6 are used to earn an effective capacitor area. (Trench capacitor cell)
However, it is regarded as a promising method for maintaining the accumulated charge amount. The capacitor is composed of a silicon substrate 4-1, a capacitor oxide film 4-2, a polycrystalline silicon layer 4-3 and an impurity diffusion layer 4-4.
トレンチキャパシタセルには、種々の構造のものが考
えられているが、第４図（ａ），（ｂ）に示すような、
溝ま内部に高濃度の不純物拡散層４−４を形成した構造
は、基板４−１側に空乏層が伸びず、1/2Vcc動作をさせ
ることも可能で、キャパシタ絶縁膜に対する負担も軽減
される。この場合、狭く、深い溝内部の垂直な側面に、
不純物を制御性良く、均一なドーピングする方法が重要
になる。Although various structures are considered for the trench capacitor cell, as shown in FIGS. 4 (a) and 4 (b),
In the structure in which the high-concentration impurity diffusion layer 4-4 is formed inside the groove, the depletion layer does not extend to the substrate 4-1 side, 1/2 Vcc operation is possible, and the load on the capacitor insulating film is reduced. It In this case, on the vertical side of the narrow, deep groove,
A method for doping impurities with good controllability and uniformity is important.
従来、集積回路プロセスでは、拡散層形成には、イオ
ン注入法がその特徴である制御性の良さから広く使用さ
れている。しかし、イオン注入法をトレンチ構造へ応用
する場合、第４図（ｅ）に示すように、不純物イオン注
入方向が一定のための、溝の垂直な側壁で注入イオンに
対して影となる部分４−７ができ、不純物の注入されな
い領域が生じる。影になる領域をなくす手段として、注
入傾斜角を変化させたり、シリコン基板を回転させる方
法が考えられる。しかし、いずれの方法も、今後の高集
積化から予想される開口部の狭く、より深い溝への応用
は不可能である。Conventionally, in an integrated circuit process, an ion implantation method has been widely used for forming a diffusion layer because of its excellent controllability. However, when the ion implantation method is applied to the trench structure, as shown in FIG. 4 (e), since the impurity ion implantation direction is constant, a portion 4 which is shaded with respect to the implanted ions on the vertical sidewall of the groove. -7 is produced, and a region where impurities are not injected is produced. As a method of eliminating the shadowed area, a method of changing the implantation inclination angle or rotating the silicon substrate can be considered. However, neither method can be applied to a groove with a narrow opening and a deeper groove, which is expected from high integration in the future.
イオン注入法に代わるトレンチキャパシタの不純物拡
散層の形成法としては、第４図（ｄ）に示すように、固
相からの拡散を利用した方法が考えられる。拡散源とし
て、不純物を添加した多結晶シリコン膜４−３やシリコ
ン酸化膜を溝内部に形成した後、熱拡散によって、シリ
コン基板の表面へ不純物を導入する方法である。この場
合拡散源の形成方法が問題であり、適切な不純物濃度の
均質な膜が、溝４−５の内壁に均一に形成されることが
必要となる。しかし、溝開口部が狭く、深さが深くなる
程、均一な拡散源の形成は困難となる。As a method for forming the impurity diffusion layer of the trench capacitor, which is an alternative to the ion implantation method, a method utilizing diffusion from a solid phase can be considered as shown in FIG. 4 (d). This is a method in which, as a diffusion source, a polycrystalline silicon film 4-3 or a silicon oxide film to which an impurity is added is formed inside the groove, and then the impurity is introduced into the surface of the silicon substrate by thermal diffusion. In this case, the method of forming the diffusion source is a problem, and it is necessary to form a uniform film having an appropriate impurity concentration uniformly on the inner wall of the groove 4-5. However, the narrower the groove opening and the deeper the depth, the more difficult it becomes to form a uniform diffusion source.
例えば、化学気相成長（CVD）法で形成する場合、被
覆性が溝の底部に近づく程悪くなり、薄膜化する。この
薄膜化は不純物の拡散量の不足を招き、溝４−５の上部
と底部とで、不純物拡散層４−４の濃度が均一にならな
くなる。また、不純物を含む溶液を塗布・乾燥させて、
拡散源とする方法では、溝内部の気泡が抜けきらなくな
るおそれがあり、１チップ百万個以上の数の溝の内部に
漏れなく溶液を導入することは、溝の開口幅が狭く、深
さが深くなるにしたがって、困難になると考えられる。
また、固相拡散法では、いずれの場合も、拡散した後、
拡散源を除去する必要がり、プロセス的に複雑なものに
ならざるを得ない。For example, in the case of forming by a chemical vapor deposition (CVD) method, the coverage becomes worse as it gets closer to the bottom of the groove, resulting in a thin film. This thinning causes a shortage of the amount of diffusion of impurities, and the concentration of the impurity diffusion layer 4-4 is not uniform at the top and bottom of the groove 4-5. In addition, by applying and drying a solution containing impurities,
In the method of using a diffusion source, bubbles inside the groove may not be completely exhausted, and it is necessary to introduce the solution into the groove of 1 million chips or more without leaking because the opening width of the groove is narrow and the depth is large. It is thought that the deeper the position becomes, the more difficult it becomes.
In the solid phase diffusion method, in any case, after diffusion,
The diffusion source needs to be removed, and the process becomes complicated.
すなわち従来の不純物導入方法では、上記の点からDR
AMのキャパシタセルに限らず、シリコン表面に形成した
開口部の幅が狭く、深さが深い溝の内壁等に不純物を制
御性良く導入することは、困難である。That is, in the conventional impurity introduction method, DR
Not limited to AM capacitor cells, it is difficult to introduce impurities with good controllability into the inner wall of a groove having a narrow opening and a deep depth formed in the silicon surface.
このため気相状態の不純物元素あるいは不純物元素を
含む化合物から熱分解反応等で、不純物元素あるいは不
純物元素を含む化合物を基板表面と吸着させて、これを
拡散源とする方法が考えられる。しかしながら、この方
法では、溝内部の不純物拡散層の濃度均一性は良いが、
基板表面に形成される自然酸化膜が不純物元素あるいは
不純物元素を含む化合物の吸着を阻害するので、基板中
に拡散する不純物の量は少ない。Therefore, a method of adsorbing the impurity element or the compound containing the impurity element to the substrate surface by a thermal decomposition reaction or the like from the vapor phase impurity element or the compound containing the impurity element and using this as a diffusion source can be considered. However, in this method, although the concentration uniformity of the impurity diffusion layer inside the groove is good,
Since the natural oxide film formed on the substrate surface inhibits the adsorption of the impurity element or the compound containing the impurity element, the amount of impurities diffused in the substrate is small.
（発明が解決しようとする課題） 本発明は、上記の点に鑑みなされたもので、その目的
とするところは、前記の気相状態の不純物元素あるいは
不純物元素を含む化合物を用いて拡散を行なう手法にお
いて、十分な量の不純物が基板中に拡散する方法を提供
することにある。(Problems to be Solved by the Invention) The present invention has been made in view of the above points, and an object thereof is to perform diffusion using the impurity element in the vapor phase state or a compound containing the impurity element. A technique is to provide a method for diffusing a sufficient amount of impurities into a substrate.
（課題を解決するための手段） 本発明の骨子は半導体基板表面にｐあるいはｎ型導電
層を形成するために、必要な元素あるいは該元素を含む
化合物を吸着させる前段階として、一旦該半導体基板表
面に基板と同種の半導体原子を原子数個分の厚さに一様
に堆積させた原子層を形成させ、吸着に対して活性な表
面とすることにより、導電層形成元素あるいは該元素を
含む化合物の吸着効率を高めることにある。(Means for Solving the Problem) The essence of the present invention is to temporarily form a semiconductor substrate by adsorbing a necessary element or a compound containing the element in order to form a p-type or n-type conductive layer on the surface of the semiconductor substrate. A conductive layer forming element or the element containing the element is formed by forming an atomic layer in which semiconductor atoms of the same kind as the substrate are evenly deposited to a thickness of several atoms to form an active surface for adsorption. It is to enhance the adsorption efficiency of the compound.
（作用） 通常の半導体基板表面には、空気中の酸素との反応に
より自然酸化膜が形成されている。この自然酸化膜は、
導電層形成元素あるいは該元素を含む化合物の吸着を阻
害する。空気中でのこの膜の形成は迅速であり、その除
去は困難である。そこで、一旦該半導体基板表面に基板
と同種の半導体原子を原子数個分の厚さに一様に堆積さ
せた原子層を形成させ、自然酸化膜の無い半導体層表面
を作成し、次いで導電層形成元素あるいは該元素を含む
化合物の吸着を行うことにより、それらの吸着効率を増
大させる。(Function) A natural oxide film is formed on a normal semiconductor substrate surface by a reaction with oxygen in the air. This natural oxide film
It inhibits the adsorption of the conductive layer forming element or the compound containing the element. The formation of this film in air is rapid and its removal is difficult. Therefore, an atomic layer is formed by temporarily depositing semiconductor atoms of the same kind as the substrate to a thickness of several atoms on the surface of the semiconductor substrate to form a semiconductor layer surface without a natural oxide film, and then forming a conductive layer. By adsorbing the forming element or the compound containing the element, the adsorption efficiency thereof is increased.
（実施例） 以下の本発明の詳細を図示の実施例によって説明す
る。(Examples) Details of the present invention will be described below with reference to illustrated examples.
導電層を形成する半導体試料としてシリコンを、導電
層を形成させるために吸着させる物質としてPH3を用い
た。まず酸系水溶液により洗浄を行なった比抵抗９〜11
Ω・cmのｐ型（100）面シリコン基板１−１に、温度780
℃、圧力1Torr、100％ SiH4で厚さ約50Åの多結晶シリ
コン層１−３を堆積する（第１図（ａ））。尚、シリコ
ン基板１−１の表面には自然酸化膜１−２ができてい
る。次いで、濃度１％のPH3を15分間導入し、リン
（Ｐ）１−４を吸着させた（第１図（ｂ））。この後窒
素希釈による10％酸素雰囲気、温度1000℃で１時間の熱
処理を行なうことにより、リンによるｎ型導電層１−５
の形成を行なった（第１図（ｃ））。尚、ｎ型導電層１
−５の上には酸化膜１−６が形成される。導電層中のリ
ンの量をシート抵抗測定により評価すると、リンを吸着
する前に多結晶シリコン層堆積を行なっていない従来例
でのシート抵抗値は1kΩ／ロであるのに対して、本実施
例のリンを吸着する前に多結晶シート層堆積を行なった
場合では500Ω／ロと半減し、リンの吸着効率の向上が
うかがえる。Silicon was used as a semiconductor sample for forming the conductive layer, and PH 3 was used as a substance to be adsorbed for forming the conductive layer. First, specific resistance 9 to 11 washed with an acid-based aqueous solution
Ω · cm p-type (100) surface silicon substrate 1-1, temperature 780
A polycrystalline silicon layer 1-3 having a thickness of about 50Å is deposited at 100 ° C, pressure 1 Torr, and 100% SiH 4 (Fig. 1 (a)). A natural oxide film 1-2 is formed on the surface of the silicon substrate 1-1. Then, PH 3 with a concentration of 1% was introduced for 15 minutes to adsorb phosphorus (P) 1-4 (Fig. 1 (b)). After that, a heat treatment is carried out at a temperature of 1000 ° C. for 1 hour in a 10% oxygen atmosphere diluted with nitrogen, whereby the n-type conductive layer 1-5 made of phosphorus is formed.
Was formed (FIG. 1 (c)). The n-type conductive layer 1
An oxide film 1-6 is formed on -5. When the amount of phosphorus in the conductive layer is evaluated by sheet resistance measurement, the sheet resistance value in the conventional example in which the polycrystalline silicon layer is not deposited before adsorbing phosphorus is 1 kΩ / b When the polycrystalline sheet layer is deposited before adsorbing phosphorus as in the example, it is halved to 500 Ω / b, which shows that the adsorption efficiency of phosphorus is improved.
さらに、上記の多結晶シリコン層堆積とPH3導入とい
う工程を、第３図に示すように、くり返し行なうと、第
３図に示した通りに、工程のくり返し回数の増加ととも
にシート抵抗値は減少し、多結晶シリコン層堆積とPH3
導入をくり返すことで、吸着するリンの量がさらに増大
することが判明した。すなわち、シリコン基板２−１の
自然酸化膜２−２の表面に、多結晶シリコン層２−３と
リン吸着層２−４が交互に堆積されている。Further, when the above-mentioned steps of depositing the polycrystalline silicon layer and introducing PH 3 are repeated as shown in FIG. 3, as shown in FIG. 3, the sheet resistance value decreases as the number of times of repeating the step increases. And polycrystalline silicon layer deposition and PH 3
It was found that the amount of phosphorus adsorbed was further increased by repeating the introduction. That is, the polycrystalline silicon layer 2-3 and the phosphorus adsorption layer 2-4 are alternately deposited on the surface of the natural oxide film 2-2 of the silicon substrate 2-1.
上記実施例による方法を用いて、第４図（ａ），
（ｂ）にその平面及び断面を示す様なシリコン基板の溝
内部および主表面に拡散層を形成した場合のMOSキャパ
シタのＣ−Ｖ（容量−電圧）特性を第４図（ｃ）に示
す。第４図（ｃ）において、従来例と上記実施例によっ
て形成されたキャパシタのＣ−Ｖ特性を比較する。従来
例では、第４図（ｄ），（ｅ）に断面を示す様に半導体
基体の溝部に不純物の導入されない領域があるため、そ
の部分で基体が空乏化して、容量が減少する。しかし、
本実施例は、均一に不純物が拡散されるため、容量を保
つことができる。Using the method according to the above embodiment, FIG.
FIG. 4C shows the CV (capacitance-voltage) characteristics of the MOS capacitor in the case where the diffusion layer is formed inside the groove and the main surface of the silicon substrate as shown in the plane and cross section of FIG. In FIG. 4 (c), the CV characteristics of the capacitor formed by the conventional example and the capacitor formed by the above example are compared. In the conventional example, as shown in cross sections in FIGS. 4 (d) and 4 (e), since there is a region where impurities are not introduced in the groove portion of the semiconductor substrate, the substrate is depleted at that portion and the capacitance is reduced. But,
In this embodiment, since the impurities are uniformly diffused, the capacity can be maintained.
本実施例では、MOSキャパシタの場合を説明したが、
その他の表面に開口の狭く且つ深い溝等の形状を有する
半導体基体への不純物導入工程においても発明を用いる
ことにより、均一で制御性の良い不純物拡散層を平坦部
は言うにおよばず溝内部にも形成することができる。In this embodiment, the case of the MOS capacitor has been described, but
By using the invention also in the step of introducing an impurity into a semiconductor substrate having a shape such as a groove having a narrow opening and a deep groove on the other surface, a uniform and well-controlled impurity diffusion layer is formed in the groove as well as in the flat portion. Can also be formed.
本発明によれば、凹形状の溝を有するシリコン基板の
表面に、高集積化に適応した均一で制御性の良い所定の
導電型を与える不純物層を形成することができる。した
がって、例えば、素子領域の微細化と共に表面に形成さ
れる溝のアスペクト比が増々大きくなるのに対応して、
その微細な深い溝の内部への不純物拡散が可能となり、
素子の高集積化及び高速化に有効である。According to the present invention, it is possible to form, on the surface of a silicon substrate having a concave groove, an impurity layer that provides a uniform and controllable predetermined conductivity type suitable for high integration. Therefore, for example, as the aspect ratio of the groove formed on the surface increases with the miniaturization of the element region,
Impurities can be diffused inside the fine deep grooves,
It is effective for high integration and high speed of the device.
第１図は本発明による不純物導入方法の手順を示した工
程図、第２図は本発明の工程をくり返し行なった場合の
試料の断面を示す工程図、第３図は本発明の工程のくり
返し回数とシート抵抗の関係を示した曲線図、第４図は
本発明の実施例の効果をMOSキャパシタのＣ−Ｖ特性に
よって従来例と比較して評価した結果を示す図である。 １−1,2−1,4−１……シリコン基板、 １−2,2−２……自然酸化膜、 １−3,2−3,4−３……多結晶シリコン層、 １−4,2−４……リン吸着層、１−５……ｎ型導電層、 １−６……酸化膜、４−２……キャパシタ酸化膜、 ４−４……不純物拡散層、４−５……溝、４−６……溝
側壁部、 ４−７……影。FIG. 1 is a process diagram showing a procedure of an impurity introduction method according to the present invention, FIG. 2 is a process diagram showing a cross section of a sample when the process of the present invention is repeated, and FIG. 3 is a process repeat of the present invention. FIG. 4 is a curve diagram showing the relationship between the number of times and the sheet resistance, and FIG. 4 is a diagram showing the results of evaluating the effect of the embodiment of the present invention by the CV characteristic of the MOS capacitor in comparison with the conventional example. 1-1,2-1-1,4-1 ... Silicon substrate, 1-2,2-2 ... Natural oxide film, 1-3,2-3,4-3 ... Polycrystalline silicon layer, 1-4 , 2-4 ... Phosphorus adsorption layer, 1-5 ... N-type conductive layer, 1-6 ... Oxide film, 4-2 ... Capacitor oxide film, 4-4 ... Impurity diffusion layer, 4-5 ... ... Groove, 4-6 ... Side wall of groove, 4-7 ... Shadow.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 奥村 勝弥 神奈川県川崎市幸区小向東芝町１ 株式 会社東芝総合研究所内 (56)参考文献 特開 昭57−118633（ＪＰ，Ａ) 特開 昭54−103671（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Katsuya Okumura 1 Komukai Toshiba-cho, Kouki-ku, Kawasaki-shi, Kanagawa Inside Toshiba Research Institute, Inc. (56) Reference JP-A-57-118633 (JP, A) JP-A-SHO 54-103671 (JP, A)
Claims (5)
形成する工程において、一旦該半導体基板表面に、吸着
に対して活性な表面となるように該半導体基板と同種の
半導体原子を原子数個分の厚さに一様に堆積させた原子
層を形成した後、該半導体層上に、ｐあるいはｎ型導電
層を形成するのに必要な元素あるいは該元素を含む化合
物を吸着せしめ、次いで該半導体基板に熱処理を行うこ
とにより、該半導体基板表面に吸着した該元素を含む化
合物から該元素を該半導体基板中に拡散させて、ｐある
いはｎ型導電層を形成することを特徴とする半導体装置
の製造方法。1. In the step of forming a p-type or n-type conductive layer on the surface of a semiconductor substrate, the number of semiconductor atoms of the same kind as that of the semiconductor substrate is once added to the surface of the semiconductor substrate so that the surface becomes active for adsorption. After forming an atomic layer uniformly deposited to a thickness of one piece, an element necessary for forming a p- or n-type conductive layer or a compound containing the element is adsorbed on the semiconductor layer, and then, A semiconductor is characterized in that the semiconductor substrate is heat-treated to diffuse the element from the compound containing the element adsorbed on the surface of the semiconductor substrate into the semiconductor substrate to form a p-type or n-type conductive layer. Device manufacturing method.
面となるように該半導体基板と同種の半導体原子を原子
数個分の厚さに一様に堆積させた原子層を形成する方法
として、該半導体元素を含む化合物ガスの熱、光反応、
ECRまたはマグネトロンを用いたプラズマ反応等の分解
反応による該半導体基板表面への該半導体原子の吸着あ
るいは堆積により行うことを特徴とする請求項１記載の
半導体装置の製造方法。2. A method for forming an atomic layer on the surface of a semiconductor substrate, in which semiconductor atoms of the same kind as the semiconductor substrate are uniformly deposited to a thickness of several atoms so as to be an active surface for adsorption. As heat, photoreaction of a compound gas containing the semiconductor element,
2. The method for manufacturing a semiconductor device according to claim 1, wherein the method is carried out by adsorption or deposition of the semiconductor atoms on the surface of the semiconductor substrate by a decomposition reaction such as plasma reaction using ECR or magnetron.
するのに必要な元素あるいは該元素該元素を含む化合物
を吸着する工程の方法として、該元素を含む化合物ガス
の熱、光反応、ECRまたはマグネトロンを用いたプラズ
マ反応等の分解反応による該半導体層上への該元素の吸
着により行うことを特徴とする請求項１記載の半導体装
置の製造方法。3. A method of adsorbing an element necessary for forming a p-type or n-type conductive layer or a compound containing the element to the semiconductor layer, which comprises heat or photoreaction of a compound gas containing the element. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the element is adsorbed on the semiconductor layer by a decomposition reaction such as plasma reaction using ECR, ECR or magnetron.
するために該半導体基板表面に吸着せしめる物質とし
て、ホウ素あるいはガリウム等の元素あるいは該元素を
含む化合物、ｎ型導電層を形成するため該半導体基板表
面に吸着せしめる物質として、ヒ素、リンあるいはアン
チモン等の元素あるいは該元素を含む化合物とすること
を特徴とする請求項１記載の半導体装置の製造方法。4. Silicon as a semiconductor, an element such as boron or gallium or a compound containing the element as a substance to be adsorbed on the surface of the semiconductor substrate to form a p-type conductive layer, and an n-type conductive layer are formed. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the substance to be adsorbed on the surface of the semiconductor substrate is an element such as arsenic, phosphorus or antimony or a compound containing the element.
面となるように該半導体基板と同種の半導体原子を原子
数個分の厚さに一様に堆積させた原子層を形成した後、
該半導体層に、ｐあるいはｎ型導電層を形成するのに必
要な元素あるいは該元素を含む化合物を吸着せしめると
いう工程を二度以上繰返すことを特徴とする請求項１記
載の半導体装置の製造方法。5. After forming an atomic layer on the surface of a semiconductor substrate by uniformly depositing semiconductor atoms of the same kind as the semiconductor substrate to a thickness of several atoms so as to become an active surface for adsorption. ,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of adsorbing an element or a compound containing the element necessary for forming a p-type or n-type conductive layer is repeated twice or more. .
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63004883A JP2694957B2 (en) | 1988-01-14 | 1988-01-14 | Method for manufacturing semiconductor device |
| KR1019890000349A KR930003859B1 (en) | 1988-01-14 | 1989-01-14 | Manufacturing method of semiconductor device |
| US08/017,449 US5354710A (en) | 1988-01-14 | 1993-02-12 | Method of manufacturing semiconductor devices using an adsorption enhancement layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63004883A JP2694957B2 (en) | 1988-01-14 | 1988-01-14 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01186615A JPH01186615A (en) | 1989-07-26 |
| JP2694957B2 true JP2694957B2 (en) | 1997-12-24 |
Family
ID=11596076
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63004883A Expired - Fee Related JP2694957B2 (en) | 1988-01-14 | 1988-01-14 | Method for manufacturing semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2694957B2 (en) |
| KR (1) | KR930003859B1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100358110C (en) * | 2002-12-20 | 2007-12-26 | 皇家飞利浦电子股份有限公司 | Method of manufacturing a semiconductor device |
| WO2010003928A2 (en) * | 2008-07-06 | 2010-01-14 | Interuniversitair Microelektronica Centrum Vzw (Imec) | Method for doping semiconductor structures and the semiconductor device thereof |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54103671A (en) * | 1978-02-01 | 1979-08-15 | Nec Corp | Production of semiconductor device |
| JPS57118633A (en) * | 1981-01-14 | 1982-07-23 | Toshiba Corp | Manufacture of semiconductor device |
| JPS61127119A (en) * | 1984-11-22 | 1986-06-14 | Sanyo Electric Co Ltd | Method of growing silicon crystal |
| JPS62219915A (en) * | 1986-03-20 | 1987-09-28 | Fuji Electric Co Ltd | Processing device for semiconductor substrate |
| JPH0821552B2 (en) * | 1986-05-12 | 1996-03-04 | ソニー株式会社 | Impurity doping method |
-
1988
- 1988-01-14 JP JP63004883A patent/JP2694957B2/en not_active Expired - Fee Related
-
1989
- 1989-01-14 KR KR1019890000349A patent/KR930003859B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR890012386A (en) | 1989-08-26 |
| KR930003859B1 (en) | 1993-05-14 |
| JPH01186615A (en) | 1989-07-26 |
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