JP2692385B2 - Frequency-DC converter circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency-to-DC converter circuit for converting an input AC signal into a DC signal which changes according to its frequency and outputting the DC signal. .

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram showing the structure of a conventional frequency-to-DC converter circuit of this type disclosed in, for example, Japanese Patent Laid-Open No. 57-160069. In the figure, 1 is a trigger signal circuit, 2 is a one-shot circuit, 3 is a delay circuit, 4 is a bias circuit, 5 is an adder circuit, and 6 is an averaging circuit, which is an AC signal Fi of a frequency fi input by this circuit configuration. Is converted into a DC signal Vo.

Next, the operation will be described with reference to the time chart shown in FIG. It should be noted that (a) to (g) in the figure respectively represent the signal waveforms of the corresponding portions shown in FIG. Also,
The frequency fi of the AC signal Fi fluctuates over a wide range, but the range between the upper limit fmax and the lower limit fmin is set as the conversion target range, and a DC signal that changes according to the input frequency is output within this range.

First, when the AC signal Fi shown in FIG. 4 (a) is input, the trigger signal circuit 1 passes the extremely short time width Tg for each zero point of the AC signal Fi and then the trigger signal FIG.
Is output. This trigger signal (b) is introduced into the one-shot circuit 2 and the delay circuit 3, of which the one-shot circuit 2 has a peak value V and a one-shot signal (c) with a time width T at each rise of the trigger signal (b). Is output. The delay circuit 3 outputs a delay signal (d) having a peak value Vd and a delay time width Td.

The delay time width Td is set by the following equation. Td = 1 / (2 · fmin) >> Tg Further, Vd is set as Vd = 2 · fmin · V · T. Therefore, as shown in the figure, the delay signal (d) is intermittent when the frequency fi of the AC signal Fi is fmin or less, and continues zero output when it is fmin or more.

The delay signal (d) is applied to the peak value V by the bias circuit 4.
The signal is biased to the negative side by d, and the bias signal (e) and the one-shot signal (c) are added by the adder circuit 5 and the added signal
It becomes (f). Then, this addition signal (f) is added to the averaging circuit 6
Are averaged to form an averaged signal (g), which becomes the final output signal as the DC signal Vo.

Here, the average value output is examined as follows for each range of the frequency fi. (1) In the range of fi <fmin, the average value of the one-shot signal (c) is 2 · fi · V · T and the average value of the bias signal (e) is 2 · fi · Vd · Td = 2 · fi · V.・ Because it becomes T,
After all, in this range, the DC signal Vo is always 0. (2) In the range of fmin <fi <fmax, since the average value of the bias signal (e) is Vd = 2 · fmin · V · T, the direct current signal Vo = 2 · (fi−fmin) · V · T. , And a value proportional to the difference from the lower limit frequency. (3) In the range of fi > fmax, the value is the same as the value obtained in (2). However, by setting T = 1 / (2 · fmax) in this range, the DC signal Vo = V-Vd = V
It is constant at (fmax-fmin) / fmax. FIG. 5 illustrates the above characteristics.

[0008]

Since the conventional frequency-to-DC converter circuit is constructed as described above, the addition signal
DC signal Vo, which is the final converted output signal from the waveform in (f)
In order to obtain the waveform of, it is necessary to provide the averaging circuit 6 equipped with a filter having a sufficiently large time constant. As a result,
The response of the conversion circuit becomes low, and when the frequency fi of the AC signal Fi fluctuates at a high speed, the conversion function cannot follow and accurate output characteristics cannot be obtained.

The present invention has been made to solve the above problems, and provides a frequency-to-DC conversion circuit that exhibits high responsiveness and obtains accurate conversion characteristics even when the frequency fluctuates rapidly. The purpose is to get.

[0010]

The frequency according to the present invention
The DC conversion circuit is an oscillator that generates a clock signal of a predetermined frequency that is sufficiently higher than the frequency of the AC signal, a waveform shaping circuit that outputs only the positive or negative polarity of the AC signal, and an output of this waveform shaping circuit. At the rising edge , counting of the clock signal is started and the output of the waveform shaping circuit
A first counter that resets the count at the fall, when the output of the first counter reaches a first set value corresponding to the conversion target upper limit frequency of the AC signal, or
When the output of the first counter is reset, an operation stop signal for stopping the operation of the first counter is output to output the wave.
When the output of the shape shaping circuit falls, the next rising edge of the clock signal
A first hold circuit that resets the operation stop signal when rising , a count of the clock signal that starts from zero when the operation stop signal rises, and a count when the operation stop signal falls.
Second counter to stop the count, stops the second counter output operation of the second of said second counter when it is set value corresponding to the lower limit difference on the converted frequency of the AC signal of this A second hold circuit for causing the second hold circuit , and the second hold circuit
E Bei conversion circuit for converting the output of the counter into a DC signal
It is a thing.

As means for obtaining a DC signal from the output of the second counter, a D / A converter for converting the output of the second counter into an analog quantity, and inverting the output polarity of this D / A converter. An inverting circuit, a bias circuit that outputs a positive bias value having the same absolute value as the negative maximum value of the output of the inverting circuit, an adding circuit that adds the outputs of the inverting circuit and the bias circuit, and the addition An averaging circuit that averages the output of the circuit and outputs it as a DC signal may be provided.

[0012]

The second counter counts the clock signal generated in the time width corresponding to the difference between the half width of the AC signal to be converted and the half width of the upper limit frequency to be converted. , Its output follows with a half cycle delay depending on the frequency of the AC signal. However, when the frequency becomes equal to or lower than the lower limit frequency to be converted, the second hold circuit operates, the counting operation of the second counter is stopped, and its output becomes constant. Further, the DC signal changes linearly with respect to the frequency, and high responsiveness is maintained without requiring a filter with a large time constant in the averaging circuit.

[0013]

1 is a circuit diagram showing the structure of a frequency-to-DC converter circuit according to an embodiment of the present invention. In the figure, 7
Is a waveform shaping circuit that outputs only a positive half cycle of the AC signal Fi, 8 is an oscillator that generates a clock signal Sc of a predetermined frequency fc that is sufficiently higher than the frequency fi of the AC signal Fi, and 9 is an output of the waveform shaping circuit 7. The clock signal Sc starts counting at the rising edge, and the output of the waveform shaping circuit 7 falls
The first counter 10 resets the count when the counter reaches the first set value C1 which is the count number corresponding to a half cycle of the upper limit frequency fmax, or the first counter 10. The output of 9 was reset
Delivery waveform shaping operation stop No. Tomeshin the first counter 9 when
The rise of the next clock signal Sc when the output of the circuit 7 falls
First holding circuit for resetting the Ride the operation stop signal, 11 the operation stop No. Tomeshin from the first hold circuit 10
2 is a second counter which starts counting the clock signal Sc from zero at the rising edge of the counter and stops counting at the falling edge of the operation stop signal. The output of the second counter 11 is the upper and lower limit difference (fmax) of the conversion target frequency. -Fmin) A second hold circuit that sends an operation stop signal to the second counter 11 when it reaches a second set value C2 that is a count number corresponding to a half cycle, and 13 is the second counter 11 D / A converter for converting the digital output of D into an analog quantity, 14 is an inverting circuit for inverting the output polarity of the D / A converter 13, 1
Reference numeral 5 denotes a bias circuit, which outputs a positive polarity bias value having the same negative absolute maximum value and absolute value of the output of the inverting circuit 14, that is, a value corresponding to the second set value. Reference numeral 16 is an adder circuit for adding the inverted signal (f) from the inverter circuit 14 and the bias value from the bias circuit 15, and 17 is an adder circuit 1
6 is an averaging circuit for averaging the outputs of 6.

Next, the operation will be described with reference to the time chart shown in FIG. It should be noted that (a) to (h) in the figure respectively represent the signal waveforms of the corresponding portions shown in FIG. First,
When the AC signal Fi shown in Fig. 2 (a) is input, the waveform shaping circuit 7 outputs only a positive half cycle signal (b)
Becomes In the figure, T indicates the time width of one cycle of the AC signal Fi, and Th indicates the time width of the output signal of the waveform shaping circuit 7.

The first counter 9 starts the counting operation at the rising edge of the output signal (b), and when the counted number reaches the first set value C1 (time width T1 up to this time), the first hold circuit 10 is started. Outputs the first hold signal (c)
Counter 9 stops its counting operation, and at the same time the second counter
The counter 11 starts the counting operation from zero and outputs the second count signal (d). The second counter 11 has a second count value C2 (time width T up to this time T2).
When 2) is reached, the second hold circuit 12 outputs the second hold signal and the second counter 11 stops its counting operation. Thereafter, until the reset by the first hold signal (c), Hold the output.

Therefore, as shown in FIG. 2, fi <fmin
In the range of (Th-T1)> T2, the second counter signal (d) rises to the level of C2, but fmin <
Since (Th-T1) <T2 in the range of fi <fmax, the signal (b) from the waveform shaping circuit 7 is interrupted by the time the second count signal (d) reaches the level of C2, and then reset. Hold that value until The range of fi> fmax
In the box, the count number of the first counter 9 is the first set value.
Since the output of the waveform shaping circuit 7 falls until reaching C1,
At this point, the first counter 9 resets the count.
You. When the first counter 9 is reset, the first
The field circuit 10 outputs the first hold signal (c).
At the next rising edge of the clock signal Sc, the first hold signal
No. (c) is reset. As a result, the second counter 1
1 starts counting from zero at the fall of the waveform shaping circuit 7
However, after that, the rising of the next clock signal Sc that is almost instantaneously occurs.
Stop counting when going up. Therefore, the second count signal
No. (d), as shown in FIG.
Will be retained.

After that, the second counter signal (d) is D / A.
It is converted into an analog quantity by the converter 13, and further, the inverting circuit 14
After the polarity is inverted at, it is added with the bias value and becomes the addition signal (g). As a result of performing the inversion and bias operations in this way, the averaging circuit 17 need only have a very small time constant, and as can be seen from the waveforms (e) to (h) in FIG. 2, the AC signal Fi frequency fi The DC signal Vo follows the fluctuation of within a half cycle and has an output value proportional to the difference from the lower limit frequency fmin.

Specific examples of each numerical value are as follows. The center frequency fo of the frequency fi of the AC signal Fi is 60 Hz, and the upper limit value fmax of the conversion target frequency is 61.2H.
z and the lower limit value fmin are 58.8 Hz. When the frequency fc of the clock signal Sc is 0.768 MHz, the first set value C1 (count number) is 6272 and the second set value C2 is 256.

When the output of the D / A converter 13 with respect to the set value C2 is + 10V (volt), the final DC signal Vo is: fi <fmin Vo = 0V fmin ≦ fi ≦ fmin Vo = 0 to 10V ( In proportion to fi-fmin), fi> fmax Vo = 10V. However, in the above circuit, the time width, which is the reciprocal of the frequency, is counted and the DC signal is obtained based on this count, so there is some error in the proportional relationship with the frequency, but it is a sufficiently small value. There is no problem in practical use.

[0020]

As described above, the present invention includes the predetermined oscillator, the waveform shaping circuit, the first counter, the first hold circuit, the second counter, and the second hold circuit. A highly responsive DC signal that follows in (1) can be obtained from the output of the second counter.

Further, in the case where a predetermined D / A converter, an inverting circuit, a bias circuit, an adding circuit and an averaging circuit are provided, a direct current which linearly changes with respect to the frequency of the AC signal in the range of the frequency to be converted. The signal is obtained. Further, since the time constant of the averaging circuit can be reduced, high responsiveness to frequency fluctuation is maintained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a frequency-DC conversion circuit according to an embodiment of the present invention.

FIG. 2 is a time chart explaining the operation of the circuit of FIG.

FIG. 3 is a circuit diagram showing a configuration of a conventional frequency-DC conversion circuit.

FIG. 4 is a time chart explaining the operation of the circuit of FIG.

FIG. 5 is a characteristic diagram showing the relationship between the voltage of a DC signal and the frequency of an AC signal.

[Explanation of symbols]

7 is a waveform shaping circuit, 8 is an oscillator, 9 is a first counter,
10 is a first hold circuit, 11 is a second counter, 1
2 is a second hold circuit, 13 is a D / A converter, 14 is an inverting circuit, 15 is a bias circuit, 16 is an adding circuit, 17
Is an averaging circuit, Fi is an AC signal, fi is a frequency of the AC signal Fi, fmax and fmin are upper and lower limit frequencies to be converted, Vo is a DC signal, Sc is a clock signal, and C1 and C2 are first and second, respectively. This is the second set value.

Claims (2)

(57) [Claims] 1. A clock signal having a predetermined frequency that is sufficiently higher than the frequency of the AC signal, in the case of converting an input AC signal into a DC signal that changes according to the frequency within a predetermined frequency range and outputting the DC signal. , A waveform shaping circuit that outputs only the positive or negative polarity of the AC signal, a count of the clock signal is started at the rising edge of the output of the waveform shaping circuit, and a falling edge of the output of the waveform shaping circuit. Count in
A first counter that resets the output of the first counter when the output of the first counter reaches a first set value corresponding to the conversion target upper limit frequency of the AC signal or when the output of the first counter.
When the force is reset, an operation stop signal for stopping the operation of the first counter is output to output the waveform shaping circuit.
The operation stops at the next rising edge of the clock signal
First hold circuit for resetting stop signal , operation stop
<br/> second counter stops counting at the falling edge of the to <br/> starts from zero count of the clock signal at the rising edge of the stop signal the operation stop signal, the output of the second counter this is the A second hold circuit that stops the operation of the second counter when the second set value corresponding to the difference between the upper and lower limits of the conversion target frequency of the AC signal is reached , and the output of the second counter
DC converter - frequency, characterized in that example Bei conversion circuit for converting the DC signal. 2. A D / A converter for converting the output of the second counter into an analog quantity, an inverting circuit for inverting the output polarity of the D / A converter, and a maximum negative polarity value of the output of the inverting circuit. A bias circuit that outputs a positive bias value having the same absolute value, an adder circuit that adds the outputs of the inversion circuit and the bias circuit, and an averaging circuit that averages the outputs of the adder circuit and outputs the DC signal. The frequency-to-DC converter circuit according to claim 1, further comprising: