JP2687493B2 - Surface mount structure of semiconductor device - Google Patents
Surface mount structure of semiconductor deviceInfo
- Publication number
- JP2687493B2 JP2687493B2 JP63262887A JP26288788A JP2687493B2 JP 2687493 B2 JP2687493 B2 JP 2687493B2 JP 63262887 A JP63262887 A JP 63262887A JP 26288788 A JP26288788 A JP 26288788A JP 2687493 B2 JP2687493 B2 JP 2687493B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- flat
- pad
- leads
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
- H01L23/49551—Cross section geometry characterised by bent parts
- H01L23/49555—Cross section geometry characterised by bent parts the bent parts being the outer leads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
- H05K3/3426—Leaded components characterised by the leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Geometry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はフラットパッケージ形IC等の半導体装置をプ
リント基板上に半田付けする際の半導体装置の表面実装
構造に関する。The present invention relates to a surface mounting structure for a semiconductor device when a semiconductor device such as a flat package type IC is soldered onto a printed board.
〔従来の技術〕 従来の表面実装用フラットパッケージ形IC（以下単に
フラットICという）はリードが複数並設されており、こ
の各リードにはプリント基板上のパッドに半田付けされ
る平坦部がそれぞれ形成されている。これを図によって
説明する。[Prior Art] A conventional flat package IC for surface mounting (hereinafter simply referred to as a flat IC) has a plurality of leads arranged side by side. Each of these leads has a flat portion to be soldered to a pad on a printed circuit board. Has been formed. This will be described with reference to the drawings.
第６図は従来のこの種のフラットICがプリント基板上
に表面実装された状態を示す斜視図、第７図は従来のフ
ラットICの半田付け部を拡大して示す斜視図である。こ
れらの図において、１はフラットIC本体を示し、２はリ
ードを示す。このリード２は前記フラットIC本体１の側
部に突設されており、フラットIC本体１の四方に複数本
並設されている。また、このリード２は基板2aと先端2b
とでは段差がつくようそれぞれ折曲げ形成され、先端2b
をフラットIC本体１の背面と平行に形成することによっ
て半田付け用平坦部2cが設けられている。３はプリント
基板を示し、このプリント基板３上には前記リード２が
半田付けされるパッド４が設けられている。このパッド
４は前記リード２の配置位置と対応するようプリント基
板３上に複数並設されており、プリント基板３上に形成
された配線（図示せず）を介して他の電子装置（図示せ
ず）等にそれぞれ接続されている。FIG. 6 is a perspective view showing a state where a conventional flat IC of this type is surface-mounted on a printed circuit board, and FIG. 7 is an enlarged perspective view showing a soldering portion of the conventional flat IC. In these figures, 1 indicates a flat IC body and 2 indicates leads. The leads 2 are projectingly provided on the side portions of the flat IC body 1, and a plurality of leads 2 are provided in parallel on four sides of the flat IC body 1. In addition, the lead 2 has a substrate 2a and a tip 2b.
And are bent to form a step, and the tip 2b
Is formed in parallel with the back surface of the flat IC body 1 to provide a flat portion 2c for soldering. Reference numeral 3 denotes a printed circuit board, and pads 4 to which the leads 2 are soldered are provided on the printed circuit board 3. A plurality of pads 4 are arranged side by side on the printed circuit board 3 so as to correspond to the positions where the leads 2 are arranged, and other electronic devices (not shown) are provided via wiring (not shown) formed on the printed circuit board 3. No.) etc. are connected respectively.
このように構成されたフラットICをプリント基板３上
に実装するには、通常は半田付け装置（図示せず）等の
自動機によって各リード２の平坦部2cと各パッド４とが
面接触されるように重ね合せ、この状態で両者を半田付
けして行われていた。In order to mount the flat IC configured as above on the printed circuit board 3, the flat portion 2c of each lead 2 and each pad 4 are normally brought into surface contact with each other by an automatic machine such as a soldering device (not shown). It was carried out by stacking them together and soldering them in this state.
しかるに、このように構成された従来の半導体装置の
表面実装構造においては、例えば自動機によらず人手に
よってフラットICをプリント基板３上に半田付けする場
合には、リード２の本数が多いため各リード２をパッド
４に正確に位置決めするのに時間がかかる。これはリー
ド２の本数が多くなればなるほど著しい。さらに、リー
ド２をパッド４上に面接触させた状態で保持させなけれ
ばならないため、半田付け中に両者がずれやすい。この
ため、この種のフラットICを手作業によって実装させる
と半田付け作業に時間がかかり過ぎ、しかも、自動機を
使用した際の搭載状態に較べて搭載状態が安定しないと
いう問題があった。However, in the conventional surface mounting structure of the semiconductor device having such a structure, when the flat IC is soldered onto the printed circuit board 3 by hand without using an automatic machine, the number of leads 2 is large, and therefore, It takes time to accurately position the lead 2 on the pad 4. This becomes remarkable as the number of leads 2 increases. Further, since the lead 2 has to be held in a state of being in surface contact with the pad 4, the two are easily displaced during soldering. For this reason, when this type of flat IC is mounted by hand, there is a problem that the soldering work takes too much time and the mounting state is not stable as compared with the mounting state when an automatic machine is used.
本発明に係る半導体装置の表面実装構造は、半田付け
部に基板内部まで延在する凹部を形成するとともに、半
導体装置のリードに前記凹に嵌合しかつ基板に係合する
位置決め用突起を設け、これら凹部および突起を一半導
体装置に対して複数設けたものである。In the surface mounting structure of the semiconductor device according to the present invention, a recess extending to the inside of the substrate is formed in the soldering portion, and a positioning protrusion that fits in the recess and engages with the substrate is provided in the lead of the semiconductor device. A plurality of these recesses and protrusions are provided for one semiconductor device.
半田付け用パッドの凹部内にリードの突起を臨ませて
リードとパッドとを対接させることにより、半導体装置
が位置決めされ、半導体装置を基板上において正確な位
置に配置することができる。また、位置決め状態では、
突起が半田付け用パッドおよび基板に当接するために半
導体装置は横方向へずれにくくなる。The semiconductor device is positioned by allowing the protrusion of the lead to face the recess of the soldering pad so that the lead and the pad are in contact with each other, and the semiconductor device can be arranged at an accurate position on the substrate. In the positioning state,
Since the projections come into contact with the soldering pads and the substrate, the semiconductor device is less likely to be displaced laterally.
以下、本発明の一実施例を第１図ないし第３図によっ
て詳細に説明する。Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS.
第１図は本発明を採用したフラットICの実装状態を示
す斜視図、第２図は同じく実装状態を示す断面図、第３
図は要部を拡大して示す斜視図である。これらの図にお
いて前記第６図および第７図で説明したものと同一もし
くは同等部材については同一符号を付し、ここにおいて
詳細な説明は省略する。これらの図において、11は位置
決め用突起を示し、この突起11はリード２の平坦部2cに
裏側へ向かって突設されており、フラットIC本体１の四
隅に配置されたリード２に形成されている。12はリード
２とパッド４とを位置決めするための位置決め用の窪み
を示し、この窪み12は前記突起11が嵌合しかつプリント
基板３に係合するようにプリント基板３を凹ませて形成
されている。13は前記突起11が臨む貫通孔を示し、この
貫通孔13は、パッド４における前記窪み12と対応する部
位に形成されている。すなわち、前記窪み12および前記
貫通孔13によってリード２を位置決めするための凹部が
形成されることになる。また、この凹部は、突起11を有
するリード２が半田付けされる部位、すなわち、フラッ
トIC本体１の四隅と対応する部位に配置されたパッド４
に形成されている。FIG. 1 is a perspective view showing a mounted state of a flat IC adopting the present invention, FIG. 2 is a sectional view showing the mounted state of the same, and FIG.
The figure is a perspective view showing an enlarged main part. In these figures, the same or similar members as those described in FIGS. 6 and 7 are designated by the same reference numerals, and detailed description thereof will be omitted. In these drawings, reference numeral 11 denotes a positioning protrusion, and the protrusion 11 is provided on the flat portion 2c of the lead 2 so as to project toward the back side, and is formed on the leads 2 arranged at the four corners of the flat IC body 1. There is. Reference numeral 12 denotes a positioning recess for positioning the lead 2 and the pad 4, and the recess 12 is formed by recessing the printed board 3 so that the projection 11 fits and engages with the printed board 3. ing. Reference numeral 13 denotes a through hole which the projection 11 faces, and the through hole 13 is formed at a portion of the pad 4 corresponding to the recess 12. That is, the recess 12 and the through hole 13 form a recess for positioning the lead 2. Further, the recesses are the pads 4 arranged at the portions to which the leads 2 having the protrusions 11 are soldered, that is, the portions corresponding to the four corners of the flat IC body 1.
Is formed.
このような突起11を備えたフラットICをプリント基板
３上で位置決めするには、突起11がパッド４の貫通孔13
内に臨むように各リード２とパッド４とを対接させるこ
とによって行われる。この際、フラットICの四隅におい
てリード２とパッド４とが係合されるため、フラットIC
は正確に位置決めされると共に、横方向へずれにくくな
る。In order to position the flat IC having the protrusions 11 on the printed circuit board 3, the protrusions 11 are formed in the through holes 13 of the pad 4.
This is performed by bringing the leads 2 and the pads 4 into contact with each other so as to face the inside. At this time, since the lead 2 and the pad 4 are engaged at the four corners of the flat IC, the flat IC
Is accurately positioned and is less likely to shift laterally.
なお、前記実施例では位置決め用の突起11および凹部
をフラットICの四隅に対応させて設けた例を示したが、
本発明はこのような限定にとらわれることなく、突起11
および凹部は全てのリード２およびパッド４に設けても
よく、また全てのリード２およびパッド４には設けずに
一つのフラットICに対して２〜３箇所設ける場合には、
なるべく離間させて配設することが望ましい。また、前
記実施例ではリード２が四方へ突出されたフラットICに
ついて説明したが、本発明は、リードが二方向へ突出さ
れたフラットICに採用してもよいということはいうまで
もない。In the above embodiment, the positioning projections 11 and the recesses are provided corresponding to the four corners of the flat IC.
The present invention is not limited to such a limitation, and the projection 11
And the recesses may be provided in all the leads 2 and the pads 4, or when not provided in all the leads 2 and the pads 4 and provided in two to three places for one flat IC,
It is desirable to arrange them as far apart as possible. In addition, although the flat IC in which the leads 2 are projected in four directions has been described in the above embodiment, it goes without saying that the present invention may be adopted in a flat IC in which the leads are projected in two directions.
また、前記実施例では位置決め用の凹部をプリント基
板３の窪み12とパッド４の貫通孔13によって形成した例
を示したが、第４図および第５図に示すように形成する
こともできる。Further, in the above-mentioned embodiment, the example in which the positioning recess is formed by the recess 12 of the printed board 3 and the through hole 13 of the pad 4 has been shown, but it may be formed as shown in FIGS. 4 and 5.
第４図および第５図は他の実施例を示すプリント基板
の断面図で、第４図においてはリード（図示せず）の突
起が挿入される位置決め用の凹部14がパッド４に形成さ
れている。この凹部14を形成するには、プリント基板３
に設けられた窪み12上にパッド４を重ねて設けることに
よって形成したり、プリント基板３上にパッド４を予め
設けておき、このパッド４をプリント基板３側へ機械的
に減り込ますことによって形成したりする方法が考えら
れる。また、第５図に示すプリント基板３においては透
孔15が穿設されており、パッド４にはこの透孔15と対応
する貫通孔16が設けられている。この第５図に示すプリ
ント基板３においては、透孔15および貫通孔16によっ
て、リード（図示せず）の突起が挿入される位置決め用
凹部が形成されることになる。前記第４図および第５図
に示すようにプリント基板３に位置決め用凹部を形成し
ても前記実施例と同様の効果が得られる。4 and 5 are sectional views of a printed circuit board showing another embodiment. In FIG. 4, a recess 14 for positioning into which a protrusion of a lead (not shown) is inserted is formed in the pad 4. There is. To form the recess 14, the printed circuit board 3
By forming the pad 4 by stacking it on the recess 12 provided in the, or by previously providing the pad 4 on the printed circuit board 3 and mechanically reducing the pad 4 to the printed circuit board 3 side. A method of forming or the like can be considered. Further, the printed board 3 shown in FIG. 5 has a through hole 15 formed therein, and the pad 4 is provided with a through hole 16 corresponding to the through hole 15. In the printed circuit board 3 shown in FIG. 5, the through hole 15 and the through hole 16 form a positioning recess into which a protrusion of a lead (not shown) is inserted. Even if the positioning recess is formed in the printed circuit board 3 as shown in FIGS. 4 and 5, the same effect as in the above embodiment can be obtained.
以上説明したように本発明によれば、半田付け部に基
板内部まで延在する凹部を形成するとともに、半導体装
置のリードに前記凹部に嵌合しかつ基板に係合する位置
決め用突起を設け、これら凹部および突起を一半導体装
置に対して複数設けたため、半田付け用パッドの凹部内
にリードの突起を臨ませてリードとパッドとを対接させ
ることにより、半導体装置が位置決めされ、半導体装置
を基板上において正確な位置に配置することができる。
また、位置決め状態では、突起が半田付け用パッドおよ
び基板に当接するために半導体装置は横方向へずれにく
くなる。したがって、本発明に係る半導体装置の表面実
装構造を採用すると、半導体装置を手作業にて基板上に
半田付けする場合に半導体装置を容易にしかも確実に位
置決めすることができるから、作業時間が短縮されかつ
自動機で搭載されたものと同様に安定した状態で半導体
装置を基板上に搭載させることができる。As described above, according to the present invention, a recess extending to the inside of the board is formed in the soldering portion, and a lead for the semiconductor device is provided with a positioning projection that fits in the recess and engages with the board. Since a plurality of these recesses and protrusions are provided for one semiconductor device, the semiconductor device is positioned by placing the lead and the pad in contact with each other so that the protrusion of the lead faces the recess of the soldering pad. It can be placed at a precise position on the substrate.
Further, in the positioned state, the semiconductor device is less likely to be displaced in the lateral direction because the protrusions come into contact with the soldering pad and the substrate. Therefore, when the surface mounting structure of the semiconductor device according to the present invention is adopted, when the semiconductor device is manually soldered onto the substrate, the semiconductor device can be positioned easily and surely, and the working time is shortened. The semiconductor device can be mounted on the substrate in a stable state like the one mounted by the automatic machine.
第１図は本発明を採用したフラットICの実装状態を示す
斜視図、第２図は同じく実装状態を示す断面図、第３図
は要部を拡大して示す斜視図、第４図は他の実施例を示
すプリント基板の断面図、第５図は同じく他の実施例を
示すプリント基板の断面図、第６図は従来のフラットIC
がプリント基板上に表面実装された状態を示す斜視図、
第７図は従来のフラットICの半田付け部を拡大して示す
斜視図である。 １……フラットIC本体、２……リード、３……プリント
基板、４……パッド、11……突起、12……窪み、13,16
……貫通孔、14……凹部、15……透孔。FIG. 1 is a perspective view showing a mounted state of a flat IC adopting the present invention, FIG. 2 is a sectional view showing the same mounted state, FIG. 3 is an enlarged perspective view of an essential part, and FIG. FIG. 5 is a sectional view of a printed circuit board showing another embodiment, FIG. 5 is a sectional view of a printed circuit board showing another embodiment, and FIG. 6 is a conventional flat IC.
Is a perspective view showing a state of being surface-mounted on a printed circuit board,
FIG. 7 is an enlarged perspective view showing a soldering portion of a conventional flat IC. 1 ... Flat IC body, 2 ... Lead, 3 ... Printed circuit board, 4 ... Pad, 11 ... Protrusion, 12 ... Dimple, 13,16
...... Through hole, 14 ...... Concave part, 15 ...... Through hole.
Claims (1)
田付け用パッドにリードを半田付けして実装される半導
体装置の表面実装構造において、半田付け部に基板内部
まで延在する凹部を形成するとともに、半導体装置のリ
ードに前記凹部に嵌合しかつ基板に係合する位置決め用
突起を設け、これら凹部および突起を一半導体装置に対
して複数設けたことを特徴とする半導体装置の表面実装
構造。1. In a surface mounting structure of a semiconductor device in which a semiconductor device having a plurality of leads is mounted by soldering leads to a soldering pad of a substrate, a recess extending to the inside of the substrate is formed in a soldering portion. At the same time, the leads of the semiconductor device are provided with positioning protrusions that fit into the recesses and engage with the substrate, and a plurality of these recesses and protrusions are provided for one semiconductor device. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63262887A JP2687493B2 (en) | 1988-10-20 | 1988-10-20 | Surface mount structure of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63262887A JP2687493B2 (en) | 1988-10-20 | 1988-10-20 | Surface mount structure of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02111093A JPH02111093A (en) | 1990-04-24 |
| JP2687493B2 true JP2687493B2 (en) | 1997-12-08 |
Family
ID=17382000
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63262887A Expired - Lifetime JP2687493B2 (en) | 1988-10-20 | 1988-10-20 | Surface mount structure of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2687493B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2979715B2 (en) * | 1991-05-02 | 1999-11-15 | 三菱電機株式会社 | Semiconductor pressure sensor |
| US5517752A (en) * | 1992-05-13 | 1996-05-21 | Fujitsu Limited | Method of connecting a pressure-connector terminal of a device with a terminal electrode of a substrate |
| US5313368A (en) * | 1993-02-02 | 1994-05-17 | The Whitaker Corporation | Electrical connections between printed circuit boards and integrated circuits surface mounted thereon |
| JPH09283901A (en) * | 1996-04-12 | 1997-10-31 | Nec Corp | Method and structure for mounting of surface mounting lsi package |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54158674A (en) * | 1978-06-05 | 1979-12-14 | Fujitsu Ltd | Method of positioning component on printed board |
-
1988
- 1988-10-20 JP JP63262887A patent/JP2687493B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02111093A (en) | 1990-04-24 |
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