JP2682037B2 - DRAM access control device - Google Patents

Description

The present invention relates to a DRAM access control device for controlling DRAM access in a fast page mode.

<Prior Art> FIG. 3 shows a time chart in which the microprocessor MPU (particularly 68020) accesses the DRAM in the fast page mode.

Fast page mode is when the row address of the previous cycle and the row address of the current cycle match (hit ▲ ▼ “L”), the row address
DRAM with strobe signal ▲ ▼ remaining "L" and only column address strobe signal ▲ ▼ remaining "L"
It refers to the mode to access.

Now, in the time chart of FIG. 3, the row address (row) is latched at "A", and the row address is "A" (hit ▲ in the first cycle C1 in this figure).
▼ “L”), row address strobe signal ▲ ▼ “L” remains unchanged, column address (col =
Column address strobe signal for B) ▼
Only ▲ becomes “L” and access is performed.

Similarly in the next cycle C2, the row address is "A" and the row address strobe signal ▲ ▼ is "L".
As it is, the column address strobe signal ▼ ▲ becomes “L” for the column address “C”, and the access is performed.

In this way, when the row addresses match each other, only the column address is used for access, so high-speed access is possible.

<Problems to be Solved by the Invention> In the time chart of FIG. 3, it is assumed that the row address changes from "A" to "D". This cycle is designated as C3.

The value of the row address is constantly monitored by the comparator, and the change in the value changes the comparator output ▲ ▼ from "L" (hit) to "H" (miss). This cancels the fast page mode until now (▲
▼ "H"), and access must be started with a new row address and column address.

That is, when the comparator output ▲ ▼ becomes "H",
Sequencer at the falling edge of clock CLK (2) ▲
▼ "H" is detected and fast page mode ▲
▼ "H" (release).

However, at this time, the period of clock CLK (1) (T1)
When the address strobe signal ▲ ▼ from the microprocessor MPU becomes active, the row address strobe signal ▲ ▼ is originally negated and access is made by a new row address as shown in the time chart of FIG. Must start, but hit ▲ ▼ “L”, fast page mode ▲
▼ "L", row address strobe signal ▲
▼ Previous address (row address A) by "L"
In some cases, an erroneous access was started, and the data strobe acknowledge signal ▲ ▼ "L" (shown by the dotted line) apparently ended the access.

The present invention has been made to solve the above problems, and accesses in the fast page mode.
It is an object of the present invention to realize a DRAM control device that continues its operation smoothly even when a mistake occurs and does not malfunction.

<Means for Solving the Problems> In order to solve the above problems, the present invention stretches the access start signal ▲ ▼ (External Cycle Start) output from the microprocessor (68020) at the start of access, and misses. When this signal occurs, the signal from the microprocessor is not accepted while this signal is active.

 The specific configuration of the present invention is as follows.

That is, it has a comparator for comparing the row address of the previous cycle and the row address of the present cycle, and when this comparator outputs a match, only the column address strobe signal is output while the row address strobe signal is being output. In the fast page mode DRAM access control device that outputs the data to access the DRAM, the system clock and the access start signal ▲ ▼
And a signal generating means for extending the access start signal ▲ ▼ by a half period of the system clock to generate a new signal ▲ ▼, and operating while the signal ▲ ▼ is "L". A sequencer having a logical configuration that cannot be provided is provided.
It is a DRAM access control device.

<Operation> The DRAM access control device of the present invention extends the access start signal ▲ ▼ by half a clock, ignores the address strobe signal ▲ ▼ even if it is active during this period, and outputs the comparator output ▲ ▼ "H". "Fast page mode ▲ ▼" H "as
Access is newly started with a row address and a column address.

<Embodiment> FIG. 1 shows the configuration of a DRAM access control device embodying the present invention.

In this figure, AB is an address bus, CB is a control signal bus, 1 is a latch for latching a row address, 2 is a row address given this time, and a row address latched in a latch 1 by previous access. Compare and match (hit; ▲ ▼ “L”) Mismatch (miss; ▲ ▼ “H”)
Comparator that outputs the
▼ and various control signals on the control signal bus CB are input to the DRAM controller for row address strobe signal ▲ ▼ and column address strobe signal ▼
A sequencer that outputs a latch signal ▲ ▼ to ▲, latch 1.

The above is the same structure as the conventional DRAM access control device, and the feature of the present invention is that the access start signal ▲ ▼ on the control signal bus CB is extended by a half clock of the system clock CLK to output a signal ▲ ▼. This is because the flip-flop circuit 4 is provided and these signals {circle around (1)} and signal {circle over (3)} are input to the sequencer 3. The signal ▲ ▼ is subjected to an OR operation in the sequencer 3 with the access start signal ▲ ▼.

Now, the operation of the DRAM access control device of the present invention thus constructed will be described with reference to the configuration diagram of FIG. 1 and the time chart of FIG.

In FIG. 1, a microprocessor (not shown) sends an access start signal ▲ ▼ to the control signal bus CB at the start of access, and the D flip-flop circuit 4 extends this signal by half a clock to generate a signal ▲ ▼. And give it to the sequencer 3. Sequencer 3 uses this signal ▲
Enter ▼ and ▲ ▼.

Now, the row address of the previous access is latched by the latch 1 and is compared with the row address given this time by the comparator 2. If they match, ▲ ▼
At "L", the sequencer 3 keeps the row address strobe signal ▲ ▼ "L" and sets the column address strobe signal ▼ ▲ to "L".

In FIG. 2, the cycle CI and the cycle C2 are exactly the same as the conventional cycles C1 and C2 shown in FIG. 3, and the row address strobe signal ▲ at the row address “A”.
▼ Column address strobe with "L" ▼
▲ Access by "L".

Now, in the cycle C3, when the given row address changes from "A" to "D", the comparator 2 output
▼ becomes “H” (miss).

On the other hand, the microprocessor first outputs the access start signal ▲ ▼ “L”, and then immediately outputs the address strobe signal AS regardless of hit / miss. According to the conventional device, a malfunction occurs due to the timing at which the address strobe signal ▲ ▼ is output, but in the device of the present invention, the access start signal ▲
A signal obtained by extending ▼ by half a clock T2 ▲
Since ▼ is given to the sequencer 3, the address strobe signal ▲ ▼ output from the microprocessor during this period T2 cannot be accepted by the sequencer 3. That is, the sequencer 3 configures logic so that it cannot operate with the signal "L", and apparently ignores the signal from the microprocessor so as not to affect the access operation.

Therefore, the sequencer 3 detects the miss (▲ ▼ “H”) by the falling edge of the clock CLK (2) and releases the fast page mode (FA ▲ ▼).
At the same time as "H"), the row address strobe signal ▲ ▼ is negated ("H") to prohibit the output of the data strobe acknowledge signal ▲ ▼ and the column address strobe signal ▲ ▼. Also,
The latch signal ▲ ▼ is output and the new row address “D” is latched in the latch 1. When the latch signal ▲ ▼ is active (“L”), the operation of the comparator 2 is prohibited.

When the latch signal ▲ ▼ is negated (“H”),
The comparator 2 operates and its output becomes ▲ ▼ "L". Next, the sequencer 3 makes a DRAM by the above signal transition.
After securing the pre-charge time of, the row address strobe signal ▲ ▼ is asserted to "L", and after 1 clock elapses, the fast page mode ▲
Assert ▼ (“L”).

Then, the sequencer 3 outputs the data strobe acknowledge signal ▲ ▼ and the column address strobe signal ▲ ▼ to execute the access operation.

As described above, the access start signal ▲ ▼ from the microprocessor is delayed by half a clock, and during that time, even if the address strobe signal ▲ ▼ becomes active, the sequencer ignores this signal and adversely affects the access operation. There is no.

<Effects of the Invention> As described above, the DRAM access control circuit of the present invention extends the access start signal ▲ ▼ by half a clock and ignores it even if the address strobe signal ▲ ▼ becomes active during this period. And comparator output ▲
▼ Fast page mode F from "H" ▲
▼ A new row address and column
Since the access is started by the address, it is possible to realize the DRAM control device in which the access operation is smoothly continued even when a mistake occurs and the malfunction does not occur.

[Brief description of the drawings]

FIG. 1 is a block diagram of a DRAM access control device embodying the present invention, FIG. 2 is a time chart showing the operation of the present invention device, and FIG. 3 is a time chart showing the operation of a conventional device. 1 ... Latch, 2 ... Comparator, 3 ... Sequencer, 4 ... D flip-flop circuit, AB ... Address
Bus, CB ... Control signal bus.

Claims (1)

(57) [Claims] 1. A comparator for comparing a row address of a previous cycle with a row address of a present cycle, and when the comparator outputs a coincidence, a row address strobe signal is output and a column address In the fast page mode DRAM access control device that outputs only the strobe signal to access the DRAM, the system clock and the access start signal ▲
Signal generating means for inputting ▼ and extending the access start signal ▲ ▼ by a half period of the system clock to generate a new signal ▲ ▼.
A DRAM access control device provided with a sequencer having a logical configuration such that it cannot operate while the signal (5) is "L".