JP2678064B2 - Semiconductor resistance forming method - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a design method for mask layout of semiconductor resistors using a computer.

2. Description of the Related Art In recent years, semiconductor integrated circuits have become larger and larger, and there is an increasing demand for automatic design using a computer. A conventional automatic design method for mask layout using a computer will be described below.

In the conventional method, when the mask pattern of the resistor is automatically generated, the designer beforehand has information on the resistance (for example, the resistance value, the unit resistance value of the diffusion layer for the resistance, the resistance width, Design specifications (such as classification of series connection / parallel connection) are determined to create a circuit diagram, and the resistance pattern is faithfully generated based on the information extracted from the circuit diagram.

Problems to be Solved by the Invention In such a conventional method, the designer decides the design specification without considering the inconvenience in the mask layout.
If it is automatically designed according to the design specifications, the blank area where elements such as resistors and transistors are not arranged is unnecessarily increased, and the degree of integration is not necessarily high. Therefore, in order to increase the degree of integration, after automatic designing, the periphery including the location where the blank area is generated is specified, the resistance existing at that location is compared with the resistance on the circuit diagram, and the design specifications are set again. After reviewing and partially changing the specifications, it is necessary to perform automatic design again, and if there are still many blank areas, review the design specifications further and perform automatic design based on the revised design specifications. It took a long processing time to reach the final conclusion, such as once.

The present invention eliminates such inconvenience, and an object of the present invention is to provide a method for automatically selecting a resistance pattern suitable for a mask layout and automatically generating the resistance pattern in a short time.

Means for Solving the Problems A semiconductor resistance forming method of the present invention prepares a plurality of resistance patterns assumed in a mask layout, and preliminarily divides them into a standard group, a bent group, and a series group according to the resistance shape. A first step of grouping, and a second step of excluding a resistance pattern of a group that does not satisfy the shape setting condition from the plurality of resistance patterns
And, next, while setting a placement planned region where the placement of the semiconductor resistor is planned, the target resistance data of the basic pattern set to the target value on the same scale as the placement planned region is generated, and the target resistance data is generated. And a size of the planned placement region, and when the target resistance data is out of the planned placement region, a third step of excluding the resistance pattern of the standard form group including the basic form pattern, and subsequently, A fourth step of selecting a minimum resistance pattern from the remaining groups of resistance patterns and generating semiconductor resistance mask data.

Operation With the above configuration, the group of resistance patterns that do not satisfy the shape conditions and the group of resistance patterns that do not fit within the planned placement area are excluded from the many possible resistance patterns, and the remaining groups of resistance patterns are excluded. Since the smallest resistance pattern type is selected from the above, the semiconductor resistance mask pattern that meets the design specifications can be determined at high speed.

Example An example of the method for forming a semiconductor resistor according to the present invention will be described below with reference to the drawings. FIG. 1 is a plan view showing a basic pattern of a semiconductor resistor used in one embodiment,
2A to 2D are views for explaining the steps of one embodiment.

First, as shown in the plan view of FIG. 1, a large number of supposed resistance patterns 1 to 7 are prepared. Then, as shown in FIG. 2A, similar resistance patterns are collected to set a group. The standard group 9 is a group of the basic pattern 1 and the parallel patterns 2 and 3 in FIG.
The resistance of the standard group 9 is composed of a linear resistance having contact portions at both ends, and has a drawback that the distance from one contact portion to the other contact portion becomes long, but instead of high precision resistance. The value is obtained. However, if the same resistance value is obtained, it is disadvantageous in that the area required for integration becomes larger as the number of parallel connections increases,
The singular form (1) is the basic form.

Next, a group in which the series patterns 4 and 5 are collected is referred to as a series group 10, and the resistance of the series group 10 is a shape in which a plurality of linear resistances arranged so as to be folded back are connected in series. Instead of reducing the distance between the contact parts, a wide area is required. This kind of resistance is
As the number of contact portions increases, the value of the contact resistance is added, and the precision is slightly inferior to that of the standard group 9, and medium precision is obtained.

The group in which the folding pattern patterns 6 and 7 are collected is referred to as a folding group 8. The resistance of the folding group 8 is formed by folding back without providing a contact part in the middle, and a large resistance value can be obtained in a small area. There is. However, the presence of the bent portion deteriorates the accuracy of the resistance value, and the resistance value becomes low accuracy. Then, in the preparatory process, a large number of resistance patterns are formed according to the shapes, that is, the bending group 8, the standard group 9, and the serial group 10 in three groups.
Prepare the streets by grouping them in advance (Fig. 2 (a))
See).

Next, from the viewpoint of the required accuracy of the resistance value, those that do not satisfy the shape setting condition are excluded. In this example, in order to set the shape of the resistance, it is assumed that there is a shape setting condition of "the resistance cannot be bent". Then, the resistance patterns 6 and 7 included in the bending group 8 in FIG. 2A are excluded.

Next, a planned arrangement area 11 in which the semiconductor resistors are to be arranged is set (see FIG. 2B), and the size of the planned arrangement area 11 and the bent group 8 in FIG. 2A are set. The removed resistance patterns (the resistance patterns of groups 9 and 10) are compared with each other, and the resistance patterns in which the size of the pattern set to the target resistance value does not fit within the planned arrangement area 11 are excluded. At this time, the resistance data of the basic pattern 1 (target resistance data 12), which is set to the target resistance value on the same scale as the planned placement area 11, is generated (FIG. 2 (c)), and the planned placement area 11 is generated.
And the target resistance data 12 are compared. Then, since the target resistance data 12 extends beyond the planned arrangement area 11, the standard form group 9 including the basic form pattern 1 is excluded from the target, and as a result, the resistance patterns 4 and 5 of the series form group 10 remain.

Finally, when the resistance pattern having the smallest size is selected from the remaining resistance patterns 4 and 5 belonging to the series type group 10, the resistance pattern 4 in FIG. 2A is selected. Then, semiconductor resistance data is generated based on the resistance pattern 4, and final determination data 13 is obtained.

As mentioned above, among the many possible resistance patterns, those that do not meet the shape conditions and those that do not fit within the planned placement area are excluded, and the type of the minimum resistance pattern is selected. A mask pattern of a suitable semiconductor resistor can be determined at high speed.

It should be noted that the above-described embodiment exemplifies a procedure for processing at high speed, and it is needless to say that the final decision data similar to the above can be obtained even if the above-mentioned procedure is replaced, if efficiency is ignored.

EFFECTS OF THE INVENTION As described above, the present invention excludes ones that do not satisfy the shape condition and ones that do not fit within the planned arrangement region from among a large number of assumed resistance patterns, and determines the minimum resistance pattern type. Since the selection is made, the special effect that the mask pattern of the semiconductor resistor that meets the design specifications can be determined at high speed is achieved.

[Brief description of the drawings]

FIG. 1 is a plan view showing a basic pattern of a semiconductor resistor used in an embodiment of the method for forming a semiconductor resistor according to the present invention.
(A)-(d) is a figure for demonstrating the process of one Example. 1 …… Basic type (straight line type) pattern, 2,3 …… Parallel type pattern, 4,5 …… Series type pattern, 6,7 …… Bending type pattern, 8 …… Bending type group, 9 …… Standard group, 10 …… Series type group, 11 …… Schedule for arranging semiconductor resistors, 12 …… Target resistance data set to target value in basic type, 13 …… Final determination data of semiconductor resistors.

Claims (1)

(57) [Claims] 1. A first step of preparing a plurality of resistance patterns expected in a mask layout and grouping them in advance into a standard type group, a bent type group, and a series type group according to the resistance shape, and A second step of excluding a resistance pattern of a group that does not satisfy a shape setting condition from the plurality of resistance patterns; Generate target resistance data of the basic pattern set to the target value on the same scale as
A third step of comparing the sizes of the target resistance data and the planned placement region, and excluding the resistance patterns of the standard form group including the basic form pattern when the target resistance data extends from the planned placement region. Then, a fourth step of selecting a minimum resistance pattern from the remaining groups of resistance patterns and generating mask data of the semiconductor resistance.